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PCI: dwc: Expand maximum number of MSI IRQs from 32 to 256

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The Synopsys PCIe Root Complex supports up to MSI 256 IRQs distributed
over 8 controller registers, therefore the maximum number of MSI IRQs
can be changed to 256. The number of controllers can be calculated based
on the number of vectors used by the specific SoC driver.

Update the dwc host bridge driver maximum number of supported MSI
IRQs.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Niklas Cassel <niklas.cassel@axis.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Gustavo Pimentel 2018-03-06 11:54:55 +00:00 • committed by Lorenzo Pieralisi
parent 3f43ccc4ea
commit 1f319cb053
2 changed files with 11 additions and 11 deletions
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12
drivers/pci/dwc/pcie-designware-host.c
View file

@ -76,11 +76,13 @@ static struct msi_domain_info dw_pcie_msi_domain_info = {
/* MSI int handler */ /* MSI int handler */
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
{ {
u32 val;
int i, pos, irq; int i, pos, irq;
u32 val, num_ctrls;
irqreturn_t ret = IRQ_NONE; irqreturn_t ret = IRQ_NONE;
for (i = 0; i < MAX_MSI_CTRLS; i++) { num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
for (i = 0; i < num_ctrls; i++) {
dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
&val); &val);
if (!val) if (!val)
@ -639,13 +641,15 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
void dw_pcie_setup_rc(struct pcie_port *pp) void dw_pcie_setup_rc(struct pcie_port *pp)
{ {
u32 val, ctrl; u32 val, ctrl, num_ctrls;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
dw_pcie_setup(pci); dw_pcie_setup(pci);
num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
/* Initialize IRQ Status array */ /* Initialize IRQ Status array */
for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) for (ctrl = 0; ctrl < num_ctrls; ctrl++)
dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + (ctrl * 12), 4, dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + (ctrl * 12), 4,
&pp->irq_status[ctrl]); &pp->irq_status[ctrl]);
/* setup RC BARs */ /* setup RC BARs */

10
drivers/pci/dwc/pcie-designware.h
View file

@ -107,13 +107,9 @@
#define MSI_MESSAGE_DATA_32 0x58 #define MSI_MESSAGE_DATA_32 0x58
#define MSI_MESSAGE_DATA_64 0x5C #define MSI_MESSAGE_DATA_64 0x5C
/* #define MAX_MSI_IRQS 256
* Maximum number of MSI IRQs can be 256 per controller. But keep #define MAX_MSI_IRQS_PER_CTRL 32
* it 32 as of now. Probably we will never need more than 32. If needed, #define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)
* then increment it in multiple of 32.
*/
#define MAX_MSI_IRQS 32
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
#define MSI_DEF_NUM_VECTORS 32 #define MSI_DEF_NUM_VECTORS 32
/* Maximum number of inbound/outbound iATUs */ /* Maximum number of inbound/outbound iATUs */