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drm/amdgpu/gfx10: add updated register offsets for VGH

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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2020-09-01 12:20:17 -04:00
parent ad088550d2
commit 1ec743ac9f
1 changed files with 16 additions and 2 deletions
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18
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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@ -99,8 +99,22 @@
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
#define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
#define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
#define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f
#define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1
#define mmVGT_TF_RING_SIZE_Vangogh 0x224e
#define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1
#define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241
#define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1
#define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250
#define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1
#define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240
#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1
#define mmSPI_CONFIG_CNTL_Vangogh 0x2440
#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
#define mmCP_HYP_PFP_UCODE_ADDR 0x5814
#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1