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powerpc/mm/book3s-64: Clean up some obsolete or misleading comments

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Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Paul Mackerras 2016-02-22 13:41:12 +11:00 • committed by Michael Ellerman
parent 2527083cb8
commit 1ec3f93710
3 changed files with 12 additions and 14 deletions
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13
arch/powerpc/include/asm/book3s/64/hash.h
View file

@ -4,8 +4,7 @@
/* /*
* Common bits between 4K and 64K pages in a linux-style PTE. * Common bits between 4K and 64K pages in a linux-style PTE.
* These match the bits in the (hardware-defined) PowerPC PTE as closely * Additional bits may be defined in pgtable-hash64-*.h
* as possible. Additional bits may be defined in pgtable-hash64-*.h
* *
* Note: We only support user read/write permissions. Supervisor always * Note: We only support user read/write permissions. Supervisor always
* have full read/write to pages above PAGE_OFFSET (pages below that * have full read/write to pages above PAGE_OFFSET (pages below that
@ -14,13 +13,13 @@
* We could create separate kernel read-only if we used the 3 PP bits * We could create separate kernel read-only if we used the 3 PP bits
* combinations that newer processors provide but we currently don't. * combinations that newer processors provide but we currently don't.
*/ */
#define _PAGE_PTE 0x00001 #define _PAGE_PTE 0x00001 /* distinguishes PTEs from pointers */
#define _PAGE_PRESENT 0x00002 /* software: pte contains a translation */ #define _PAGE_PRESENT 0x00002 /* software: pte contains a translation */
#define _PAGE_BIT_SWAP_TYPE 2 #define _PAGE_BIT_SWAP_TYPE 2
#define _PAGE_USER 0x00004 /* matches one of the PP bits */ #define _PAGE_USER 0x00004 /* page may be accessed by userspace */
#define _PAGE_EXEC 0x00008 /* No execute on POWER4 and newer (we invert) */ #define _PAGE_EXEC 0x00008 /* execute permission */
#define _PAGE_GUARDED 0x00010 #define _PAGE_GUARDED 0x00010 /* G: guarded (side-effect) page */
/* We can derive Memory coherence from _PAGE_NO_CACHE */ /* M (memory coherence) is always set in the HPTE, so we don't need it here */
#define _PAGE_COHERENT 0x0 #define _PAGE_COHERENT 0x0
#define _PAGE_NO_CACHE 0x00020 /* I: cache inhibit */ #define _PAGE_NO_CACHE 0x00020 /* I: cache inhibit */
#define _PAGE_WRITETHRU 0x00040 /* W: cache write-through */ #define _PAGE_WRITETHRU 0x00040 /* W: cache write-through */

3
arch/powerpc/mm/hash64_64k.c
View file

@ -249,8 +249,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access,
return 0; return 0;
/* /*
* Try to lock the PTE, add ACCESSED and DIRTY if it was * Try to lock the PTE, add ACCESSED and DIRTY if it was
* a write access. Since this is 4K insert of 64K page size * a write access.
* also add _PAGE_COMBO
*/ */
new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED; new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED;
if (access & _PAGE_RW) if (access & _PAGE_RW)

10
arch/powerpc/mm/hash_utils_64.c
View file

@ -168,11 +168,11 @@ unsigned long htab_convert_pte_flags(unsigned long pteflags)
rflags |= HPTE_R_N; rflags |= HPTE_R_N;
/* /*
* PP bits: * PP bits:
* Linux use slb key 0 for kernel and 1 for user. * Linux uses slb key 0 for kernel and 1 for user.
* kernel areas are mapped by PP bits 00 * kernel areas are mapped with PP=00
* and and there is no kernel RO (_PAGE_KERNEL_RO). * and there is no kernel RO (_PAGE_KERNEL_RO).
* User area mapped by 0x2 and read only use by * User area is mapped with PP=0x2 for read/write
* 0x3. * or PP=0x3 for read-only (including writeable but clean pages).
*/ */
if (pteflags & _PAGE_USER) { if (pteflags & _PAGE_USER) {
rflags |= 0x2; rflags |= 0x2;