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ASoC: fsl_xcvr: reset RX dpath after wrong preamble
Below preamble error means wrong preamble of IEC958 received, the channel order may be wrong at the moment. FSL_XCVR_IRQ_PREAMBLE_MISMATCH FSL_XCVR_IRQ_UNEXP_PRE_REC FSL_XCVR_IRQ_M_W_PRE_MISMATCH FSL_XCVR_IRQ_B_PRE_MISMATCH All above errors may cause channel swap, to avoid such issues, need to reset the DMAC path. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://patch.msgid.link/1728368873-31379-3-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Shengjiu Wang
Mark Brown
parent
06461e288a
commit
1e5d0f1061
2 changed files with 81 additions and 13 deletions
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@ -53,6 +53,8 @@ struct fsl_xcvr {
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struct snd_aes_iec958 rx_iec958;
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struct snd_aes_iec958 tx_iec958;
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u8 cap_ds[FSL_XCVR_CAPDS_SIZE];
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struct work_struct work_rst;
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spinlock_t lock; /* Protect hw_reset and trigger */
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};
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static const struct fsl_xcvr_pll_conf {
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@ -663,7 +665,10 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
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{
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struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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int ret;
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unsigned long lock_flags;
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int ret = 0;
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spin_lock_irqsave(&xcvr->lock, lock_flags);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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@ -675,7 +680,7 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
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FSL_XCVR_EXT_CTRL_DPTH_RESET(tx));
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if (ret < 0) {
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dev_err(dai->dev, "Failed to set DPATH RESET: %d\n", ret);
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return ret;
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goto release_lock;
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}
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if (tx) {
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@ -687,7 +692,7 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
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FSL_XCVR_ISR_CMDC_TX_EN);
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if (ret < 0) {
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dev_err(dai->dev, "err updating isr %d\n", ret);
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return ret;
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goto release_lock;
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}
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fallthrough;
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case FSL_XCVR_MODE_SPDIF:
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@ -696,7 +701,7 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
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FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
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if (ret < 0) {
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dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret);
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return ret;
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goto release_lock;
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}
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break;
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}
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@ -707,14 +712,14 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
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FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0);
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if (ret < 0) {
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dev_err(dai->dev, "Failed to enable DMA: %d\n", ret);
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return ret;
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goto release_lock;
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}
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ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
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FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL);
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if (ret < 0) {
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dev_err(dai->dev, "Error while setting IER0: %d\n", ret);
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return ret;
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goto release_lock;
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}
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/* clear DPATH RESET */
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@ -723,7 +728,7 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
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0);
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if (ret < 0) {
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dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret);
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return ret;
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goto release_lock;
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}
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break;
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@ -736,14 +741,14 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
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FSL_XCVR_EXT_CTRL_DMA_DIS(tx));
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if (ret < 0) {
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dev_err(dai->dev, "Failed to disable DMA: %d\n", ret);
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return ret;
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goto release_lock;
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}
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ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
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FSL_XCVR_IRQ_EARC_ALL, 0);
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if (ret < 0) {
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dev_err(dai->dev, "Failed to clear IER0: %d\n", ret);
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return ret;
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goto release_lock;
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}
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if (tx) {
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@ -754,7 +759,7 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
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FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
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if (ret < 0) {
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dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret);
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return ret;
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goto release_lock;
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}
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if (xcvr->soc_data->spdif_only)
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break;
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@ -768,17 +773,20 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
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if (ret < 0) {
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dev_err(dai->dev,
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"Err updating ISR %d\n", ret);
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return ret;
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goto release_lock;
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}
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break;
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}
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}
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break;
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default:
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return -EINVAL;
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ret = -EINVAL;
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break;
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}
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return 0;
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release_lock:
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spin_unlock_irqrestore(&xcvr->lock, lock_flags);
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return ret;
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}
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static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
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@ -1198,6 +1206,34 @@ static const struct regmap_config fsl_xcvr_regmap_cfg = {
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.cache_type = REGCACHE_FLAT,
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};
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static void reset_rx_work(struct work_struct *work)
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{
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struct fsl_xcvr *xcvr = container_of(work, struct fsl_xcvr, work_rst);
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struct device *dev = &xcvr->pdev->dev;
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unsigned long lock_flags;
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u32 ext_ctrl;
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dev_dbg(dev, "reset rx path\n");
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spin_lock_irqsave(&xcvr->lock, lock_flags);
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regmap_read(xcvr->regmap, FSL_XCVR_EXT_CTRL, &ext_ctrl);
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if (!(ext_ctrl & FSL_XCVR_EXT_CTRL_DMA_RD_DIS)) {
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regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
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FSL_XCVR_EXT_CTRL_DMA_RD_DIS,
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FSL_XCVR_EXT_CTRL_DMA_RD_DIS);
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regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
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FSL_XCVR_EXT_CTRL_RX_DPTH_RESET,
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FSL_XCVR_EXT_CTRL_RX_DPTH_RESET);
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regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
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FSL_XCVR_EXT_CTRL_DMA_RD_DIS,
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0);
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regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
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FSL_XCVR_EXT_CTRL_RX_DPTH_RESET,
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0);
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}
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spin_unlock_irqrestore(&xcvr->lock, lock_flags);
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}
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static irqreturn_t irq0_isr(int irq, void *devid)
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{
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struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid;
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@ -1269,6 +1305,29 @@ static irqreturn_t irq0_isr(int irq, void *devid)
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dev_dbg(dev, "CMDC status update\n");
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isr_clr |= FSL_XCVR_IRQ_CMDC_STATUS_UPD;
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}
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if (isr & FSL_XCVR_IRQ_PREAMBLE_MISMATCH) {
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dev_dbg(dev, "Preamble mismatch\n");
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isr_clr |= FSL_XCVR_IRQ_PREAMBLE_MISMATCH;
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}
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if (isr & FSL_XCVR_IRQ_UNEXP_PRE_REC) {
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dev_dbg(dev, "Unexpected preamble received\n");
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isr_clr |= FSL_XCVR_IRQ_UNEXP_PRE_REC;
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}
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if (isr & FSL_XCVR_IRQ_M_W_PRE_MISMATCH) {
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dev_dbg(dev, "M/W preamble mismatch\n");
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isr_clr |= FSL_XCVR_IRQ_M_W_PRE_MISMATCH;
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}
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if (isr & FSL_XCVR_IRQ_B_PRE_MISMATCH) {
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dev_dbg(dev, "B preamble mismatch\n");
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isr_clr |= FSL_XCVR_IRQ_B_PRE_MISMATCH;
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}
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if (isr & (FSL_XCVR_IRQ_PREAMBLE_MISMATCH |
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FSL_XCVR_IRQ_UNEXP_PRE_REC |
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FSL_XCVR_IRQ_M_W_PRE_MISMATCH |
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FSL_XCVR_IRQ_B_PRE_MISMATCH)) {
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schedule_work(&xcvr->work_rst);
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}
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if (isr_clr) {
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regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr);
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@ -1415,11 +1474,16 @@ static int fsl_xcvr_probe(struct platform_device *pdev)
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fsl_xcvr_comp.name);
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}
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INIT_WORK(&xcvr->work_rst, reset_rx_work);
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spin_lock_init(&xcvr->lock);
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return ret;
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}
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static void fsl_xcvr_remove(struct platform_device *pdev)
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{
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struct fsl_xcvr *xcvr = dev_get_drvdata(&pdev->dev);
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cancel_work_sync(&xcvr->work_rst);
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pm_runtime_disable(&pdev->dev);
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}
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@ -166,6 +166,10 @@
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FSL_XCVR_IRQ_FIFO_UOFL_ERR | \
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FSL_XCVR_IRQ_HOST_WAKEUP | \
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FSL_XCVR_IRQ_CMDC_STATUS_UPD |\
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FSL_XCVR_IRQ_B_PRE_MISMATCH |\
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FSL_XCVR_IRQ_M_W_PRE_MISMATCH |\
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FSL_XCVR_IRQ_PREAMBLE_MISMATCH |\
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FSL_XCVR_IRQ_UNEXP_PRE_REC |\
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FSL_XCVR_IRQ_ARC_MODE)
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#define FSL_XCVR_ISR_CMDC_TX_EN BIT(3)
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