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drm/radeon/dce3: switch back to old pll allocation order for discrete

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The order shouldn't matter, but this seems to cause regressions for
certain specific cases.  This should fix it for now.  We probably
need to investigate a proper fix in the next development cycle.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Andy Furniss <andyqos@ukfsn.org>
This commit is contained in:
Alex Deucher 2012-11-05 10:16:12 -05:00
parent 695ddeb457
commit 1e4db5f2b4
1 changed files with 31 additions and 23 deletions
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54
drivers/gpu/drm/radeon/atombios_crtc.c
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@ -1696,35 +1696,43 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
return ATOM_PPLL2; return ATOM_PPLL2;
DRM_ERROR("unable to allocate a PPLL\n"); DRM_ERROR("unable to allocate a PPLL\n");
return ATOM_PPLL_INVALID; return ATOM_PPLL_INVALID;
} else { } else if (ASIC_IS_AVIVO(rdev)) {
if (ASIC_IS_AVIVO(rdev)) { /* in DP mode, the DP ref clock can come from either PPLL
/* in DP mode, the DP ref clock can come from either PPLL * depending on the asic:
* depending on the asic: * DCE3: PPLL1 or PPLL2
* DCE3: PPLL1 or PPLL2 */
*/ if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { /* use the same PPLL for all DP monitors */
/* use the same PPLL for all DP monitors */ pll = radeon_get_shared_dp_ppll(crtc);
pll = radeon_get_shared_dp_ppll(crtc); if (pll != ATOM_PPLL_INVALID)
if (pll != ATOM_PPLL_INVALID) return pll;
return pll; } else {
} else { /* use the same PPLL for all monitors with the same clock */
/* use the same PPLL for all monitors with the same clock */ pll = radeon_get_shared_nondp_ppll(crtc);
pll = radeon_get_shared_nondp_ppll(crtc); if (pll != ATOM_PPLL_INVALID)
if (pll != ATOM_PPLL_INVALID) return pll;
return pll; }
} /* all other cases */
/* all other cases */ pll_in_use = radeon_get_pll_use_mask(crtc);
pll_in_use = radeon_get_pll_use_mask(crtc); /* the order shouldn't matter here, but we probably
* need this until we have atomic modeset
*/
if (rdev->flags & RADEON_IS_IGP) {
if (!(pll_in_use & (1 << ATOM_PPLL1))) if (!(pll_in_use & (1 << ATOM_PPLL1)))
return ATOM_PPLL1; return ATOM_PPLL1;
if (!(pll_in_use & (1 << ATOM_PPLL2))) if (!(pll_in_use & (1 << ATOM_PPLL2)))
return ATOM_PPLL2; return ATOM_PPLL2;
DRM_ERROR("unable to allocate a PPLL\n");
return ATOM_PPLL_INVALID;
} else { } else {
/* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ if (!(pll_in_use & (1 << ATOM_PPLL2)))
return radeon_crtc->crtc_id; return ATOM_PPLL2;
if (!(pll_in_use & (1 << ATOM_PPLL1)))
return ATOM_PPLL1;
} }
DRM_ERROR("unable to allocate a PPLL\n");
return ATOM_PPLL_INVALID;
} else {
/* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
return radeon_crtc->crtc_id;
} }
} }