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SPI: add CSR SiRFprimaII SPI controller driver
CSR SiRFprimaII has two SPIs (SPI0 and SPI1). Features: * Master and slave modes * 8-/12-/16-/32-bit data unit * 256 bytes receive data FIFO and 256 bytes transmit data FIFO * Multi-unit frame * Configurable SPI_EN (chip select pin) active state * Configurable SPI_CLK polarity * Configurable SPI_CLK phase * Configurable MSB/LSB first Signed-off-by: Zhiwu Song <zhiwu.song@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Zhiwu Song
Grant Likely
parent
de3bd7e6de
commit
1cc2df9d6f
3 changed files with 695 additions and 0 deletions
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@ -336,6 +336,13 @@ config SPI_SH_HSPI
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help
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SPI driver for SuperH HSPI blocks.
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config SPI_SIRF
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tristate "CSR SiRFprimaII SPI controller"
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depends on ARCH_PRIMA2
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select SPI_BITBANG
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help
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SPI driver for CSR SiRFprimaII SoCs
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config SPI_STMP3XXX
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tristate "Freescale STMP37xx/378x SPI/SSP controller"
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depends on ARCH_STMP3XXX
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@ -53,6 +53,7 @@ obj-$(CONFIG_SPI_SH) += spi-sh.o
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obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
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obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
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obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
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obj-$(CONFIG_SPI_STMP3XXX) += spi-stmp.o
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obj-$(CONFIG_SPI_TEGRA) += spi-tegra.o
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obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.o
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687
drivers/spi/spi-sirf.c
Normal file
687
drivers/spi/spi-sirf.c
Normal file
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@ -0,0 +1,687 @@
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/*
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* SPI bus driver for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/of_gpio.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/pinctrl/pinmux.h>
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#define DRIVER_NAME "sirfsoc_spi"
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#define SIRFSOC_SPI_CTRL 0x0000
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#define SIRFSOC_SPI_CMD 0x0004
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#define SIRFSOC_SPI_TX_RX_EN 0x0008
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#define SIRFSOC_SPI_INT_EN 0x000C
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#define SIRFSOC_SPI_INT_STATUS 0x0010
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#define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100
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#define SIRFSOC_SPI_TX_DMA_IO_LEN 0x0104
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#define SIRFSOC_SPI_TXFIFO_CTRL 0x0108
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#define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C
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#define SIRFSOC_SPI_TXFIFO_OP 0x0110
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#define SIRFSOC_SPI_TXFIFO_STATUS 0x0114
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#define SIRFSOC_SPI_TXFIFO_DATA 0x0118
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#define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120
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#define SIRFSOC_SPI_RX_DMA_IO_LEN 0x0124
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#define SIRFSOC_SPI_RXFIFO_CTRL 0x0128
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#define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C
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#define SIRFSOC_SPI_RXFIFO_OP 0x0130
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#define SIRFSOC_SPI_RXFIFO_STATUS 0x0134
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#define SIRFSOC_SPI_RXFIFO_DATA 0x0138
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#define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144
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/* SPI CTRL register defines */
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#define SIRFSOC_SPI_SLV_MODE BIT(16)
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#define SIRFSOC_SPI_CMD_MODE BIT(17)
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#define SIRFSOC_SPI_CS_IO_OUT BIT(18)
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#define SIRFSOC_SPI_CS_IO_MODE BIT(19)
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#define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20)
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#define SIRFSOC_SPI_CS_IDLE_STAT BIT(21)
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#define SIRFSOC_SPI_TRAN_MSB BIT(22)
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#define SIRFSOC_SPI_DRV_POS_EDGE BIT(23)
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#define SIRFSOC_SPI_CS_HOLD_TIME BIT(24)
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#define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25)
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#define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26)
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#define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26)
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#define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26)
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#define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26)
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#define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
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#define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
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#define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
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/* Interrupt Enable */
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#define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
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#define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
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#define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
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#define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
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#define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4)
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#define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5)
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#define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6)
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#define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
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#define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8)
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#define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9)
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#define SIRFSOC_SPI_FRM_END_INT_EN BIT(10)
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#define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF
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/* Interrupt status */
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#define SIRFSOC_SPI_RX_DONE BIT(0)
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#define SIRFSOC_SPI_TX_DONE BIT(1)
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#define SIRFSOC_SPI_RX_OFLOW BIT(2)
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#define SIRFSOC_SPI_TX_UFLOW BIT(3)
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#define SIRFSOC_SPI_RX_FIFO_FULL BIT(6)
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#define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7)
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#define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8)
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#define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9)
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#define SIRFSOC_SPI_FRM_END BIT(10)
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/* TX RX enable */
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#define SIRFSOC_SPI_RX_EN BIT(0)
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#define SIRFSOC_SPI_TX_EN BIT(1)
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#define SIRFSOC_SPI_CMD_TX_EN BIT(2)
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#define SIRFSOC_SPI_IO_MODE_SEL BIT(0)
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#define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2)
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/* FIFO OPs */
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#define SIRFSOC_SPI_FIFO_RESET BIT(0)
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#define SIRFSOC_SPI_FIFO_START BIT(1)
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/* FIFO CTRL */
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#define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0)
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#define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0)
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#define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0)
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/* FIFO Status */
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#define SIRFSOC_SPI_FIFO_LEVEL_MASK 0xFF
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#define SIRFSOC_SPI_FIFO_FULL BIT(8)
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#define SIRFSOC_SPI_FIFO_EMPTY BIT(9)
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/* 256 bytes rx/tx FIFO */
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#define SIRFSOC_SPI_FIFO_SIZE 256
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#define SIRFSOC_SPI_DAT_FRM_LEN_MAX (64 * 1024)
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#define SIRFSOC_SPI_FIFO_SC(x) ((x) & 0x3F)
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#define SIRFSOC_SPI_FIFO_LC(x) (((x) & 0x3F) << 10)
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#define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20)
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#define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2)
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struct sirfsoc_spi {
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struct spi_bitbang bitbang;
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struct completion done;
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void __iomem *base;
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u32 ctrl_freq; /* SPI controller clock speed */
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struct clk *clk;
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struct pinmux *pmx;
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/* rx & tx bufs from the spi_transfer */
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const void *tx;
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void *rx;
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/* place received word into rx buffer */
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void (*rx_word) (struct sirfsoc_spi *);
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/* get word from tx buffer for sending */
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void (*tx_word) (struct sirfsoc_spi *);
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/* number of words left to be tranmitted/received */
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unsigned int left_tx_cnt;
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unsigned int left_rx_cnt;
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/* tasklet to push tx msg into FIFO */
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struct tasklet_struct tasklet_tx;
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int chipselect[0];
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};
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static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
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{
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u32 data;
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u8 *rx = sspi->rx;
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data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
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if (rx) {
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*rx++ = (u8) data;
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sspi->rx = rx;
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}
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sspi->left_rx_cnt--;
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}
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static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
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{
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u32 data = 0;
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const u8 *tx = sspi->tx;
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if (tx) {
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data = *tx++;
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sspi->tx = tx;
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}
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writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
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sspi->left_tx_cnt--;
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}
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static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
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{
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u32 data;
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u16 *rx = sspi->rx;
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data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
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if (rx) {
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*rx++ = (u16) data;
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sspi->rx = rx;
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}
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sspi->left_rx_cnt--;
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}
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static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
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{
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u32 data = 0;
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const u16 *tx = sspi->tx;
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if (tx) {
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data = *tx++;
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sspi->tx = tx;
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}
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writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
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sspi->left_tx_cnt--;
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}
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static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
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{
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u32 data;
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u32 *rx = sspi->rx;
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data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
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if (rx) {
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*rx++ = (u32) data;
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sspi->rx = rx;
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}
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sspi->left_rx_cnt--;
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}
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static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
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{
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u32 data = 0;
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const u32 *tx = sspi->tx;
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if (tx) {
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data = *tx++;
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sspi->tx = tx;
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}
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writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
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sspi->left_tx_cnt--;
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}
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static void spi_sirfsoc_tasklet_tx(unsigned long arg)
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{
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struct sirfsoc_spi *sspi = (struct sirfsoc_spi *)arg;
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/* Fill Tx FIFO while there are left words to be transmitted */
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while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS) &
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SIRFSOC_SPI_FIFO_FULL)) &&
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sspi->left_tx_cnt)
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sspi->tx_word(sspi);
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}
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static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
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{
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struct sirfsoc_spi *sspi = dev_id;
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u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
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writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
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/* Error Conditions */
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if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
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spi_stat & SIRFSOC_SPI_TX_UFLOW) {
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complete(&sspi->done);
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writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
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}
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if (spi_stat & SIRFSOC_SPI_FRM_END) {
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while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
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& SIRFSOC_SPI_FIFO_EMPTY)) &&
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sspi->left_rx_cnt)
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sspi->rx_word(sspi);
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/* Received all words */
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if ((sspi->left_rx_cnt == 0) && (sspi->left_tx_cnt == 0)) {
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complete(&sspi->done);
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writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
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}
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}
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if (spi_stat & SIRFSOC_SPI_RXFIFO_THD_REACH ||
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spi_stat & SIRFSOC_SPI_TXFIFO_THD_REACH ||
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spi_stat & SIRFSOC_SPI_RX_FIFO_FULL ||
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spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
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tasklet_schedule(&sspi->tasklet_tx);
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return IRQ_HANDLED;
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}
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static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
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{
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struct sirfsoc_spi *sspi;
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int timeout = t->len * 10;
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sspi = spi_master_get_devdata(spi->master);
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sspi->tx = t->tx_buf;
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sspi->rx = t->rx_buf;
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sspi->left_tx_cnt = sspi->left_rx_cnt = t->len;
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INIT_COMPLETION(sspi->done);
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writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
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if (t->len == 1) {
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writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
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SIRFSOC_SPI_ENA_AUTO_CLR,
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sspi->base + SIRFSOC_SPI_CTRL);
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writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
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writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
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} else if ((t->len > 1) && (t->len < SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
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writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
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SIRFSOC_SPI_MUL_DAT_MODE |
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SIRFSOC_SPI_ENA_AUTO_CLR,
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sspi->base + SIRFSOC_SPI_CTRL);
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writel(t->len - 1, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
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writel(t->len - 1, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
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} else {
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writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
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sspi->base + SIRFSOC_SPI_CTRL);
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writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
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writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
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}
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writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
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/* Send the first word to trigger the whole tx/rx process */
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sspi->tx_word(sspi);
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writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
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SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN |
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SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
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SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN);
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writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, sspi->base + SIRFSOC_SPI_TX_RX_EN);
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if (wait_for_completion_timeout(&sspi->done, timeout) == 0)
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dev_err(&spi->dev, "transfer timeout\n");
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/* TX, RX FIFO stop */
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writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
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writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
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writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
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return t->len - sspi->left_rx_cnt;
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}
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static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
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{
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struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
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if (sspi->chipselect[spi->chip_select] == 0) {
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u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
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regval |= SIRFSOC_SPI_CS_IO_OUT;
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switch (value) {
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case BITBANG_CS_ACTIVE:
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if (spi->mode & SPI_CS_HIGH)
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regval |= SIRFSOC_SPI_CS_IO_OUT;
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else
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regval &= ~SIRFSOC_SPI_CS_IO_OUT;
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break;
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case BITBANG_CS_INACTIVE:
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if (spi->mode & SPI_CS_HIGH)
|
||||
regval &= ~SIRFSOC_SPI_CS_IO_OUT;
|
||||
else
|
||||
regval |= SIRFSOC_SPI_CS_IO_OUT;
|
||||
break;
|
||||
}
|
||||
writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
|
||||
} else {
|
||||
int gpio = sspi->chipselect[spi->chip_select];
|
||||
gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
|
||||
{
|
||||
struct sirfsoc_spi *sspi;
|
||||
u8 bits_per_word = 0;
|
||||
int hz = 0;
|
||||
u32 regval;
|
||||
u32 txfifo_ctrl, rxfifo_ctrl;
|
||||
u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4;
|
||||
|
||||
sspi = spi_master_get_devdata(spi->master);
|
||||
|
||||
bits_per_word = t && t->bits_per_word ? t->bits_per_word :
|
||||
spi->bits_per_word;
|
||||
hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
|
||||
|
||||
/* Enable IO mode for RX, TX */
|
||||
writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
|
||||
writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
|
||||
regval = (sspi->ctrl_freq / (2 * hz)) - 1;
|
||||
|
||||
if (regval > 0xFFFF || regval < 0) {
|
||||
dev_err(&spi->dev, "Speed %d not supported\n", hz);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (bits_per_word) {
|
||||
case 8:
|
||||
regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
|
||||
sspi->rx_word = spi_sirfsoc_rx_word_u8;
|
||||
sspi->tx_word = spi_sirfsoc_tx_word_u8;
|
||||
txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
|
||||
SIRFSOC_SPI_FIFO_WIDTH_BYTE;
|
||||
rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
|
||||
SIRFSOC_SPI_FIFO_WIDTH_BYTE;
|
||||
break;
|
||||
case 12:
|
||||
case 16:
|
||||
regval |= (bits_per_word == 12) ? SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
|
||||
SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
|
||||
sspi->rx_word = spi_sirfsoc_rx_word_u16;
|
||||
sspi->tx_word = spi_sirfsoc_tx_word_u16;
|
||||
txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
|
||||
SIRFSOC_SPI_FIFO_WIDTH_WORD;
|
||||
rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
|
||||
SIRFSOC_SPI_FIFO_WIDTH_WORD;
|
||||
break;
|
||||
case 32:
|
||||
regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
|
||||
sspi->rx_word = spi_sirfsoc_rx_word_u32;
|
||||
sspi->tx_word = spi_sirfsoc_tx_word_u32;
|
||||
txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
|
||||
SIRFSOC_SPI_FIFO_WIDTH_DWORD;
|
||||
rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
|
||||
SIRFSOC_SPI_FIFO_WIDTH_DWORD;
|
||||
break;
|
||||
default:
|
||||
dev_err(&spi->dev, "Bits per word %d not supported\n",
|
||||
bits_per_word);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!(spi->mode & SPI_CS_HIGH))
|
||||
regval |= SIRFSOC_SPI_CS_IDLE_STAT;
|
||||
if (!(spi->mode & SPI_LSB_FIRST))
|
||||
regval |= SIRFSOC_SPI_TRAN_MSB;
|
||||
if (spi->mode & SPI_CPOL)
|
||||
regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
|
||||
|
||||
/*
|
||||
* Data should be driven at least 1/2 cycle before the fetch edge to make
|
||||
* sure that data gets stable at the fetch edge.
|
||||
*/
|
||||
if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
|
||||
(!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
|
||||
regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
|
||||
else
|
||||
regval |= SIRFSOC_SPI_DRV_POS_EDGE;
|
||||
|
||||
writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |
|
||||
SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
|
||||
SIRFSOC_SPI_FIFO_HC(2),
|
||||
sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK);
|
||||
writel(SIRFSOC_SPI_FIFO_SC(2) |
|
||||
SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
|
||||
SIRFSOC_SPI_FIFO_HC(fifo_size - 2),
|
||||
sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK);
|
||||
writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
|
||||
writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
|
||||
|
||||
writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_sirfsoc_setup(struct spi_device *spi)
|
||||
{
|
||||
struct sirfsoc_spi *sspi;
|
||||
|
||||
if (!spi->max_speed_hz)
|
||||
return -EINVAL;
|
||||
|
||||
sspi = spi_master_get_devdata(spi->master);
|
||||
|
||||
if (!spi->bits_per_word)
|
||||
spi->bits_per_word = 8;
|
||||
|
||||
return spi_sirfsoc_setup_transfer(spi, NULL);
|
||||
}
|
||||
|
||||
static int __devinit spi_sirfsoc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sirfsoc_spi *sspi;
|
||||
struct spi_master *master;
|
||||
struct resource *mem_res;
|
||||
int num_cs, cs_gpio, irq;
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
ret = of_property_read_u32(pdev->dev.of_node,
|
||||
"sirf,spi-num-chipselects", &num_cs);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Unable to get chip select number\n");
|
||||
goto err_cs;
|
||||
}
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs);
|
||||
if (!master) {
|
||||
dev_err(&pdev->dev, "Unable to allocate SPI master\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
platform_set_drvdata(pdev, master);
|
||||
sspi = spi_master_get_devdata(master);
|
||||
|
||||
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem_res) {
|
||||
dev_err(&pdev->dev, "Unable to get IO resource\n");
|
||||
ret = -ENODEV;
|
||||
goto free_master;
|
||||
}
|
||||
master->num_chipselect = num_cs;
|
||||
|
||||
for (i = 0; i < master->num_chipselect; i++) {
|
||||
cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i);
|
||||
if (cs_gpio < 0) {
|
||||
dev_err(&pdev->dev, "can't get cs gpio from DT\n");
|
||||
ret = -ENODEV;
|
||||
goto free_master;
|
||||
}
|
||||
|
||||
sspi->chipselect[i] = cs_gpio;
|
||||
if (cs_gpio == 0)
|
||||
continue; /* use cs from spi controller */
|
||||
|
||||
ret = gpio_request(cs_gpio, DRIVER_NAME);
|
||||
if (ret) {
|
||||
while (i > 0) {
|
||||
i--;
|
||||
if (sspi->chipselect[i] > 0)
|
||||
gpio_free(sspi->chipselect[i]);
|
||||
}
|
||||
dev_err(&pdev->dev, "fail to request cs gpios\n");
|
||||
goto free_master;
|
||||
}
|
||||
}
|
||||
|
||||
sspi->base = devm_request_and_ioremap(&pdev->dev, mem_res);
|
||||
if (!sspi->base) {
|
||||
dev_err(&pdev->dev, "IO remap failed!\n");
|
||||
ret = -ENOMEM;
|
||||
goto free_master;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
ret = -ENXIO;
|
||||
goto free_master;
|
||||
}
|
||||
ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
|
||||
DRIVER_NAME, sspi);
|
||||
if (ret)
|
||||
goto free_master;
|
||||
|
||||
sspi->bitbang.master = spi_master_get(master);
|
||||
sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
|
||||
sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
|
||||
sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
|
||||
sspi->bitbang.master->setup = spi_sirfsoc_setup;
|
||||
master->bus_num = pdev->id;
|
||||
sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
|
||||
|
||||
sspi->pmx = pinmux_get(&pdev->dev, NULL);
|
||||
ret = IS_ERR(sspi->pmx);
|
||||
if (ret)
|
||||
goto free_master;
|
||||
|
||||
pinmux_enable(sspi->pmx);
|
||||
|
||||
sspi->clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(sspi->clk)) {
|
||||
ret = -EINVAL;
|
||||
goto free_pmx;
|
||||
}
|
||||
clk_enable(sspi->clk);
|
||||
sspi->ctrl_freq = clk_get_rate(sspi->clk);
|
||||
|
||||
init_completion(&sspi->done);
|
||||
|
||||
tasklet_init(&sspi->tasklet_tx, spi_sirfsoc_tasklet_tx,
|
||||
(unsigned long)sspi);
|
||||
|
||||
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
|
||||
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
|
||||
writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
|
||||
writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
|
||||
/* We are not using dummy delay between command and data */
|
||||
writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
|
||||
|
||||
ret = spi_bitbang_start(&sspi->bitbang);
|
||||
if (ret)
|
||||
goto free_clk;
|
||||
|
||||
dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
|
||||
|
||||
return 0;
|
||||
|
||||
free_clk:
|
||||
clk_disable(sspi->clk);
|
||||
clk_put(sspi->clk);
|
||||
free_pmx:
|
||||
pinmux_disable(sspi->pmx);
|
||||
pinmux_put(sspi->pmx);
|
||||
free_master:
|
||||
spi_master_put(master);
|
||||
err_cs:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit spi_sirfsoc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct sirfsoc_spi *sspi;
|
||||
int i;
|
||||
|
||||
master = platform_get_drvdata(pdev);
|
||||
sspi = spi_master_get_devdata(master);
|
||||
|
||||
spi_bitbang_stop(&sspi->bitbang);
|
||||
for (i = 0; i < master->num_chipselect; i++) {
|
||||
if (sspi->chipselect[i] > 0)
|
||||
gpio_free(sspi->chipselect[i]);
|
||||
}
|
||||
clk_disable(sspi->clk);
|
||||
clk_put(sspi->clk);
|
||||
pinmux_disable(sspi->pmx);
|
||||
pinmux_put(sspi->pmx);
|
||||
spi_master_put(master);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int spi_sirfsoc_suspend(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
|
||||
|
||||
clk_disable(sspi->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_sirfsoc_resume(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
|
||||
|
||||
clk_enable(sspi->clk);
|
||||
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
|
||||
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
|
||||
writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
|
||||
writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops spi_sirfsoc_pm_ops = {
|
||||
.suspend = spi_sirfsoc_suspend,
|
||||
.resume = spi_sirfsoc_resume,
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct of_device_id spi_sirfsoc_of_match[] = {
|
||||
{ .compatible = "sirf,prima2-spi", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sirfsoc_spi_of_match);
|
||||
|
||||
static struct platform_driver spi_sirfsoc_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
#ifdef CONFIG_PM
|
||||
.pm = &spi_sirfsoc_pm_ops,
|
||||
#endif
|
||||
.of_match_table = spi_sirfsoc_of_match,
|
||||
},
|
||||
.probe = spi_sirfsoc_probe,
|
||||
.remove = __devexit_p(spi_sirfsoc_remove),
|
||||
};
|
||||
module_platform_driver(spi_sirfsoc_driver);
|
||||
|
||||
MODULE_DESCRIPTION("SiRF SoC SPI master driver");
|
||||
MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
|
||||
"Barry Song <Baohua.Song@csr.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Add table
Reference in a new issue