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arm64: dts: qcom: sc7280: fix codec reset line polarity for CRD 3.0/3.1

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The driver for the codec, when resetting the chip, first drives the line
low, and then high. This means that the line is active low. Change the
annotation in the DTS accordingly.

Fixes: 0a3a56a93f ("arm64: dts: qcom: sc7280: Add wcd9385 codec node for CRD 3.0/3.1")
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221027074652.1044235-4-dmitry.torokhov@gmail.com
This commit is contained in:
Dmitry Torokhov 2022-10-27 00:46:50 -07:00 • committed by Bjorn Andersson
parent 15d9fcbb3e
commit 1caf66104c
1 changed files with 1 additions and 1 deletions
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2
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
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@ -37,7 +37,7 @@
pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>;
reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
qcom,rx-device = <&wcd_rx>;