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nds32: Fix typo in Kconfig.cpu

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This patch fixes some spelling typo in Kconfig.cpu

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by: Greentime Hu <green.hu@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
This commit is contained in:
Masanari Iida 2019-08-14 12:45:21 +09:00 • committed by Greentime Hu
parent 9e5183ee41
commit 1b78375c37
1 changed files with 4 additions and 4 deletions
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8
arch/nds32/Kconfig.cpu
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@ -13,7 +13,7 @@ config FPU
default n default n
help help
If FPU ISA is used in user space, this configuration shall be Y to If FPU ISA is used in user space, this configuration shall be Y to
enable required support in kerenl such as fpu context switch and enable required support in kernel such as fpu context switch and
fpu exception handler. fpu exception handler.
If no FPU ISA is used in user space, say N. If no FPU ISA is used in user space, say N.
@ -27,7 +27,7 @@ config LAZY_FPU
enhance system performance by reducing the context switch enhance system performance by reducing the context switch
frequency of the FPU register. frequency of the FPU register.
For nomal case, say Y. For normal case, say Y.
config SUPPORT_DENORMAL_ARITHMETIC config SUPPORT_DENORMAL_ARITHMETIC
bool "Denormal arithmetic support" bool "Denormal arithmetic support"
@ -36,7 +36,7 @@ config SUPPORT_DENORMAL_ARITHMETIC
help help
Say Y here to enable arithmetic of denormalized number. Enabling Say Y here to enable arithmetic of denormalized number. Enabling
this feature can enhance the precision for tininess number. this feature can enhance the precision for tininess number.
However, performance loss in float pointe calculations is However, performance loss in float point calculations is
possibly significant due to additional FPU exception. possibly significant due to additional FPU exception.
If the calculated tolerance for tininess number is not critical, If the calculated tolerance for tininess number is not critical,
@ -73,7 +73,7 @@ choice
the cache aliasing issue. The rest cpus(N13, N10 and D10) are the cache aliasing issue. The rest cpus(N13, N10 and D10) are
implemented as VIPT data cache. It may cause the cache aliasing issue implemented as VIPT data cache. It may cause the cache aliasing issue
if its cache way size is larger than page size. You can specify the if its cache way size is larger than page size. You can specify the
CPU type direcly or choose CPU_V3 if unsure. CPU type directly or choose CPU_V3 if unsure.
A kernel built for N10 is able to run on N15, D15, N13, N10 or D10. A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
A kernel built for N15 is able to run on N15 or D15. A kernel built for N15 is able to run on N15 or D15.