public-mirrors/linux
1
0
Fork 0
mirror of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2025-08-05 16:54:27 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

drm/amdgpu: replace MCA macro with ACA for XGMI

Browse source 
use new ACA macro to instead of MCA

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yang Wang 2023-11-24 16:46:25 +08:00 • committed by Alex Deucher
parent 46e2231ce0
commit 1714a1ffaf
1 changed files with 12 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

24
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
View file

@ -1047,8 +1047,8 @@ static int xgmi_v6_4_0_aca_bank_generate_report(struct aca_handle *handle, struc
if (ret) if (ret)
return ret; return ret;
status = bank->regs[MCA_REG_IDX_STATUS]; status = bank->regs[ACA_REG_IDX_STATUS];
ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status); ext_error_code = ACA_REG__STATUS__ERRORCODEEXT(status);
error_str = ext_error_code < ARRAY_SIZE(xgmi_v6_4_0_ras_error_code_ext) ? error_str = ext_error_code < ARRAY_SIZE(xgmi_v6_4_0_ras_error_code_ext) ?
xgmi_v6_4_0_ras_error_code_ext[ext_error_code] : NULL; xgmi_v6_4_0_ras_error_code_ext[ext_error_code] : NULL;
@ -1158,7 +1158,7 @@ static void amdgpu_xgmi_legacy_reset_ras_error_count(struct amdgpu_device *adev)
static void __xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst, u64 mca_base) static void __xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst, u64 mca_base)
{ {
WREG64_MCA(xgmi_inst, mca_base, MCA_REG_IDX_STATUS, 0ULL); WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL);
} }
static void xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst) static void xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst)
@ -1336,12 +1336,12 @@ static void amdgpu_xgmi_legacy_query_ras_error_count(struct amdgpu_device *adev,
err_data->ce_count += ce_cnt; err_data->ce_count += ce_cnt;
} }
static enum amdgpu_mca_error_type xgmi_v6_4_0_pcs_mca_get_error_type(struct amdgpu_device *adev, u64 status) static enum aca_error_type xgmi_v6_4_0_pcs_mca_get_error_type(struct amdgpu_device *adev, u64 status)
{ {
const char *error_str; const char *error_str;
int ext_error_code; int ext_error_code;
ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status); ext_error_code = ACA_REG__STATUS__ERRORCODEEXT(status);
error_str = ext_error_code < ARRAY_SIZE(xgmi_v6_4_0_ras_error_code_ext) ? error_str = ext_error_code < ARRAY_SIZE(xgmi_v6_4_0_ras_error_code_ext) ?
xgmi_v6_4_0_ras_error_code_ext[ext_error_code] : NULL; xgmi_v6_4_0_ras_error_code_ext[ext_error_code] : NULL;
@ -1350,9 +1350,9 @@ static enum amdgpu_mca_error_type xgmi_v6_4_0_pcs_mca_get_error_type(struct amdg
switch (ext_error_code) { switch (ext_error_code) {
case 0: case 0:
return AMDGPU_MCA_ERROR_TYPE_UE; return ACA_ERROR_TYPE_UE;
case 6: case 6:
return AMDGPU_MCA_ERROR_TYPE_CE; return ACA_ERROR_TYPE_CE;
default: default:
return -EINVAL; return -EINVAL;
} }
@ -1366,22 +1366,22 @@ static void __xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, struct a
int xgmi_inst = mcm_info->die_id; int xgmi_inst = mcm_info->die_id;
u64 status = 0; u64 status = 0;
status = RREG64_MCA(xgmi_inst, mca_base, MCA_REG_IDX_STATUS); status = RREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS);
if (!MCA_REG__STATUS__VAL(status)) if (!ACA_REG__STATUS__VAL(status))
return; return;
switch (xgmi_v6_4_0_pcs_mca_get_error_type(adev, status)) { switch (xgmi_v6_4_0_pcs_mca_get_error_type(adev, status)) {
case AMDGPU_MCA_ERROR_TYPE_UE: case ACA_ERROR_TYPE_UE:
amdgpu_ras_error_statistic_ue_count(err_data, mcm_info, NULL, 1ULL); amdgpu_ras_error_statistic_ue_count(err_data, mcm_info, NULL, 1ULL);
break; break;
case AMDGPU_MCA_ERROR_TYPE_CE: case ACA_ERROR_TYPE_CE:
amdgpu_ras_error_statistic_ce_count(err_data, mcm_info, NULL, 1ULL); amdgpu_ras_error_statistic_ce_count(err_data, mcm_info, NULL, 1ULL);
break; break;
default: default:
break; break;
} }
WREG64_MCA(xgmi_inst, mca_base, MCA_REG_IDX_STATUS, 0ULL); WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL);
} }
static void xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, int xgmi_inst, struct ras_err_data *err_data) static void xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, int xgmi_inst, struct ras_err_data *err_data)