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drm/amdgpu/nv: add mode2 reset handling
Vangogh will use mode2 reset, so plumb it through the nv soc driver. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com>
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parent
20e157c725
commit
1608635534
1 changed files with 12 additions and 2 deletions
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@ -351,6 +351,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
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struct smu_context *smu = &adev->smu;
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if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
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amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
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amdgpu_reset_method == AMD_RESET_METHOD_BACO)
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return amdgpu_reset_method;
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@ -359,6 +360,8 @@ nv_asic_reset_method(struct amdgpu_device *adev)
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amdgpu_reset_method);
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switch (adev->asic_type) {
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case CHIP_VANGOGH:
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return AMD_RESET_METHOD_MODE2;
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_DIMGREY_CAVEFISH:
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@ -376,7 +379,8 @@ static int nv_asic_reset(struct amdgpu_device *adev)
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int ret = 0;
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struct smu_context *smu = &adev->smu;
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if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
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switch (nv_asic_reset_method(adev)) {
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case AMD_RESET_METHOD_BACO:
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dev_info(adev->dev, "BACO reset\n");
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ret = smu_baco_enter(smu);
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@ -385,9 +389,15 @@ static int nv_asic_reset(struct amdgpu_device *adev)
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ret = smu_baco_exit(smu);
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if (ret)
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return ret;
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} else {
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break;
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case AMD_RESET_METHOD_MODE2:
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dev_info(adev->dev, "MODE2 reset\n");
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ret = amdgpu_dpm_mode2_reset(adev);
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break;
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default:
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dev_info(adev->dev, "MODE1 reset\n");
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ret = nv_asic_mode1_reset(adev);
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break;
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}
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return ret;
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