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x86/insn: x86/insn: Add support for REX2 prefix to the instruction decoder opcode map

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Support for REX2 has been added to the instruction decoder logic and the
awk script that generates the attribute tables from the opcode map.

Add REX2 prefix byte (0xD5) to the opcode map.

Add annotation (!REX2) for map 0/1 opcodes that are reserved under REX2.

Add JMPABS to the opcode map and add annotation (REX2) to identify that it
has a mandatory REX2 prefix. A separate opcode attribute table is not
needed at this time because JMPABS has the same attribute encoding as the
MOV instruction that it shares an opcode with i.e. INAT_MOFFSET.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20240502105853.5338-7-adrian.hunter@intel.com
This commit is contained in:
Adrian Hunter 2024-05-02 13:58:49 +03:00 • committed by Ingo Molnar
parent eada38d575
commit 159039af8c
2 changed files with 152 additions and 144 deletions
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148
arch/x86/lib/x86-opcode-map.txt
View file

@ -33,6 +33,10 @@
# - (F2): the last prefix is 0xF2 # - (F2): the last prefix is 0xF2
# - (!F3) : the last prefix is not 0xF3 (including non-last prefix case) # - (!F3) : the last prefix is not 0xF3 (including non-last prefix case)
# - (66&F2): Both 0x66 and 0xF2 prefixes are specified. # - (66&F2): Both 0x66 and 0xF2 prefixes are specified.
#
# REX2 Prefix
# - (!REX2): REX2 is not allowed
# - (REX2): REX2 variant e.g. JMPABS
Table: one byte opcode Table: one byte opcode
Referrer: Referrer:
@ -157,22 +161,22 @@ AVXcode:
6e: OUTS/OUTSB DX,Xb 6e: OUTS/OUTSB DX,Xb
6f: OUTS/OUTSW/OUTSD DX,Xz 6f: OUTS/OUTSW/OUTSD DX,Xz
# 0x70 - 0x7f # 0x70 - 0x7f
70: JO Jb 70: JO Jb (!REX2)
71: JNO Jb 71: JNO Jb (!REX2)
72: JB/JNAE/JC Jb 72: JB/JNAE/JC Jb (!REX2)
73: JNB/JAE/JNC Jb 73: JNB/JAE/JNC Jb (!REX2)
74: JZ/JE Jb 74: JZ/JE Jb (!REX2)
75: JNZ/JNE Jb 75: JNZ/JNE Jb (!REX2)
76: JBE/JNA Jb 76: JBE/JNA Jb (!REX2)
77: JNBE/JA Jb 77: JNBE/JA Jb (!REX2)
78: JS Jb 78: JS Jb (!REX2)
79: JNS Jb 79: JNS Jb (!REX2)
7a: JP/JPE Jb 7a: JP/JPE Jb (!REX2)
7b: JNP/JPO Jb 7b: JNP/JPO Jb (!REX2)
7c: JL/JNGE Jb 7c: JL/JNGE Jb (!REX2)
7d: JNL/JGE Jb 7d: JNL/JGE Jb (!REX2)
7e: JLE/JNG Jb 7e: JLE/JNG Jb (!REX2)
7f: JNLE/JG Jb 7f: JNLE/JG Jb (!REX2)
# 0x80 - 0x8f # 0x80 - 0x8f
80: Grp1 Eb,Ib (1A) 80: Grp1 Eb,Ib (1A)
81: Grp1 Ev,Iz (1A) 81: Grp1 Ev,Iz (1A)
@ -208,24 +212,24 @@ AVXcode:
9e: SAHF 9e: SAHF
9f: LAHF 9f: LAHF
# 0xa0 - 0xaf # 0xa0 - 0xaf
a0: MOV AL,Ob a0: MOV AL,Ob (!REX2)
a1: MOV rAX,Ov a1: MOV rAX,Ov (!REX2) | JMPABS O (REX2),(o64)
a2: MOV Ob,AL a2: MOV Ob,AL (!REX2)
a3: MOV Ov,rAX a3: MOV Ov,rAX (!REX2)
a4: MOVS/B Yb,Xb a4: MOVS/B Yb,Xb (!REX2)
a5: MOVS/W/D/Q Yv,Xv a5: MOVS/W/D/Q Yv,Xv (!REX2)
a6: CMPS/B Xb,Yb a6: CMPS/B Xb,Yb (!REX2)
a7: CMPS/W/D Xv,Yv a7: CMPS/W/D Xv,Yv (!REX2)
a8: TEST AL,Ib a8: TEST AL,Ib (!REX2)
a9: TEST rAX,Iz a9: TEST rAX,Iz (!REX2)
aa: STOS/B Yb,AL aa: STOS/B Yb,AL (!REX2)
ab: STOS/W/D/Q Yv,rAX ab: STOS/W/D/Q Yv,rAX (!REX2)
ac: LODS/B AL,Xb ac: LODS/B AL,Xb (!REX2)
ad: LODS/W/D/Q rAX,Xv ad: LODS/W/D/Q rAX,Xv (!REX2)
ae: SCAS/B AL,Yb ae: SCAS/B AL,Yb (!REX2)
# Note: The May 2011 Intel manual shows Xv for the second parameter of the # Note: The May 2011 Intel manual shows Xv for the second parameter of the
# next instruction but Yv is correct # next instruction but Yv is correct
af: SCAS/W/D/Q rAX,Yv af: SCAS/W/D/Q rAX,Yv (!REX2)
# 0xb0 - 0xbf # 0xb0 - 0xbf
b0: MOV AL/R8L,Ib b0: MOV AL/R8L,Ib
b1: MOV CL/R9L,Ib b1: MOV CL/R9L,Ib
@ -266,7 +270,7 @@ d1: Grp2 Ev,1 (1A)
d2: Grp2 Eb,CL (1A) d2: Grp2 Eb,CL (1A)
d3: Grp2 Ev,CL (1A) d3: Grp2 Ev,CL (1A)
d4: AAM Ib (i64) d4: AAM Ib (i64)
d5: AAD Ib (i64) d5: AAD Ib (i64) | REX2 (Prefix),(o64)
d6: d6:
d7: XLAT/XLATB d7: XLAT/XLATB
d8: ESC d8: ESC
@ -281,26 +285,26 @@ df: ESC
# Note: "forced64" is Intel CPU behavior: they ignore 0x66 prefix # Note: "forced64" is Intel CPU behavior: they ignore 0x66 prefix
# in 64-bit mode. AMD CPUs accept 0x66 prefix, it causes RIP truncation # in 64-bit mode. AMD CPUs accept 0x66 prefix, it causes RIP truncation
# to 16 bits. In 32-bit mode, 0x66 is accepted by both Intel and AMD. # to 16 bits. In 32-bit mode, 0x66 is accepted by both Intel and AMD.
e0: LOOPNE/LOOPNZ Jb (f64) e0: LOOPNE/LOOPNZ Jb (f64) (!REX2)
e1: LOOPE/LOOPZ Jb (f64) e1: LOOPE/LOOPZ Jb (f64) (!REX2)
e2: LOOP Jb (f64) e2: LOOP Jb (f64) (!REX2)
e3: JrCXZ Jb (f64) e3: JrCXZ Jb (f64) (!REX2)
e4: IN AL,Ib e4: IN AL,Ib (!REX2)
e5: IN eAX,Ib e5: IN eAX,Ib (!REX2)
e6: OUT Ib,AL e6: OUT Ib,AL (!REX2)
e7: OUT Ib,eAX e7: OUT Ib,eAX (!REX2)
# With 0x66 prefix in 64-bit mode, for AMD CPUs immediate offset # With 0x66 prefix in 64-bit mode, for AMD CPUs immediate offset
# in "near" jumps and calls is 16-bit. For CALL, # in "near" jumps and calls is 16-bit. For CALL,
# push of return address is 16-bit wide, RSP is decremented by 2 # push of return address is 16-bit wide, RSP is decremented by 2
# but is not truncated to 16 bits, unlike RIP. # but is not truncated to 16 bits, unlike RIP.
e8: CALL Jz (f64) e8: CALL Jz (f64) (!REX2)
e9: JMP-near Jz (f64) e9: JMP-near Jz (f64) (!REX2)
ea: JMP-far Ap (i64) ea: JMP-far Ap (i64) (!REX2)
eb: JMP-short Jb (f64) eb: JMP-short Jb (f64) (!REX2)
ec: IN AL,DX ec: IN AL,DX (!REX2)
ed: IN eAX,DX ed: IN eAX,DX (!REX2)
ee: OUT DX,AL ee: OUT DX,AL (!REX2)
ef: OUT DX,eAX ef: OUT DX,eAX (!REX2)
# 0xf0 - 0xff # 0xf0 - 0xff
f0: LOCK (Prefix) f0: LOCK (Prefix)
f1: f1:
@ -386,14 +390,14 @@ AVXcode: 1
2e: vucomiss Vss,Wss (v1) | vucomisd Vsd,Wsd (66),(v1) 2e: vucomiss Vss,Wss (v1) | vucomisd Vsd,Wsd (66),(v1)
2f: vcomiss Vss,Wss (v1) | vcomisd Vsd,Wsd (66),(v1) 2f: vcomiss Vss,Wss (v1) | vcomisd Vsd,Wsd (66),(v1)
# 0x0f 0x30-0x3f # 0x0f 0x30-0x3f
30: WRMSR 30: WRMSR (!REX2)
31: RDTSC 31: RDTSC (!REX2)
32: RDMSR 32: RDMSR (!REX2)
33: RDPMC 33: RDPMC (!REX2)
34: SYSENTER 34: SYSENTER (!REX2)
35: SYSEXIT 35: SYSEXIT (!REX2)
36: 36:
37: GETSEC 37: GETSEC (!REX2)
38: escape # 3-byte escape 1 38: escape # 3-byte escape 1
39: 39:
3a: escape # 3-byte escape 2 3a: escape # 3-byte escape 2
@ -473,22 +477,22 @@ AVXcode: 1
7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqa32/64 Wx,Vx (66),(evo) | vmovdqu Wx,Vx (F3) | vmovdqu32/64 Wx,Vx (F3),(evo) | vmovdqu8/16 Wx,Vx (F2),(ev) 7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqa32/64 Wx,Vx (66),(evo) | vmovdqu Wx,Vx (F3) | vmovdqu32/64 Wx,Vx (F3),(evo) | vmovdqu8/16 Wx,Vx (F2),(ev)
# 0x0f 0x80-0x8f # 0x0f 0x80-0x8f
# Note: "forced64" is Intel CPU behavior (see comment about CALL insn). # Note: "forced64" is Intel CPU behavior (see comment about CALL insn).
80: JO Jz (f64) 80: JO Jz (f64) (!REX2)
81: JNO Jz (f64) 81: JNO Jz (f64) (!REX2)
82: JB/JC/JNAE Jz (f64) 82: JB/JC/JNAE Jz (f64) (!REX2)
83: JAE/JNB/JNC Jz (f64) 83: JAE/JNB/JNC Jz (f64) (!REX2)
84: JE/JZ Jz (f64) 84: JE/JZ Jz (f64) (!REX2)
85: JNE/JNZ Jz (f64) 85: JNE/JNZ Jz (f64) (!REX2)
86: JBE/JNA Jz (f64) 86: JBE/JNA Jz (f64) (!REX2)
87: JA/JNBE Jz (f64) 87: JA/JNBE Jz (f64) (!REX2)
88: JS Jz (f64) 88: JS Jz (f64) (!REX2)
89: JNS Jz (f64) 89: JNS Jz (f64) (!REX2)
8a: JP/JPE Jz (f64) 8a: JP/JPE Jz (f64) (!REX2)
8b: JNP/JPO Jz (f64) 8b: JNP/JPO Jz (f64) (!REX2)
8c: JL/JNGE Jz (f64) 8c: JL/JNGE Jz (f64) (!REX2)
8d: JNL/JGE Jz (f64) 8d: JNL/JGE Jz (f64) (!REX2)
8e: JLE/JNG Jz (f64) 8e: JLE/JNG Jz (f64) (!REX2)
8f: JNLE/JG Jz (f64) 8f: JNLE/JG Jz (f64) (!REX2)
# 0x0f 0x90-0x9f # 0x0f 0x90-0x9f
90: SETO Eb | kmovw/q Vk,Wk | kmovb/d Vk,Wk (66) 90: SETO Eb | kmovw/q Vk,Wk | kmovb/d Vk,Wk (66)
91: SETNO Eb | kmovw/q Mv,Vk | kmovb/d Mv,Vk (66) 91: SETNO Eb | kmovw/q Mv,Vk | kmovb/d Mv,Vk (66)

148
tools/arch/x86/lib/x86-opcode-map.txt
View file

@ -33,6 +33,10 @@
# - (F2): the last prefix is 0xF2 # - (F2): the last prefix is 0xF2
# - (!F3) : the last prefix is not 0xF3 (including non-last prefix case) # - (!F3) : the last prefix is not 0xF3 (including non-last prefix case)
# - (66&F2): Both 0x66 and 0xF2 prefixes are specified. # - (66&F2): Both 0x66 and 0xF2 prefixes are specified.
#
# REX2 Prefix
# - (!REX2): REX2 is not allowed
# - (REX2): REX2 variant e.g. JMPABS
Table: one byte opcode Table: one byte opcode
Referrer: Referrer:
@ -157,22 +161,22 @@ AVXcode:
6e: OUTS/OUTSB DX,Xb 6e: OUTS/OUTSB DX,Xb
6f: OUTS/OUTSW/OUTSD DX,Xz 6f: OUTS/OUTSW/OUTSD DX,Xz
# 0x70 - 0x7f # 0x70 - 0x7f
70: JO Jb 70: JO Jb (!REX2)
71: JNO Jb 71: JNO Jb (!REX2)
72: JB/JNAE/JC Jb 72: JB/JNAE/JC Jb (!REX2)
73: JNB/JAE/JNC Jb 73: JNB/JAE/JNC Jb (!REX2)
74: JZ/JE Jb 74: JZ/JE Jb (!REX2)
75: JNZ/JNE Jb 75: JNZ/JNE Jb (!REX2)
76: JBE/JNA Jb 76: JBE/JNA Jb (!REX2)
77: JNBE/JA Jb 77: JNBE/JA Jb (!REX2)
78: JS Jb 78: JS Jb (!REX2)
79: JNS Jb 79: JNS Jb (!REX2)
7a: JP/JPE Jb 7a: JP/JPE Jb (!REX2)
7b: JNP/JPO Jb 7b: JNP/JPO Jb (!REX2)
7c: JL/JNGE Jb 7c: JL/JNGE Jb (!REX2)
7d: JNL/JGE Jb 7d: JNL/JGE Jb (!REX2)
7e: JLE/JNG Jb 7e: JLE/JNG Jb (!REX2)
7f: JNLE/JG Jb 7f: JNLE/JG Jb (!REX2)
# 0x80 - 0x8f # 0x80 - 0x8f
80: Grp1 Eb,Ib (1A) 80: Grp1 Eb,Ib (1A)
81: Grp1 Ev,Iz (1A) 81: Grp1 Ev,Iz (1A)
@ -208,24 +212,24 @@ AVXcode:
9e: SAHF 9e: SAHF
9f: LAHF 9f: LAHF
# 0xa0 - 0xaf # 0xa0 - 0xaf
a0: MOV AL,Ob a0: MOV AL,Ob (!REX2)
a1: MOV rAX,Ov a1: MOV rAX,Ov (!REX2) | JMPABS O (REX2),(o64)
a2: MOV Ob,AL a2: MOV Ob,AL (!REX2)
a3: MOV Ov,rAX a3: MOV Ov,rAX (!REX2)
a4: MOVS/B Yb,Xb a4: MOVS/B Yb,Xb (!REX2)
a5: MOVS/W/D/Q Yv,Xv a5: MOVS/W/D/Q Yv,Xv (!REX2)
a6: CMPS/B Xb,Yb a6: CMPS/B Xb,Yb (!REX2)
a7: CMPS/W/D Xv,Yv a7: CMPS/W/D Xv,Yv (!REX2)
a8: TEST AL,Ib a8: TEST AL,Ib (!REX2)
a9: TEST rAX,Iz a9: TEST rAX,Iz (!REX2)
aa: STOS/B Yb,AL aa: STOS/B Yb,AL (!REX2)
ab: STOS/W/D/Q Yv,rAX ab: STOS/W/D/Q Yv,rAX (!REX2)
ac: LODS/B AL,Xb ac: LODS/B AL,Xb (!REX2)
ad: LODS/W/D/Q rAX,Xv ad: LODS/W/D/Q rAX,Xv (!REX2)
ae: SCAS/B AL,Yb ae: SCAS/B AL,Yb (!REX2)
# Note: The May 2011 Intel manual shows Xv for the second parameter of the # Note: The May 2011 Intel manual shows Xv for the second parameter of the
# next instruction but Yv is correct # next instruction but Yv is correct
af: SCAS/W/D/Q rAX,Yv af: SCAS/W/D/Q rAX,Yv (!REX2)
# 0xb0 - 0xbf # 0xb0 - 0xbf
b0: MOV AL/R8L,Ib b0: MOV AL/R8L,Ib
b1: MOV CL/R9L,Ib b1: MOV CL/R9L,Ib
@ -266,7 +270,7 @@ d1: Grp2 Ev,1 (1A)
d2: Grp2 Eb,CL (1A) d2: Grp2 Eb,CL (1A)
d3: Grp2 Ev,CL (1A) d3: Grp2 Ev,CL (1A)
d4: AAM Ib (i64) d4: AAM Ib (i64)
d5: AAD Ib (i64) d5: AAD Ib (i64) | REX2 (Prefix),(o64)
d6: d6:
d7: XLAT/XLATB d7: XLAT/XLATB
d8: ESC d8: ESC
@ -281,26 +285,26 @@ df: ESC
# Note: "forced64" is Intel CPU behavior: they ignore 0x66 prefix # Note: "forced64" is Intel CPU behavior: they ignore 0x66 prefix
# in 64-bit mode. AMD CPUs accept 0x66 prefix, it causes RIP truncation # in 64-bit mode. AMD CPUs accept 0x66 prefix, it causes RIP truncation
# to 16 bits. In 32-bit mode, 0x66 is accepted by both Intel and AMD. # to 16 bits. In 32-bit mode, 0x66 is accepted by both Intel and AMD.
e0: LOOPNE/LOOPNZ Jb (f64) e0: LOOPNE/LOOPNZ Jb (f64) (!REX2)
e1: LOOPE/LOOPZ Jb (f64) e1: LOOPE/LOOPZ Jb (f64) (!REX2)
e2: LOOP Jb (f64) e2: LOOP Jb (f64) (!REX2)
e3: JrCXZ Jb (f64) e3: JrCXZ Jb (f64) (!REX2)
e4: IN AL,Ib e4: IN AL,Ib (!REX2)
e5: IN eAX,Ib e5: IN eAX,Ib (!REX2)
e6: OUT Ib,AL e6: OUT Ib,AL (!REX2)
e7: OUT Ib,eAX e7: OUT Ib,eAX (!REX2)
# With 0x66 prefix in 64-bit mode, for AMD CPUs immediate offset # With 0x66 prefix in 64-bit mode, for AMD CPUs immediate offset
# in "near" jumps and calls is 16-bit. For CALL, # in "near" jumps and calls is 16-bit. For CALL,
# push of return address is 16-bit wide, RSP is decremented by 2 # push of return address is 16-bit wide, RSP is decremented by 2
# but is not truncated to 16 bits, unlike RIP. # but is not truncated to 16 bits, unlike RIP.
e8: CALL Jz (f64) e8: CALL Jz (f64) (!REX2)
e9: JMP-near Jz (f64) e9: JMP-near Jz (f64) (!REX2)
ea: JMP-far Ap (i64) ea: JMP-far Ap (i64) (!REX2)
eb: JMP-short Jb (f64) eb: JMP-short Jb (f64) (!REX2)
ec: IN AL,DX ec: IN AL,DX (!REX2)
ed: IN eAX,DX ed: IN eAX,DX (!REX2)
ee: OUT DX,AL ee: OUT DX,AL (!REX2)
ef: OUT DX,eAX ef: OUT DX,eAX (!REX2)
# 0xf0 - 0xff # 0xf0 - 0xff
f0: LOCK (Prefix) f0: LOCK (Prefix)
f1: f1:
@ -386,14 +390,14 @@ AVXcode: 1
2e: vucomiss Vss,Wss (v1) | vucomisd Vsd,Wsd (66),(v1) 2e: vucomiss Vss,Wss (v1) | vucomisd Vsd,Wsd (66),(v1)
2f: vcomiss Vss,Wss (v1) | vcomisd Vsd,Wsd (66),(v1) 2f: vcomiss Vss,Wss (v1) | vcomisd Vsd,Wsd (66),(v1)
# 0x0f 0x30-0x3f # 0x0f 0x30-0x3f
30: WRMSR 30: WRMSR (!REX2)
31: RDTSC 31: RDTSC (!REX2)
32: RDMSR 32: RDMSR (!REX2)
33: RDPMC 33: RDPMC (!REX2)
34: SYSENTER 34: SYSENTER (!REX2)
35: SYSEXIT 35: SYSEXIT (!REX2)
36: 36:
37: GETSEC 37: GETSEC (!REX2)
38: escape # 3-byte escape 1 38: escape # 3-byte escape 1
39: 39:
3a: escape # 3-byte escape 2 3a: escape # 3-byte escape 2
@ -473,22 +477,22 @@ AVXcode: 1
7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqa32/64 Wx,Vx (66),(evo) | vmovdqu Wx,Vx (F3) | vmovdqu32/64 Wx,Vx (F3),(evo) | vmovdqu8/16 Wx,Vx (F2),(ev) 7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqa32/64 Wx,Vx (66),(evo) | vmovdqu Wx,Vx (F3) | vmovdqu32/64 Wx,Vx (F3),(evo) | vmovdqu8/16 Wx,Vx (F2),(ev)
# 0x0f 0x80-0x8f # 0x0f 0x80-0x8f
# Note: "forced64" is Intel CPU behavior (see comment about CALL insn). # Note: "forced64" is Intel CPU behavior (see comment about CALL insn).
80: JO Jz (f64) 80: JO Jz (f64) (!REX2)
81: JNO Jz (f64) 81: JNO Jz (f64) (!REX2)
82: JB/JC/JNAE Jz (f64) 82: JB/JC/JNAE Jz (f64) (!REX2)
83: JAE/JNB/JNC Jz (f64) 83: JAE/JNB/JNC Jz (f64) (!REX2)
84: JE/JZ Jz (f64) 84: JE/JZ Jz (f64) (!REX2)
85: JNE/JNZ Jz (f64) 85: JNE/JNZ Jz (f64) (!REX2)
86: JBE/JNA Jz (f64) 86: JBE/JNA Jz (f64) (!REX2)
87: JA/JNBE Jz (f64) 87: JA/JNBE Jz (f64) (!REX2)
88: JS Jz (f64) 88: JS Jz (f64) (!REX2)
89: JNS Jz (f64) 89: JNS Jz (f64) (!REX2)
8a: JP/JPE Jz (f64) 8a: JP/JPE Jz (f64) (!REX2)
8b: JNP/JPO Jz (f64) 8b: JNP/JPO Jz (f64) (!REX2)
8c: JL/JNGE Jz (f64) 8c: JL/JNGE Jz (f64) (!REX2)
8d: JNL/JGE Jz (f64) 8d: JNL/JGE Jz (f64) (!REX2)
8e: JLE/JNG Jz (f64) 8e: JLE/JNG Jz (f64) (!REX2)
8f: JNLE/JG Jz (f64) 8f: JNLE/JG Jz (f64) (!REX2)
# 0x0f 0x90-0x9f # 0x0f 0x90-0x9f
90: SETO Eb | kmovw/q Vk,Wk | kmovb/d Vk,Wk (66) 90: SETO Eb | kmovw/q Vk,Wk | kmovb/d Vk,Wk (66)
91: SETNO Eb | kmovw/q Mv,Vk | kmovb/d Mv,Vk (66) 91: SETNO Eb | kmovw/q Mv,Vk | kmovb/d Mv,Vk (66)