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riscv: dts: renesas: Add specific RZ/Five cache compatible

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When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.

Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.

Acked-by: Ben Zong-You Xie <ben717@andestech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20250512-sphere-plenty-8ce4cd772745@spud
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Conor Dooley 2025-05-12 14:48:15 +01:00 • committed by Geert Uytterhoeven
parent fb30a7c596
commit 1064013303
1 changed files with 2 additions and 1 deletions
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3
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
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@ -143,7 +143,8 @@
};
l2cache: cache-controller@13400000 {
compatible = "andestech,ax45mp-cache", "cache";
compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
"cache";
reg = <0x0 0x13400000 0x0 0x100000>;
interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
cache-size = <0x40000>;