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gpio: pmic-eic-sprd: Configure the bit corresponding to the EIC through offset

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A bank PMIC EIC contains 16 EICs, and the operating registers
are BIT0-BIT15, such as BIT0 of the register operated by EIC0.
Using the one-dimensional array reg[CACHE_NR_REGS] for maintenance
will cause the configuration of other EICs to be affected when
operating a certain EIC. In order to solve this problem, configure
the bit corresponding to the EIC through offset.

Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
Reviewed-by: Chunyan Zhang <zhang.lyra@gmail.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
Wenhua Lin 2024-01-02 16:28:29 +08:00 • committed by Bartosz Golaszewski
parent f34fd6ee1b
commit 0f57b21300
1 changed files with 10 additions and 9 deletions
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19
drivers/gpio/gpio-pmic-eic-sprd.c
View file

@ -151,8 +151,8 @@ static void sprd_pmic_eic_irq_mask(struct irq_data *data)
struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
u32 offset = irqd_to_hwirq(data); u32 offset = irqd_to_hwirq(data);
pmic_eic->reg[REG_IE] = 0; pmic_eic->reg[REG_IE] &= ~BIT(offset);
pmic_eic->reg[REG_TRIG] = 0; pmic_eic->reg[REG_TRIG] &= ~BIT(offset);
gpiochip_disable_irq(chip, offset); gpiochip_disable_irq(chip, offset);
} }
@ -165,8 +165,8 @@ static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
gpiochip_enable_irq(chip, offset); gpiochip_enable_irq(chip, offset);
pmic_eic->reg[REG_IE] = 1; pmic_eic->reg[REG_IE] |= BIT(offset);
pmic_eic->reg[REG_TRIG] = 1; pmic_eic->reg[REG_TRIG] |= BIT(offset);
} }
static int sprd_pmic_eic_irq_set_type(struct irq_data *data, static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
@ -174,13 +174,14 @@ static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
{ {
struct gpio_chip *chip = irq_data_get_irq_chip_data(data); struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
u32 offset = irqd_to_hwirq(data);
switch (flow_type) { switch (flow_type) {
case IRQ_TYPE_LEVEL_HIGH: case IRQ_TYPE_LEVEL_HIGH:
pmic_eic->reg[REG_IEV] = 1; pmic_eic->reg[REG_IEV] |= BIT(offset);
break; break;
case IRQ_TYPE_LEVEL_LOW: case IRQ_TYPE_LEVEL_LOW:
pmic_eic->reg[REG_IEV] = 0; pmic_eic->reg[REG_IEV] &= ~BIT(offset);
break; break;
case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_EDGE_FALLING:
@ -222,15 +223,15 @@ static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1); sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
} else { } else {
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
pmic_eic->reg[REG_IEV]); !!(pmic_eic->reg[REG_IEV] & BIT(offset)));
} }
/* Set irq unmask */ /* Set irq unmask */
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
pmic_eic->reg[REG_IE]); !!(pmic_eic->reg[REG_IE] & BIT(offset)));
/* Generate trigger start pulse for debounce EIC */ /* Generate trigger start pulse for debounce EIC */
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
pmic_eic->reg[REG_TRIG]); !!(pmic_eic->reg[REG_TRIG] & BIT(offset)));
mutex_unlock(&pmic_eic->buslock); mutex_unlock(&pmic_eic->buslock);
} }