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SoCFPGA DTS updates for v6.15

Browse source 
- Updates to dt-bindings
         - Document Agilex5 NAND daughter board
         - Convert Stratix10 FPGA Manager to json-schema
         - Convert Stratix10 Service Layer to json-schema
         - Add document for Terasic's DE10-nano board
 - Add support for Agilex5 NAND daughter board
 - Add basic support for Terasic's DE10-nano board
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Merge tag 'socfpga_dts_updates_for_v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt

SoCFPGA DTS updates for v6.15
- Updates to dt-bindings
        - Document Agilex5 NAND daughter board
        - Convert Stratix10 FPGA Manager to json-schema
        - Convert Stratix10 Service Layer to json-schema
        - Add document for Terasic's DE10-nano board
- Add support for Agilex5 NAND daughter board
- Add basic support for Terasic's DE10-nano board

* tag 'socfpga_dts_updates_for_v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: socfpga: agilex: Add dma channel id for spi
  arm64: dts: socfpga: agilex5: add led and memory nodes
  arm64: dts: intel: socfpga_agilex: add frequencies to internal oscillators
  ARM: dts: socfpga: Add basic support for Terrasic's de10-nano
  dt-bindings: altera: Add compatible for Terasic's DE10-nano
  arm64: dts: socfpga: agilex5: add qspi flash node
  dt-bindings: firmware: stratix10: Convert to json-schema
  dt-bindings: fpga: stratix10: Convert to json-schema
  arm64: dts: socfpga: agilex5: fix gpio0 address
  arm64: dts: socfpga: agilex5: add NAND daughter board
  dt-bindings: intel: document Agilex5 NAND daughter board

Link: https://lore.kernel.org/r/20250326121152.1739873-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-05-09 22:34:37 +02:00
commit 0d57ac1f92
13 changed files with 376 additions and 77 deletions
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1
Documentation/devicetree/bindings/arm/altera.yaml
View file

@ -47,6 +47,7 @@ properties:
- novtech,chameleon96
- samtec,vining
- terasic,de0-atlas
- terasic,de10-nano
- terasic,socfpga-cyclone5-sockit
- const: altr,socfpga-cyclone5
- const: altr,socfpga

1
Documentation/devicetree/bindings/arm/intel,socfpga.yaml
View file

@ -25,6 +25,7 @@ properties:
items:
- enum:
- intel,socfpga-agilex5-socdk
- intel,socfpga-agilex5-socdk-nand
- const: intel,socfpga-agilex5
additionalProperties: true

57
Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
View file

@ -1,57 +0,0 @@
Intel Service Layer Driver for Stratix10 SoC
============================================
Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
configured from HPS, there needs to be a way for HPS to notify SDM the
location and size of the configuration data. Then SDM will get the
configuration data from that location and perform the FPGA configuration.
To meet the whole system security needs and support virtual machine requesting
communication with SDM, only the secure world of software (EL3, Exception
Layer 3) can interface with SDM. All software entities running on other
exception layers must channel through the EL3 software whenever it needs
service from SDM.
Intel Stratix10 service layer driver, running at privileged exception level
(EL1, Exception Layer 1), interfaces with the service providers and provides
the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
driver also manages secure monitor call (SMC) to communicate with secure monitor
code running in EL3.
Required properties:
-------------------
The svc node has the following mandatory properties, must be located under
the firmware node.
- compatible: "intel,stratix10-svc" or "intel,agilex-svc"
- method: smc or hvc
smc - Secure Monitor Call
hvc - Hypervisor Call
- memory-region:
phandle to the reserved memory node. See
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
for details
Example:
-------
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
service_reserved: svcbuffer@0 {
compatible = "shared-dma-pool";
reg = <0x0 0x0 0x0 0x1000000>;
alignment = <0x1000>;
no-map;
};
};
firmware {
svc {
compatible = "intel,stratix10-svc";
method = "smc";
memory-region = <&service_reserved>;
};
};

93
Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml Normal file
View file

@ -0,0 +1,93 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/firmware/intel,stratix10-svc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel Service Layer Driver for Stratix10 SoC
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
- Mahesh Rao <mahesh.rao@altera.com>
description: >
Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
configured from HPS, there needs to be a way for HPS to notify SDM the
location and size of the configuration data. Then SDM will get the
configuration data from that location and perform the FPGA configuration.
To meet the whole system security needs and support virtual machine requesting
communication with SDM, only the secure world of software (EL3, Exception
Layer 3) can interface with SDM. All software entities running on other
exception layers must channel through the EL3 software whenever it needs
service from SDM.
Intel Stratix10 service layer driver, running at privileged exception level
(EL1, Exception Layer 1), interfaces with the service providers and provides
the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
driver also manages secure monitor call (SMC) to communicate with secure monitor
code running in EL3.
properties:
compatible:
enum:
- intel,stratix10-svc
- intel,agilex-svc
method:
description: |
Supervisory call method to be used to communicate with the
secure service layer.
Permitted values are:
- "smc" : SMC #0, following the SMCCC
- "hvc" : HVC #0, following the SMCCC
$ref: /schemas/types.yaml#/definitions/string-array
enum:
- smc
- hvc
memory-region:
maxItems: 1
description:
reserved memory region for the service layer driver to
communicate with the secure device manager.
fpga-mgr:
$ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml
description: Optional child node for fpga manager to perform fabric configuration.
required:
- compatible
- method
- memory-region
additionalProperties: false
examples:
- |
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
service_reserved: svcbuffer@0 {
compatible = "shared-dma-pool";
reg = <0x0 0x0 0x0 0x1000000>;
alignment = <0x1000>;
no-map;
};
};
firmware {
svc {
compatible = "intel,stratix10-svc";
method = "smc";
memory-region = <&service_reserved>;
fpga-mgr {
compatible = "intel,stratix10-soc-fpga-mgr";
};
};
};

36
Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml Normal file
View file

@ -0,0 +1,36 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel Stratix10 SoC FPGA Manager
maintainers:
- Mahesh Rao <mahesh.rao@altera.com>
- Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
- Niravkumar L Rabara <nirav.rabara@altera.com>
description:
The Intel Stratix10 SoC consists of a 64-bit quad-core ARM Cortex A53 hard
processor system (HPS) and a Secure Device Manager (SDM). The Stratix10
SoC FPGA Manager driver is used to configure/reconfigure the FPGA fabric
on the die.The driver communicates with SDM/ATF via the stratix10-svc
platform driver for performing its operations.
properties:
compatible:
enum:
- intel,stratix10-soc-fpga-mgr
- intel,agilex-soc-fpga-mgr
required:
- compatible
additionalProperties: false
examples:
- |
fpga-mgr {
compatible = "intel,stratix10-soc-fpga-mgr";
};

18
Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt
View file

@ -1,18 +0,0 @@
Intel Stratix10 SoC FPGA Manager
Required properties:
The fpga_mgr node has the following mandatory property, must be located under
firmware/svc node.
- compatible : should contain "intel,stratix10-soc-fpga-mgr" or
"intel,agilex-soc-fpga-mgr"
Example:
firmware {
svc {
fpga_mgr: fpga-mgr {
compatible = "intel,stratix10-soc-fpga-mgr";
};
};
};

1
arch/arm/boot/dts/intel/socfpga/Makefile
View file

@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_de10nano.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sodia.dtb \

95
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts Normal file
View file

@ -0,0 +1,95 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017, Intel Corporation
*
* based on socfpga_cyclone5_de0_nano_soc.dts
*/
/dts-v1/;
#include "socfpga_cyclone5.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Terasic DE10-Nano";
compatible = "terasic,de10-nano", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
/* 1 GiB */
device_type = "memory";
reg = <0x0 0x40000000>;
};
soc {
fpga: bus@ff200000 {
compatible = "simple-bus";
reg = <0xff200000 0x00200000>;
ranges = <0x00000000 0xff200000 0x00200000>;
#address-cells = <1>;
#size-cells = <1>;
/*
* Here the devices will appear if an FPGA image is
* loaded. Their description is expected to be added
* using a device tree overlay that matches the image.
*/
};
};
};
&gmac1 {
/* Uses a KSZ9031RNX phy */
phy-mode = "rgmii-id";
rxd0-skew-ps = <420>;
rxd1-skew-ps = <420>;
rxd2-skew-ps = <420>;
rxd3-skew-ps = <420>;
txen-skew-ps = <0>;
rxdv-skew-ps = <420>;
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
accelerometer@53 {
compatible = "adi,adxl345";
reg = <0x53>;
/* HPS_GSENSOR_INT is routed to UART0_RX/CAN0_RX/SPIM0_SS1/HPS_GPIO61 */
interrupt-parent = <&portc>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "INT1";
};
};
&mmc0 {
/* micro SD card socket J11 */
status = "okay";
};
&uart0 {
/*
* Accessible via USB (FT232R) on Mini-USB plug J4
* RX = TRACE_D0/SPIS0_CLK/UART0_RX/HPS_GPIO49
* TX = TRACE_D1/SPIS0_MOSI/UART0_TX/HPS_GPIO50
* no handshaking lines
*/
clock-frequency = <100000000>;
};

1
arch/arm64/boot/dts/intel/Makefile
View file

@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb \
socfpga_agilex5_socdk.dtb \
socfpga_agilex5_socdk_nand.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb

6
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View file

@ -114,11 +114,13 @@
cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
cb_intosc_ls_clk: cb-intosc-ls-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <400000000>;
};
f2s_free_clk: f2s-free-clk {
@ -457,6 +459,8 @@
reg-io-width = <4>;
num-cs = <4>;
clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
dmas = <&pdma 16>, <&pdma 17>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -471,6 +475,8 @@
reg-io-width = <4>;
num-cs = <4>;
clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
dmas = <&pdma 20>, <&pdma 21>;
dma-names = "tx", "rx";
status = "disabled";
};

4
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
View file

@ -222,9 +222,9 @@
status = "disabled";
};
gpio0: gpio@ffc03200 {
gpio0: gpio@10c03200 {
compatible = "snps,dw-apb-gpio";
reg = <0xffc03200 0x100>;
reg = <0x10c03200 0x100>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst GPIO0_RESET>;

51
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
View file

@ -15,6 +15,26 @@
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
label = "hps_led0";
gpios = <&porta 11 GPIO_ACTIVE_HIGH>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0x0 0x80000000 0x0 0x0>;
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
@ -25,6 +45,37 @@
clock-frequency = <25000000>;
};
&qspi {
status = "okay";
flash@0 {
compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,read-delay = <2>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
qspi_boot: partition@0 {
label = "u-boot";
reg = <0x0 0x04200000>;
};
root: partition@4200000 {
label = "root";
reg = <0x04200000 0x0be00000>;
};
};
};
};
&uart0 {
status = "okay";
};

89
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts Normal file
View file

@ -0,0 +1,89 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2025, Altera Corporation
*/
#include "socfpga_agilex5.dtsi"
/ {
model = "SoCFPGA Agilex5 SoCDK NAND daughter board";
compatible = "intel,socfpga-agilex5-socdk-nand", "intel,socfpga-agilex5";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led0 {
label = "hps_led0";
gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
};
led1 {
label = "hps_led1";
gpios = <&porta 7 GPIO_ACTIVE_HIGH>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0x0 0x80000000 0x0 0x0>;
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i3c0 {
status = "okay";
};
&i3c1 {
status = "okay";
};
&nand {
status = "okay";
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-bus-width = <8>;
partition@0 {
label = "u-boot";
reg = <0 0x200000>;
};
partition@200000 {
label = "root";
reg = <0x200000 0xffe00000>;
};
};
};
&osc1 {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};
&watchdog0 {
status = "okay";
};