arm64: dts: mediatek: mt7988: add cci node

Add cci devicetree node for cpu frequency scaling.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250706132213.20412-9-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Frank Wunderlich 2025-07-06 15:22:03 +02:00 committed by AngeloGioacchino Del Regno
parent bd9e0f5d90
commit 0cbdb6d046
No known key found for this signature in database
GPG key ID: 9A3604CFAD978478

View file

@ -12,6 +12,35 @@
#address-cells = <2>;
#size-cells = <2>;
cci: cci {
compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci";
clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
<&topckgen CLK_TOP_XTAL>;
clock-names = "cci", "intermediate";
operating-points-v2 = <&cci_opp>;
};
cci_opp: opp-table-cci {
compatible = "operating-points-v2";
opp-shared;
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-microvolt = <850000>;
};
opp-660000000 {
opp-hz = /bits/ 64 <660000000>;
opp-microvolt = <850000>;
};
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <850000>;
};
opp-1080000000 {
opp-hz = /bits/ 64 <1080000000>;
opp-microvolt = <900000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -25,6 +54,7 @@
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
mediatek,cci = <&cci>;
};
cpu1: cpu@1 {
@ -36,6 +66,7 @@
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
mediatek,cci = <&cci>;
};
cpu2: cpu@2 {
@ -47,6 +78,7 @@
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
mediatek,cci = <&cci>;
};
cpu3: cpu@3 {
@ -58,6 +90,7 @@
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
mediatek,cci = <&cci>;
};
cluster0_opp: opp-table-0 {