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drm/i915: s/cdclk_state/cdclk_config/

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I want to have a higher level cdclk state object so let's rename
the current lower level thing to cdclk_config (because I lack
imagination).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-8-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
This commit is contained in:
Ville Syrjälä 2020-01-20 19:47:17 +02:00
parent 65c88a866d
commit 0bb94e0383
6 changed files with 246 additions and 242 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

426
drivers/gpu/drm/i915/display/intel_cdclk.c
View file

File diff suppressed because it is too large Load diff

18
drivers/gpu/drm/i915/display/intel_cdclk.h
View file

@ -12,7 +12,7 @@
struct drm_i915_private;
struct intel_atomic_state;
struct intel_cdclk_state;
struct intel_cdclk_config;
struct intel_crtc_state;
struct intel_cdclk_vals {
@ -29,22 +29,22 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
void intel_update_cdclk(struct drm_i915_private *dev_priv);
void intel_update_rawclk(struct drm_i915_private *dev_priv);
bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
const struct intel_cdclk_state *b);
bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b);
void intel_cdclk_clear_state(struct intel_atomic_state *state);
void intel_cdclk_swap_state(struct intel_atomic_state *state);
void
intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *old_state,
const struct intel_cdclk_state *new_state,
const struct intel_cdclk_config *old_state,
const struct intel_cdclk_config *new_state,
enum pipe pipe);
void
intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *old_state,
const struct intel_cdclk_state *new_state,
const struct intel_cdclk_config *old_state,
const struct intel_cdclk_config *new_state,
enum pipe pipe);
void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
const char *context);
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
const char *context);
int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
#endif /* __INTEL_CDCLK_H__ */

2
drivers/gpu/drm/i915/display/intel_display.c
View file

@ -17576,7 +17576,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
void intel_modeset_init_hw(struct drm_i915_private *i915)
{
intel_update_cdclk(i915);
intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
}

8
drivers/gpu/drm/i915/display/intel_display_power.c
View file

@ -1050,7 +1050,7 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_state cdclk_state = {};
struct intel_cdclk_config cdclk_config = {};
if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) {
tgl_disable_dc3co(dev_priv);
@ -1059,9 +1059,9 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
dev_priv->display.get_cdclk(dev_priv, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_config));
gen9_assert_dbuf_enabled(dev_priv);
@ -4696,7 +4696,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_update_cdclk(dev_priv);
intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
}
/*

14
drivers/gpu/drm/i915/display/intel_display_types.h
View file

@ -464,17 +464,17 @@ struct intel_atomic_state {
struct {
/*
* Logical state of cdclk (used for all scaling, watermark,
* etc. calculations and checks). This is computed as if all
* enabled crtcs were active.
* Logical configuration of cdclk (used for all scaling,
* watermark, etc. calculations and checks). This is
* computed as if all enabled crtcs were active.
*/
struct intel_cdclk_state logical;
struct intel_cdclk_config logical;
/*
* Actual state of cdclk, can be different from the logical
* state only when all crtc's are DPMS off.
* Actual configuration of cdclk, can be different from the
* logical configuration only when all crtc's are DPMS off.
*/
struct intel_cdclk_state actual;
struct intel_cdclk_config actual;
int force_min_cdclk;
bool force_min_cdclk_changed;

20
drivers/gpu/drm/i915/i915_drv.h
View file

@ -253,18 +253,18 @@ struct sdvo_device_mapping {
struct intel_connector;
struct intel_encoder;
struct intel_atomic_state;
struct intel_cdclk_config;
struct intel_crtc_state;
struct intel_initial_plane_config;
struct intel_crtc;
struct intel_limit;
struct dpll;
struct intel_cdclk_state;
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state);
struct intel_cdclk_config *cdclk_config);
void (*set_cdclk)(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe);
int (*get_fifo_size)(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane);
@ -878,7 +878,7 @@ struct intel_wm_config {
bool sprites_scaled;
};
struct intel_cdclk_state {
struct intel_cdclk_config {
unsigned int cdclk, vco, ref, bypass;
u8 voltage_level;
};
@ -1009,17 +1009,17 @@ struct drm_i915_private {
*/
struct {
/*
* The current logical cdclk state.
* The current logical cdclk configuration.
* See intel_atomic_state.cdclk.logical
*/
struct intel_cdclk_state logical;
struct intel_cdclk_config logical;
/*
* The current actual cdclk state.
* The current actual cdclk configuration.
* See intel_atomic_state.cdclk.actual
*/
struct intel_cdclk_state actual;
/* The current hardware cdclk state */
struct intel_cdclk_state hw;
struct intel_cdclk_config actual;
/* The current hardware cdclk configuration */
struct intel_cdclk_config hw;
/* cdclk, divider, and ratio table from bspec */
const struct intel_cdclk_vals *table;