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clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics

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This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Eugen Hristev 2020-11-19 17:43:11 +02:00 • committed by Stephen Boyd
parent e26b3006ff
commit 0bb4623f13
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/at91/sama7g5.c
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@ -775,13 +775,13 @@ static const struct clk_pll_characteristics pll_characteristics = {
/* MCK0 characteristics. */
static const struct clk_master_characteristics mck0_characteristics = {
.output = { .min = 140000000, .max = 200000000 },
.divisors = { 1, 2, 4, 3 },
.divisors = { 1, 2, 4, 3, 5 },
.have_div3_pres = 1,
};
/* MCK0 layout. */
static const struct clk_master_layout mck0_layout = {
.mask = 0x373,
.mask = 0x773,
.pres_shift = 4,
.offset = 0x28,
};