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net/mlx5e: Expose FEC counters via ethtool

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Add FEC counters' statistics of corrected_blocks and
uncorrectable_blocks, along with their lanes via ethtool.

HW supports corrected_blocks and uncorrectable_blocks counters both for
RS-FEC mode and FC-FEC mode. In FC mode these counters are accumulated
per lane, while in RS mode the correction method crosses lanes, thus
only total corrected_blocks and uncorrectable_blocks are reported in
this mode.

Signed-off-by: Lama Kayal <lkayal@nvidia.com>
Reviewed-by: Gal Pressman <gal@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Lama Kayal 2021-09-13 16:06:35 +03:00 • committed by Saeed Mahameed
parent f79a609ea6
commit 0a1498ebfa
1 changed files with 98 additions and 3 deletions
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101
drivers/net/ethernet/mellanox/mlx5/core/en_stats.c
View file

@ -35,6 +35,7 @@
#include "en_accel/tls.h" #include "en_accel/tls.h"
#include "en_accel/en_accel.h" #include "en_accel/en_accel.h"
#include "en/ptp.h" #include "en/ptp.h"
#include "en/port.h"
static unsigned int stats_grps_num(struct mlx5e_priv *priv) static unsigned int stats_grps_num(struct mlx5e_priv *priv)
{ {
@ -1158,12 +1159,99 @@ static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy)
mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
} }
void mlx5e_stats_fec_get(struct mlx5e_priv *priv, static int fec_num_lanes(struct mlx5_core_dev *dev)
struct ethtool_fec_stats *fec_stats) {
u32 out[MLX5_ST_SZ_DW(pmlp_reg)] = {};
u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {};
int err;
MLX5_SET(pmlp_reg, in, local_port, 1);
err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
MLX5_REG_PMLP, 0, 0);
if (err)
return 0;
return MLX5_GET(pmlp_reg, out, width);
}
static int fec_active_mode(struct mlx5_core_dev *mdev)
{
unsigned long fec_active_long;
u32 fec_active;
if (mlx5e_get_fec_mode(mdev, &fec_active, NULL))
return MLX5E_FEC_NOFEC;
fec_active_long = fec_active;
return find_first_bit(&fec_active_long, sizeof(unsigned long) * BITS_PER_BYTE);
}
#define MLX5E_STATS_SET_FEC_BLOCK(idx) ({ \
fec_stats->corrected_blocks.lanes[(idx)] = \
MLX5E_READ_CTR64_BE_F(ppcnt, phys_layer_cntrs, \
fc_fec_corrected_blocks_lane##idx); \
fec_stats->uncorrectable_blocks.lanes[(idx)] = \
MLX5E_READ_CTR64_BE_F(ppcnt, phys_layer_cntrs, \
fc_fec_uncorrectable_blocks_lane##idx); \
})
static void fec_set_fc_stats(struct ethtool_fec_stats *fec_stats,
u32 *ppcnt, u8 lanes)
{
if (lanes > 3) { /* 4 lanes */
MLX5E_STATS_SET_FEC_BLOCK(3);
MLX5E_STATS_SET_FEC_BLOCK(2);
}
if (lanes > 1) /* 2 lanes */
MLX5E_STATS_SET_FEC_BLOCK(1);
if (lanes > 0) /* 1 lane */
MLX5E_STATS_SET_FEC_BLOCK(0);
}
static void fec_set_rs_stats(struct ethtool_fec_stats *fec_stats, u32 *ppcnt)
{
fec_stats->corrected_blocks.total =
MLX5E_READ_CTR64_BE_F(ppcnt, phys_layer_cntrs,
rs_fec_corrected_blocks);
fec_stats->uncorrectable_blocks.total =
MLX5E_READ_CTR64_BE_F(ppcnt, phys_layer_cntrs,
rs_fec_uncorrectable_blocks);
}
static void fec_set_block_stats(struct mlx5e_priv *priv,
struct ethtool_fec_stats *fec_stats)
{
struct mlx5_core_dev *mdev = priv->mdev;
u32 out[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
int mode = fec_active_mode(mdev);
if (mode == MLX5E_FEC_NOFEC)
return;
MLX5_SET(ppcnt_reg, in, local_port, 1);
MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
if (mlx5_core_access_reg(mdev, in, sz, outl, sz, MLX5_REG_PPCNT, 0, 0))
return;
switch (mode) {
case MLX5E_FEC_RS_528_514:
case MLX5E_FEC_RS_544_514:
case MLX5E_FEC_LLRS_272_257_1:
fec_set_rs_stats(fec_stats, out);
return;
case MLX5E_FEC_FIRECODE:
fec_set_fc_stats(fec_stats, out, fec_num_lanes(mdev));
}
}
static void fec_set_corrected_bits_total(struct mlx5e_priv *priv,
struct ethtool_fec_stats *fec_stats)
{ {
u32 ppcnt_phy_statistical[MLX5_ST_SZ_DW(ppcnt_reg)]; u32 ppcnt_phy_statistical[MLX5_ST_SZ_DW(ppcnt_reg)];
struct mlx5_core_dev *mdev = priv->mdev; struct mlx5_core_dev *mdev = priv->mdev;
u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
@ -1181,6 +1269,13 @@ void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
phy_corrected_bits); phy_corrected_bits);
} }
void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
struct ethtool_fec_stats *fec_stats)
{
fec_set_corrected_bits_total(priv, fec_stats);
fec_set_block_stats(priv, fec_stats);
}
#define PPORT_ETH_EXT_OFF(c) \ #define PPORT_ETH_EXT_OFF(c) \
MLX5_BYTE_OFF(ppcnt_reg, \ MLX5_BYTE_OFF(ppcnt_reg, \
counter_set.eth_extended_cntrs_grp_data_layout.c##_high) counter_set.eth_extended_cntrs_grp_data_layout.c##_high)