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rtase: Implement net_device_ops
1. Implement .ndo_set_rx_mode so that the device can change address list filtering. 2. Implement .ndo_set_mac_address so that mac address can be changed. 3. Implement .ndo_change_mtu so that mtu can be changed. 4. Implement .ndo_tx_timeout to perform related processing when the transmitter does not make any progress. 5. Implement .ndo_get_stats64 to provide statistics that are called when the user wants to get network device usage. 6. Implement .ndo_vlan_rx_add_vid to register VLAN ID when the device supports VLAN filtering. 7. Implement .ndo_vlan_rx_kill_vid to unregister VLAN ID when the device supports VLAN filtering. 8. Implement the .ndo_setup_tc to enable setting any "tc" scheduler, classifier or action on dev. 9. Implement .ndo_fix_features enables adjusting requested feature flags based on device-specific constraints. 10. Implement .ndo_set_features enables updating device configuration to new features. Signed-off-by: Justin Lai <justinlai0215@realtek.com> Link: https://patch.msgid.link/20240904032114.247117-9-justinlai0215@realtek.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Justin Lai
Jakub Kicinski
parent
cf7226c808
commit
0796004899
1 changed files with 235 additions and 0 deletions
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@ -1417,6 +1417,11 @@ err_dma_0:
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return NETDEV_TX_OK;
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}
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static void rtase_set_rx_mode(struct net_device *dev)
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{
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rtase_hw_set_rx_packet_filter(dev);
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}
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static void rtase_enable_eem_write(const struct rtase_private *tp)
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{
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u8 val;
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@ -1449,10 +1454,240 @@ static void rtase_rar_set(const struct rtase_private *tp, const u8 *addr)
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rtase_w16(tp, RTASE_LBK_CTRL, RTASE_LBK_ATLD | RTASE_LBK_CLR);
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}
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static int rtase_set_mac_address(struct net_device *dev, void *p)
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{
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struct rtase_private *tp = netdev_priv(dev);
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int ret;
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ret = eth_mac_addr(dev, p);
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if (ret)
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return ret;
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rtase_rar_set(tp, dev->dev_addr);
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return 0;
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}
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static int rtase_change_mtu(struct net_device *dev, int new_mtu)
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{
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dev->mtu = new_mtu;
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netdev_update_features(dev);
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return 0;
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}
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static void rtase_wait_for_quiescence(const struct net_device *dev)
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{
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struct rtase_private *tp = netdev_priv(dev);
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struct rtase_int_vector *ivec;
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u32 i;
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for (i = 0; i < tp->int_nums; i++) {
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ivec = &tp->int_vector[i];
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synchronize_irq(ivec->irq);
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/* wait for any pending NAPI task to complete */
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napi_disable(&ivec->napi);
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}
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rtase_irq_dis_and_clear(tp);
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for (i = 0; i < tp->int_nums; i++) {
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ivec = &tp->int_vector[i];
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napi_enable(&ivec->napi);
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}
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}
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static void rtase_sw_reset(struct net_device *dev)
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{
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struct rtase_private *tp = netdev_priv(dev);
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int ret;
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netif_stop_queue(dev);
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netif_carrier_off(dev);
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rtase_hw_reset(dev);
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/* let's wait a bit while any (async) irq lands on */
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rtase_wait_for_quiescence(dev);
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rtase_tx_clear(tp);
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rtase_rx_clear(tp);
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ret = rtase_init_ring(dev);
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if (ret) {
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netdev_err(dev, "unable to init ring\n");
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rtase_free_desc(tp);
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return;
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}
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rtase_hw_config(dev);
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/* always link, so start to transmit & receive */
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rtase_hw_start(dev);
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netif_carrier_on(dev);
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netif_wake_queue(dev);
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}
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static void rtase_dump_tally_counter(const struct rtase_private *tp)
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{
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dma_addr_t paddr = tp->tally_paddr;
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u32 cmd = lower_32_bits(paddr);
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u32 val;
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int err;
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rtase_w32(tp, RTASE_DTCCR4, upper_32_bits(paddr));
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rtase_w32(tp, RTASE_DTCCR0, cmd);
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rtase_w32(tp, RTASE_DTCCR0, cmd | RTASE_COUNTER_DUMP);
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err = read_poll_timeout(rtase_r32, val, !(val & RTASE_COUNTER_DUMP),
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10, 250, false, tp, RTASE_DTCCR0);
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if (err == -ETIMEDOUT)
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netdev_err(tp->dev, "error occurred in dump tally counter\n");
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}
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static void rtase_dump_state(const struct net_device *dev)
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{
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const struct rtase_private *tp = netdev_priv(dev);
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int max_reg_size = RTASE_PCI_REGS_SIZE;
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const struct rtase_counters *counters;
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const struct rtase_ring *ring;
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u32 dword_rd;
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int n = 0;
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ring = &tp->tx_ring[0];
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netdev_err(dev, "Tx descriptor info:\n");
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netdev_err(dev, "Tx curIdx = 0x%x\n", ring->cur_idx);
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netdev_err(dev, "Tx dirtyIdx = 0x%x\n", ring->dirty_idx);
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netdev_err(dev, "Tx phyAddr = %pad\n", &ring->phy_addr);
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ring = &tp->rx_ring[0];
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netdev_err(dev, "Rx descriptor info:\n");
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netdev_err(dev, "Rx curIdx = 0x%x\n", ring->cur_idx);
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netdev_err(dev, "Rx dirtyIdx = 0x%x\n", ring->dirty_idx);
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netdev_err(dev, "Rx phyAddr = %pad\n", &ring->phy_addr);
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netdev_err(dev, "Device Registers:\n");
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netdev_err(dev, "Chip Command = 0x%02x\n",
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rtase_r8(tp, RTASE_CHIP_CMD));
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netdev_err(dev, "IMR = %08x\n", rtase_r32(tp, RTASE_IMR0));
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netdev_err(dev, "ISR = %08x\n", rtase_r32(tp, RTASE_ISR0));
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netdev_err(dev, "Boot Ctrl Reg(0xE004) = %04x\n",
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rtase_r16(tp, RTASE_BOOT_CTL));
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netdev_err(dev, "EPHY ISR(0xE014) = %04x\n",
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rtase_r16(tp, RTASE_EPHY_ISR));
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netdev_err(dev, "EPHY IMR(0xE016) = %04x\n",
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rtase_r16(tp, RTASE_EPHY_IMR));
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netdev_err(dev, "CLKSW SET REG(0xE018) = %04x\n",
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rtase_r16(tp, RTASE_CLKSW_SET));
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netdev_err(dev, "Dump PCI Registers:\n");
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while (n < max_reg_size) {
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if ((n % RTASE_DWORD_MOD) == 0)
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netdev_err(tp->dev, "0x%03x:\n", n);
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pci_read_config_dword(tp->pdev, n, &dword_rd);
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netdev_err(tp->dev, "%08x\n", dword_rd);
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n += 4;
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}
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netdev_err(dev, "Dump tally counter:\n");
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counters = tp->tally_vaddr;
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rtase_dump_tally_counter(tp);
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netdev_err(dev, "tx_packets %lld\n",
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le64_to_cpu(counters->tx_packets));
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netdev_err(dev, "rx_packets %lld\n",
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le64_to_cpu(counters->rx_packets));
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netdev_err(dev, "tx_errors %lld\n",
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le64_to_cpu(counters->tx_errors));
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netdev_err(dev, "rx_errors %d\n",
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le32_to_cpu(counters->rx_errors));
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netdev_err(dev, "rx_missed %d\n",
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le16_to_cpu(counters->rx_missed));
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netdev_err(dev, "align_errors %d\n",
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le16_to_cpu(counters->align_errors));
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netdev_err(dev, "tx_one_collision %d\n",
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le32_to_cpu(counters->tx_one_collision));
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netdev_err(dev, "tx_multi_collision %d\n",
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le32_to_cpu(counters->tx_multi_collision));
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netdev_err(dev, "rx_unicast %lld\n",
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le64_to_cpu(counters->rx_unicast));
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netdev_err(dev, "rx_broadcast %lld\n",
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le64_to_cpu(counters->rx_broadcast));
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netdev_err(dev, "rx_multicast %d\n",
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le32_to_cpu(counters->rx_multicast));
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netdev_err(dev, "tx_aborted %d\n",
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le16_to_cpu(counters->tx_aborted));
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netdev_err(dev, "tx_underun %d\n",
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le16_to_cpu(counters->tx_underun));
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}
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static void rtase_tx_timeout(struct net_device *dev, unsigned int txqueue)
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{
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rtase_dump_state(dev);
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rtase_sw_reset(dev);
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}
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static void rtase_get_stats64(struct net_device *dev,
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struct rtnl_link_stats64 *stats)
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{
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const struct rtase_private *tp = netdev_priv(dev);
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const struct rtase_counters *counters;
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counters = tp->tally_vaddr;
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dev_fetch_sw_netstats(stats, dev->tstats);
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/* fetch additional counter values missing in stats collected by driver
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* from tally counter
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*/
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rtase_dump_tally_counter(tp);
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stats->rx_errors = tp->stats.rx_errors;
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stats->tx_errors = le64_to_cpu(counters->tx_errors);
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stats->rx_dropped = tp->stats.rx_dropped;
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stats->tx_dropped = tp->stats.tx_dropped;
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stats->multicast = tp->stats.multicast;
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stats->rx_length_errors = tp->stats.rx_length_errors;
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}
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static netdev_features_t rtase_fix_features(struct net_device *dev,
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netdev_features_t features)
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{
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netdev_features_t features_fix = features;
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/* not support TSO for jumbo frames */
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if (dev->mtu > ETH_DATA_LEN)
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features_fix &= ~NETIF_F_ALL_TSO;
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return features_fix;
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}
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static int rtase_set_features(struct net_device *dev,
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netdev_features_t features)
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{
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netdev_features_t features_set = features;
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features_set &= NETIF_F_RXALL | NETIF_F_RXCSUM |
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NETIF_F_HW_VLAN_CTAG_RX;
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if (features_set ^ dev->features)
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rtase_hw_set_features(dev, features_set);
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return 0;
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}
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static const struct net_device_ops rtase_netdev_ops = {
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.ndo_open = rtase_open,
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.ndo_stop = rtase_close,
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.ndo_start_xmit = rtase_start_xmit,
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.ndo_set_rx_mode = rtase_set_rx_mode,
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.ndo_set_mac_address = rtase_set_mac_address,
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.ndo_change_mtu = rtase_change_mtu,
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.ndo_tx_timeout = rtase_tx_timeout,
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.ndo_get_stats64 = rtase_get_stats64,
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.ndo_fix_features = rtase_fix_features,
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.ndo_set_features = rtase_set_features,
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};
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static void rtase_get_mac_address(struct net_device *dev)
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