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i.MX arm64 device tree for 6.9:

Browse source 
- New board support: Apalis eval v1.2 carrier board, Variscite
   VAR-SOM-MX93, phyBOARD-Segin-i.MX93.
 - A series from Adam Ford to enable bluetooth, configure multiple queues
   on eqos, remove unnecessary clock configuration for i.MX8 Beacon boards.
 - Several changesets from Alexander Stein to add i.MX8DXP support, enable
   audio and GPU for i.MX8QXP, re-parent MEDIA_MIPI_PHY1_REF clock for
   i.MX8MP, and improve MBA8xx board description.
 - A few dt-schema fixes from Fabio Estevam for i.MX8MM and i.MX93 devices.
 - A bunch of changes from Frank Li to improve i.MX8QM and i.MX8DXL
   support, correcting edma3 power-domains and interrupt numbers, adding
   I2C, FlexCAN and SMMU devices, etc.
 - A series from Frieder Schrempf to improve imx8mm-kontron board
   descriptions, disabling pulls, fixing up RTC device, adding EEPROM,
   and refactoring OSM-S module, etc.
 - A set of Data Modul i.MX8M Plus eDM SBC improvements from Marek Vasut.
 - A series from Shengjiu Wang to add PDM micphone and SPDIF sound card
   support for imx8mm-evk board.
 - A series of imx8mm-venice boards improvement from Tim Harvey to add
   TPM device, fix USB OTG VBUS etc.
 - Other small and random improvements on various boards.
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Merge tag 'imx-dt64-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX arm64 device tree for 6.9:

- New board support: Apalis eval v1.2 carrier board, Variscite
  VAR-SOM-MX93, phyBOARD-Segin-i.MX93.
- A series from Adam Ford to enable bluetooth, configure multiple queues
  on eqos, remove unnecessary clock configuration for i.MX8 Beacon boards.
- Several changesets from Alexander Stein to add i.MX8DXP support, enable
  audio and GPU for i.MX8QXP, re-parent MEDIA_MIPI_PHY1_REF clock for
  i.MX8MP, and improve MBA8xx board description.
- A few dt-schema fixes from Fabio Estevam for i.MX8MM and i.MX93 devices.
- A bunch of changes from Frank Li to improve i.MX8QM and i.MX8DXL
  support, correcting edma3 power-domains and interrupt numbers, adding
  I2C, FlexCAN and SMMU devices, etc.
- A series from Frieder Schrempf to improve imx8mm-kontron board
  descriptions, disabling pulls, fixing up RTC device, adding EEPROM,
  and refactoring OSM-S module, etc.
- A set of Data Modul i.MX8M Plus eDM SBC improvements from Marek Vasut.
- A series from Shengjiu Wang to add PDM micphone and SPDIF sound card
  support for imx8mm-evk board.
- A series of imx8mm-venice boards improvement from Tim Harvey to add
  TPM device, fix USB OTG VBUS etc.
- Other small and random improvements on various boards.

* tag 'imx-dt64-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (77 commits)
  arm64: dts: imx8mm-kontron-bl-osm-s: Fix Ethernet PHY compatible
  arm64: dts: imx8-apalis-v1.1: Remove reset-names from ethernet-phy
  arm64: dts: imx8mp-evk: Fix hdmi@3d node
  arm64: dts: imx93-var-som: Remove phy-supply from eqos
  arm64: dts: imx8mp-phyboard-pollux: Disable pull-up for CD GPIO
  arm64: dts: imx8mp-phyboard-pollux: Reduce drive strength for eqos tx lines
  arm64: dts: imx8mp-phyboard-pollux: Set debug uart muxing to 0x140
  arm64: dts: imx8mp-phyboard-pollux: Add and update rtc devicetree node
  arm64: dts: imx8mm-evk: Add spdif sound card support
  arm64: dts: mba8xx: Add missing #interrupt-cells
  arm64: dts: imx8mp: Set SPI NOR to max 40 MHz on Data Modul i.MX8M Plus eDM SBC
  arm64: dts: imx8mn: tqma8mqnl-mba8mx: Add USB DR overlay
  arm64: dts: imx8mq: tqma8mq-mba8mx: Add missing USB vbus supply
  arm64: dts: freescale: imx8mm/imx8mq: mba8mx: Use PCIe clock generator
  arm64: dts: imx8mn-beacon: Remove unnecessary clock configuration
  arm64: dts: imx8mn: Slow default video_pll clock rate
  arm64: dts: imx8mp-beacon: Configure multiple queues on eqos
  arm64: dts: imx8mp-beacon: Enable Bluetooth
  arm64: dts: freescale: minor whitespace cleanup
  arm64: dts: lx2160a: Fix DTS for full PL011 UART
  ...

Link: https://lore.kernel.org/r/20240226034147.233993-4-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-03-01 13:37:49 +01:00
commit 06d179e31c
63 changed files with 3749 additions and 404 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/boot/dts/nxp/ls/ls1021a.dtsi
View file

@ -810,6 +810,7 @@
snps,dis_rxdet_inp3_quirk;
usb3-lpm-capable;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
};
pcie@3400000 {

8
arch/arm64/boot/dts/freescale/Makefile
View file

@ -99,6 +99,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-8-x.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-7-x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
@ -152,7 +153,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtbo
imx8mn-tqma8mqnl-mba8mx-usbotg-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-usbotg.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-usbotg.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
@ -207,8 +210,10 @@ imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33-dtbs += imx8mq-tqma8mq-mba8mx.dtb imx8mq-
dtb-$(CONFIG_ARCH_MXC) += imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-eval.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-eval-v1.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-ixora-v1.1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval-v1.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
@ -218,10 +223,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo
imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo

10
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View file

@ -290,7 +290,7 @@
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1012a-dcfg",
"syscon";
reg = <0x0 0x1ee0000 0x0 0x10000>;
reg = <0x0 0x1ee0000 0x0 0x1000>;
big-endian;
};
@ -351,24 +351,26 @@
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
scl-gpios = <&gpio0 2 0>;
status = "disabled";
};
i2c1: i2c@2190000 {
compatible = "fsl,vf610-i2c";
compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
scl-gpios = <&gpio0 13 0>;
status = "disabled";
};
@ -499,6 +501,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
};
sata: sata@3200000 {
@ -550,6 +553,7 @@
<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
status = "disabled";
};

1
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View file

@ -485,7 +485,6 @@
<0x00030005 0x00000042>,
<0x00030006 0x0000004c>,
<0x00030007 0x00000056>;
big-endian;
#thermal-sensor-cells = <1>;
};

6
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View file

@ -591,6 +591,8 @@
reg = <0x00 0x03400000 0x0 0x00100000>,
<0x20 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
interrupt-names = "pme";
num-ib-windows = <24>;
num-ob-windows = <256>;
max-functions = /bits/ 8 <2>;
@ -628,6 +630,8 @@
reg = <0x00 0x03500000 0x0 0x00100000>,
<0x28 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <6>;
status = "disabled";
@ -664,6 +668,8 @@
reg = <0x00 0x03600000 0x0 0x00100000>,
<0x30 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <6>;
status = "disabled";

32
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View file

@ -949,34 +949,50 @@
};
uart0: serial@21c0000 {
compatible = "arm,sbsa-uart","arm,pl011";
compatible = "arm,pl011", "arm,primecell";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
clock-names = "uartclk", "apb_pclk";
reg = <0x0 0x21c0000 0x0 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
status = "disabled";
};
uart1: serial@21d0000 {
compatible = "arm,sbsa-uart","arm,pl011";
compatible = "arm,pl011", "arm,primecell";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
clock-names = "uartclk", "apb_pclk";
reg = <0x0 0x21d0000 0x0 0x1000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
status = "disabled";
};
uart2: serial@21e0000 {
compatible = "arm,sbsa-uart","arm,pl011";
compatible = "arm,pl011", "arm,primecell";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
clock-names = "uartclk", "apb_pclk";
reg = <0x0 0x21e0000 0x0 0x1000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
status = "disabled";
};
uart3: serial@21f0000 {
compatible = "arm,sbsa-uart","arm,pl011";
compatible = "arm,pl011", "arm,primecell";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
clock-names = "uartclk", "apb_pclk";
reg = <0x0 0x21f0000 0x0 0x1000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
status = "disabled";
};

26
arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.1.dtsi Normal file
View file

@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024 Toradex
*/
#include "imx8-apalis-eval.dtsi"
/* Apalis CAN1 */
&flexcan1 {
status = "okay";
};
/* Apalis CAN2 */
&flexcan2 {
status = "okay";
};
/* Apalis MMC1 */
&usdhc2 {
status = "okay";
};
/* Apalis SD1 */
&usdhc3 {
status = "okay";
};

124
arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.2.dtsi Normal file
View file

@ -0,0 +1,124 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024 Toradex
*/
#include "imx8-apalis-eval.dtsi"
/ {
reg_3v3_mmc: regulator-3v3-mmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_3v3_mmc>;
enable-active-high;
gpio = <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <100000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3.3V_MMC";
startup-delay-us = <10000>;
};
reg_3v3_sd: regulator-3v3-sd {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_3v3_sd>;
enable-active-high;
gpio = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <100000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3.3V_SD";
startup-delay-us = <10000>;
};
reg_can1: regulator-can1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_can1_power>;
enable-active-high;
gpio = <&lsio_gpio5 22 GPIO_ACTIVE_HIGH>;
regulator-name = "5V_SW_CAN1";
startup-delay-us = <10000>;
};
reg_can2: regulator-can2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_can2_power>;
enable-active-high;
gpio = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
regulator-name = "5V_SW_CAN2";
startup-delay-us = <10000>;
};
};
/* Apalis CAN1 */
&flexcan1 {
xceiver-supply = <&reg_can1>;
status = "okay";
};
/* Apalis CAN2 */
&flexcan2 {
xceiver-supply = <&reg_can2>;
status = "okay";
};
/* Apalis I2C1 */
&i2c2 {
status = "okay";
/* Power/Current Measurement Sensor */
hwmon@40 {
compatible = "ti,ina219";
reg = <0x40>;
shunt-resistor = <5000>;
};
temperature-sensor@4f {
compatible = "ti,tmp75c";
reg = <0x4f>;
};
eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
};
};
/* Apalis MMC1 */
&usdhc2 {
pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>;
pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>;
pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>;
pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>;
bus-width = <4>;
vmmc-supply = <&reg_3v3_mmc>;
status = "okay";
};
/* Apalis SD1 */
&usdhc3 {
vmmc-supply = <&reg_3v3_sd>;
status = "okay";
};
&iomuxc {
pinctrl_enable_3v3_mmc: enable3v3mmcgrp {
fsl,pins = <IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 0x00000021>; /* MXM3_148 */
};
pinctrl_enable_3v3_sd: enable3v3sdgrp {
fsl,pins = <IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x00000021>; /* MXM3_152 */
};
pinctrl_enable_can1_power: enablecan1powergrp {
fsl,pins = <IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021>; /* MXM3_158 */
};
pinctrl_enable_can2_power: enablecan2powergrp {
fsl,pins = <IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021>; /* MXM3_156 */
};
};

22
arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi
View file

@ -35,18 +35,6 @@
status = "okay";
};
/* Apalis CAN1 */
&flexcan1 {
status = "okay";
};
/* Apalis CAN2 */
&flexcan2 {
status = "okay";
};
/* TODO: GPU */
/* Apalis I2C1 */
&i2c2 {
status = "okay";
@ -132,13 +120,3 @@
};
/* TODO: Apalis USBH4 SuperSpeed */
/* Apalis MMC1 */
&usdhc2 {
status = "okay";
};
/* Apalis SD1 */
&usdhc3 {
status = "okay";
};

1
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
View file

@ -261,7 +261,6 @@
reset-assert-us = <2>;
reset-deassert-us = <2>;
reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
reset-names = "phy";
};
};
};

330
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
View file

@ -4,6 +4,7 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
@ -14,12 +15,174 @@ audio_ipg_clk: clock-audio-ipg {
clock-output-names = "audio_ipg_clk";
};
clk_ext_aud_mclk0: clock-ext-aud-mclk0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "ext_aud_mclk0";
};
clk_ext_aud_mclk1: clock-ext-aud-mclk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "ext_aud_mclk1";
};
clk_esai0_rx_clk: clock-esai0-rx {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "esai0_rx_clk";
};
clk_esai0_rx_hf_clk: clock-esai0-rx-hf {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "esai0_rx_hf_clk";
};
clk_esai0_tx_clk: clock-esai0-tx {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "esai0_tx_clk";
};
clk_esai0_tx_hf_clk: clock-esai0-tx-hf {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "esai0_tx_hf_clk";
};
clk_spdif0_rx: clock-spdif0-rx {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "spdif0_rx";
};
clk_sai0_rx_bclk: clock-sai0-rx-bclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "sai0_rx_bclk";
};
clk_sai0_tx_bclk: clock-sai0-tx-bclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "sai0_tx_bclk";
};
clk_sai1_rx_bclk: clock-sai1-rx-bclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "sai1_rx_bclk";
};
clk_sai1_tx_bclk: clock-sai1-tx-bclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "sai1_tx_bclk";
};
clk_sai2_rx_bclk: clock-sai2-rx-bclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "sai2_rx_bclk";
};
clk_sai3_rx_bclk: clock-sai3-rx-bclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "sai3_rx_bclk";
};
clk_sai4_rx_bclk: clock-sai4-rx-bclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "sai4_rx_bclk";
};
audio_subsys: bus@59000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x59000000 0x0 0x59000000 0x1000000>;
sai0: sai@59040000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59040000 0x10000>;
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai0_lpcg 1>,
<&clk_dummy>,
<&sai0_lpcg 0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
power-domains = <&pd IMX_SC_R_SAI_0>;
status = "disabled";
};
sai1: sai@59050000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59050000 0x10000>;
interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai1_lpcg 1>,
<&clk_dummy>,
<&sai1_lpcg 0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
power-domains = <&pd IMX_SC_R_SAI_1>;
status = "disabled";
};
sai2: sai@59060000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59060000 0x10000>;
interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai2_lpcg 1>,
<&clk_dummy>,
<&sai2_lpcg 0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dma-names = "rx";
dmas = <&edma0 16 0 1>;
power-domains = <&pd IMX_SC_R_SAI_2>;
status = "disabled";
};
sai3: sai@59070000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59070000 0x10000>;
interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai3_lpcg 1>,
<&clk_dummy>,
<&sai3_lpcg 0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dma-names = "rx";
dmas = <&edma0 17 0 1>;
power-domains = <&pd IMX_SC_R_SAI_3>;
status = "disabled";
};
edma0: dma-controller@591f0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x591f0000 0x190000>;
@ -76,6 +239,54 @@ audio_subsys: bus@59000000 {
<&pd IMX_SC_R_DMA_0_CH23>;
};
sai0_lpcg: clock-controller@59440000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59440000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>,
<&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "sai0_lpcg_mclk",
"sai0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SAI_0>;
};
sai1_lpcg: clock-controller@59450000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59450000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>,
<&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "sai1_lpcg_mclk",
"sai1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SAI_1>;
};
sai2_lpcg: clock-controller@59460000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59460000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>,
<&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "sai2_lpcg_mclk",
"sai2_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SAI_2>;
};
sai3_lpcg: clock-controller@59470000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59470000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>,
<&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "sai3_lpcg_mclk",
"sai3_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SAI_3>;
};
dsp_lpcg: clock-controller@59580000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59580000 0x10000>;
@ -151,4 +362,123 @@ audio_subsys: bus@59000000 {
<&pd IMX_SC_R_DMA_1_CH9>,
<&pd IMX_SC_R_DMA_1_CH10>;
};
aud_rec0_lpcg: clock-controller@59d00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59d00000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "aud_rec_clk0_lpcg_clk";
power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
};
aud_rec1_lpcg: clock-controller@59d10000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59d10000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "aud_rec_clk1_lpcg_clk";
power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
};
aud_pll_div0_lpcg: clock-controller@59d20000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59d20000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "aud_pll_div_clk0_lpcg_clk";
power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
};
aud_pll_div1_lpcg: clock-controller@59d30000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59d30000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "aud_pll_div_clk1_lpcg_clk";
power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
};
mclkout0_lpcg: clock-controller@59d50000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59d50000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "mclkout0_lpcg_clk";
power-domains = <&pd IMX_SC_R_MCLK_OUT_0>;
};
mclkout1_lpcg: clock-controller@59d60000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59d60000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "mclkout1_lpcg_clk";
power-domains = <&pd IMX_SC_R_MCLK_OUT_1>;
};
acm: acm@59e00000 {
compatible = "fsl,imx8qxp-acm";
reg = <0x59e00000 0x1d0000>;
#clock-cells = <1>;
power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_MCLK_OUT_0>,
<&pd IMX_SC_R_MCLK_OUT_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>,
<&pd IMX_SC_R_ASRC_0>,
<&pd IMX_SC_R_ASRC_1>,
<&pd IMX_SC_R_ESAI_0>,
<&pd IMX_SC_R_SAI_0>,
<&pd IMX_SC_R_SAI_1>,
<&pd IMX_SC_R_SAI_2>,
<&pd IMX_SC_R_SAI_3>,
<&pd IMX_SC_R_SAI_4>,
<&pd IMX_SC_R_SAI_5>,
<&pd IMX_SC_R_SPDIF_0>,
<&pd IMX_SC_R_MQS_0>;
clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
<&aud_rec1_lpcg IMX_LPCG_CLK_0>,
<&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
<&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
<&clk_ext_aud_mclk0>,
<&clk_ext_aud_mclk1>,
<&clk_esai0_rx_clk>,
<&clk_esai0_rx_hf_clk>,
<&clk_esai0_tx_clk>,
<&clk_esai0_tx_hf_clk>,
<&clk_spdif0_rx>,
<&clk_sai0_rx_bclk>,
<&clk_sai0_tx_bclk>,
<&clk_sai1_rx_bclk>,
<&clk_sai1_tx_bclk>,
<&clk_sai2_rx_bclk>,
<&clk_sai3_rx_bclk>,
<&clk_sai4_rx_bclk>;
clock-names = "aud_rec_clk0_lpcg_clk",
"aud_rec_clk1_lpcg_clk",
"aud_pll_div_clk0_lpcg_clk",
"aud_pll_div_clk1_lpcg_clk",
"ext_aud_mclk0",
"ext_aud_mclk1",
"esai0_rx_clk",
"esai0_rx_hf_clk",
"esai0_tx_clk",
"esai0_tx_hf_clk",
"spdif0_rx",
"sai0_rx_bclk",
"sai0_tx_bclk",
"sai1_rx_bclk",
"sai1_tx_bclk",
"sai2_rx_bclk",
"sai3_rx_bclk",
"sai4_rx_bclk";
};
};

63
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
View file

@ -5,6 +5,7 @@
*/
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/firmware/imx/rsrc.h>
dma_ipg_clk: clock-dma-ipg {
@ -93,8 +94,8 @@ dma_subsys: bus@5a000000 {
assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_0>;
dma-names = "tx","rx";
dmas = <&edma2 9 0 0>, <&edma2 8 0 1>;
dma-names = "rx", "tx";
dmas = <&edma2 8 0 FSL_EDMA_RX>, <&edma2 9 0 0>;
status = "disabled";
};
@ -107,8 +108,8 @@ dma_subsys: bus@5a000000 {
assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_1>;
dma-names = "tx","rx";
dmas = <&edma2 11 0 0>, <&edma2 10 0 1>;
dma-names = "rx", "tx";
dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 11 0 0>;
status = "disabled";
};
@ -121,8 +122,8 @@ dma_subsys: bus@5a000000 {
assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_2>;
dma-names = "tx","rx";
dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
dma-names = "rx", "tx";
dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>;
status = "disabled";
};
@ -135,8 +136,8 @@ dma_subsys: bus@5a000000 {
assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_3>;
dma-names = "tx","rx";
dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
dma-names = "rx", "tx";
dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>;
status = "disabled";
};
@ -192,29 +193,6 @@ dma_subsys: bus@5a000000 {
<&pd IMX_SC_R_DMA_2_CH15>;
};
edma3: dma-controller@5a9f0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x5a9f0000 0x90000>;
#dma-cells = <3>;
dma-channels = <8>;
interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
<&pd IMX_SC_R_DMA_3_CH1>,
<&pd IMX_SC_R_DMA_3_CH2>,
<&pd IMX_SC_R_DMA_3_CH3>,
<&pd IMX_SC_R_DMA_3_CH4>,
<&pd IMX_SC_R_DMA_3_CH5>,
<&pd IMX_SC_R_DMA_3_CH6>,
<&pd IMX_SC_R_DMA_3_CH7>;
};
spi0_lpcg: clock-controller@5a400000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a400000 0x10000>;
@ -460,6 +438,29 @@ dma_subsys: bus@5a000000 {
status = "disabled";
};
edma3: dma-controller@5a9f0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x5a9f0000 0x90000>;
#dma-cells = <3>;
dma-channels = <8>;
interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
<&pd IMX_SC_R_DMA_3_CH1>,
<&pd IMX_SC_R_DMA_3_CH2>,
<&pd IMX_SC_R_DMA_3_CH3>,
<&pd IMX_SC_R_DMA_3_CH4>,
<&pd IMX_SC_R_DMA_3_CH5>,
<&pd IMX_SC_R_DMA_3_CH6>,
<&pd IMX_SC_R_DMA_3_CH7>;
};
i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>;

27
arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi Normal file
View file

@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
gpu0_subsys: bus@53000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x53000000 0x0 0x53000000 0x1000000>;
gpu_3d0: gpu@53100000 {
compatible = "vivante,gc";
reg = <0x53100000 0x40000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
clock-names = "core", "shader";
assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
assigned-clock-rates = <700000000>, <850000000>;
power-domains = <&pd IMX_SC_R_GPU_0_PID0>;
};
};

101
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View file

@ -81,6 +81,24 @@
status = "disabled";
};
reg_can0_stby: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "can0-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can1_stby: regulator-5 {
compatible = "regulator-fixed";
regulator-name = "can1-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
@ -261,12 +279,81 @@
};
};
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
pca6416_3: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&lsio_gpio2>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
};
pca9548_2: i2c-mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
};
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can0_stby>;
status = "okay";
};
&flexcan3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan3>;
xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
&lsio_gpio4 {
status = "okay";
};
@ -436,6 +523,20 @@
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021
IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021
>;
};
pinctrl_flexcan3: flexcan3grp {
fsl,pins = <
IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021
IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0

77
arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
View file

@ -15,6 +15,63 @@
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
};
&edma0 {
reg = <0x591f0000 0x1a0000>;
#dma-cells = <3>;
dma-channels = <25>;
dma-channel-mask = <0x1c0cc0>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */
power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
<&pd IMX_SC_R_DMA_0_CH1>,
<&pd IMX_SC_R_DMA_0_CH2>,
<&pd IMX_SC_R_DMA_0_CH3>,
<&pd IMX_SC_R_DMA_0_CH4>,
<&pd IMX_SC_R_DMA_0_CH5>,
<&pd IMX_SC_R_DMA_0_CH6>,
<&pd IMX_SC_R_DMA_0_CH7>,
<&pd IMX_SC_R_DMA_0_CH8>,
<&pd IMX_SC_R_DMA_0_CH9>,
<&pd IMX_SC_R_DMA_0_CH10>,
<&pd IMX_SC_R_DMA_0_CH11>,
<&pd IMX_SC_R_DMA_0_CH12>,
<&pd IMX_SC_R_DMA_0_CH13>,
<&pd IMX_SC_R_DMA_0_CH14>,
<&pd IMX_SC_R_DMA_0_CH15>,
<&pd IMX_SC_R_DMA_0_CH16>,
<&pd IMX_SC_R_DMA_0_CH17>,
<&pd IMX_SC_R_DMA_0_CH18>,
<&pd IMX_SC_R_DMA_0_CH19>,
<&pd IMX_SC_R_DMA_0_CH20>,
<&pd IMX_SC_R_DMA_0_CH21>,
<&pd IMX_SC_R_DMA_0_CH22>,
<&pd IMX_SC_R_DMA_0_CH23>,
<&pd IMX_SC_R_DMA_0_CH24>;
};
&edma2 {
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
@ -45,24 +102,44 @@
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
};
&flexcan1 {
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
};
&flexcan2 {
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
};
&flexcan3 {
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c0 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "tx","rx";
dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL_EDMA_RX>;
};
&i2c1 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "tx","rx";
dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL_EDMA_RX>;
};
&i2c2 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "tx","rx";
dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL_EDMA_RX>;
};
&i2c3 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "tx","rx";
dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL_EDMA_RX>;
};
&lpuart0 {

1
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
View file

@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

16
arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp-mba8xx.dts Normal file
View file

@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
/*
* Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
#include "imx8dxp-tqma8xdp.dtsi"
#include "mba8xx.dtsi"
/ {
model = "TQ-Systems i.MX8DXP TQMa8XDP on MBa8Xx";
compatible = "tq,imx8dxp-tqma8xdp-mba8xx", "tq,imx8dxp-tqma8xdp", "fsl,imx8dxp";
};

24
arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdp.dtsi Normal file
View file

@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
/*
* Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
#include "imx8dxp.dtsi"
#include "tqma8xx.dtsi"
/ {
model = "TQ-Systems i.MX8DXP TQMa8XDP";
compatible = "tq,imx8dxp-tqma8xdp", "fsl,imx8dxp";
};
&pmic_thermal {
cooling-maps {
map0 {
cooling-device =
<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

24
arch/arm64/boot/dts/freescale/imx8dxp.dtsi Normal file
View file

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2019 NXP
*/
/dts-v1/;
#include "imx8qxp.dtsi"
/delete-node/ &A35_2;
/delete-node/ &A35_3;
&thermal_zones {
cpu0-thermal {
cooling-maps {
map0 {
cooling-device =
<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};

69
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View file

@ -151,6 +151,28 @@
clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
};
};
sound-micfil {
compatible = "fsl,imx-audio-card";
model = "micfil-audio";
pri-dai-link {
link-name = "micfil hifi";
format = "i2s";
cpu {
sound-dai = <&micfil>;
};
};
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif1>;
spdif-out;
spdif-in;
};
};
&A53_0 {
@ -434,6 +456,16 @@
status = "okay";
};
&micfil {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX8MM_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <196608000>;
status = "okay";
};
&mipi_csi {
status = "okay";
@ -509,6 +541,24 @@
status = "okay";
};
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif1>;
assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
<&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba",
"pll8k", "pll11k";
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
@ -636,6 +686,18 @@
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
@ -666,6 +728,13 @@
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159

294
arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts
View file

@ -25,23 +25,21 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led1 {
label = "led1";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led2 {
label = "led2";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
};
led3 {
label = "led3";
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
};
};
@ -52,24 +50,12 @@
reg_rst_eth2: regulator-rst-eth2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_eth2>;
gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-name = "rst-usb-eth2";
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_vbus>;
gpio = <&gpio3 25 GPIO_ACTIVE_LOW>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "usb1-vbus";
};
reg_vdd_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-always-on;
@ -80,9 +66,6 @@
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
can@0 {
@ -91,7 +74,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
clocks = <&osc_can>;
interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>;
/*
* Limit the SPI clock to 15 MHz to prevent issues
* with corrupted data due to chip errata.
@ -103,9 +86,6 @@
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
status = "okay";
eeram@0 {
@ -117,8 +97,8 @@
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-connection-type = "rgmii-rxid";
pinctrl-0 = <&pinctrl_enet_rgmii>;
phy-connection-type = "rgmii-id";
phy-handle = <&ethphy>;
status = "okay";
@ -127,55 +107,101 @@
#size-cells = <0>;
ethphy: ethernet-phy@0 {
compatible = "ethernet-phy-id4f51.e91b";
reg = <0>;
reset-assert-us = <1>;
reset-deassert-us = <15000>;
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
};
};
};
/*
* Rename SoM signals according to board usage:
* GPIO_B_0 -> DIO1_OUT
* GPIO_B_1 -> DIO2_OUT
*/
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>;
gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out",
"dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1",
"", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4",
"GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "DIO1_OUT",
"DIO2_OUT", "USB_A_OC#", "CAM_MCK", "USB_B_OC#",
"ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3",
"ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1",
"ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)",
"ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)",
"ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0",
"ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2",
"ETH_A_(R)(G)MII_RXD3";
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio5>;
gpio-line-names = "", "", "dio4-in", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
/*
* Rename SoM signals according to board usage:
* GPIO_B_2 -> DIO3_OUT
* GPIO_B_3 -> DIO4_OUT
*/
&gpio3 {
gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5",
"SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1",
"GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1",
"SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4",
"CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "DIO3_OUT",
"USB_B_EN", "DIO4_OUT", "PCIe_CLKREQ#", "PCIe_A_PERST#",
"PCIe_WAKE#", "USB_A_EN";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
/*
* Rename SoM signals according to board usage:
* GPIO_B_4 -> DIO1_IN
* GPIO_B_5 -> DIO2_IN
* GPIO_B_6 -> DIO3_IN
* GPIO_B_7 -> DIO4_IN
*/
&gpio4 {
gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN",
"DIO1_IN", "BOOT_SEL0#", "BOOT_SEL1#", "",
"", "", "I2S_LRCLK", "I2S_BITCLK",
"I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "DIO2_IN", "DIO3_IN",
"DIO4_IN", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6",
"I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS",
"UART_A_RTS", "", "", "",
"PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX";
};
&i2c3 {
status = "okay";
usb-hub@2c {
compatible = "microchip,usb2514b";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_hub>;
reg = <0x2c>;
non-removable-ports = <0>, <3>;
reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
};
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&reg_usb2_vbus {
status = "disabled";
};
&reg_usdhc2_vcc {
status = "disabled";
};
&reg_usdhc3_vcc {
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
uart-has-rtscts;
status = "okay";
@ -183,8 +209,6 @@
&usbotg1 {
dr_mode = "otg";
disable-over-current;
vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
@ -195,14 +219,17 @@
#size-cells = <0>;
status = "okay";
/* VBUS is controlled by the hub */
/delete-property/ vbus-supply;
usb1@1 {
compatible = "usb424,9514";
compatible = "usb424,2514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
usbnet: ethernet@1 {
compatible = "usb424,ec00";
compatible = "usbb95,772b";
reg = <1>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
@ -210,167 +237,20 @@
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_nvcc_sd>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
&iomuxc {
pinctrl_can: cangrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */
>;
};
pinctrl_ecspi2: ecspi2grp {
pinctrl_usb_hub: usbhubgrp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
>;
};
pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
>;
};
pinctrl_gpio5: gpio5grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
>;
};
pinctrl_reg_usb1_vbus: regusb1vbusgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
>;
};
pinctrl_usb_eth2: usbeth2grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */
>;
};
};

38
arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
View file

@ -279,8 +279,8 @@
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083
>;
};
@ -292,19 +292,19 @@
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0
>;
};
@ -316,40 +316,40 @@
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
};

567
arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi
View file

@ -3,6 +3,7 @@
* Copyright (C) 2022 Kontron Electronics GmbH
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx8mm.dtsi"
@ -28,6 +29,73 @@
chosen {
stdout-path = &uart3;
};
reg_vdd_carrier: regulator-vdd-carrier {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_vdd_carrier>;
gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
regulator-name = "VDD_CARRIER";
regulator-state-standby {
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
regulator-state-disk {
regulator-off-in-suspend;
};
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_vbus>;
enable-active-high;
gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "VBUS_USB1";
};
reg_usb2_vbus: regulator-usb2-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb2_vbus>;
enable-active-high;
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "VBUS_USB2";
};
reg_usdhc2_vcc: regulator-usdhc2-vcc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>;
enable-active-high;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VCC_SDIO_A";
};
reg_usdhc3_vcc: regulator-usdhc3-vcc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc3_vcc>;
enable-active-high;
gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VCC_SDIO_B";
};
};
&A53_0 {
@ -96,6 +164,79 @@
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_ecspi2_gpio>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>;
gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1",
"", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4",
"GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "GPIO_B_0",
"GPIO_B_1", "USB_A_OC#", "CAM_MCK", "USB_B_OC#",
"ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3",
"ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1",
"ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)",
"ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)",
"ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0",
"ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2",
"ETH_A_(R)(G)MII_RXD3";
};
&gpio2 {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "",
"SDIO_A_CD#", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",
"SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN",
"SDIO_A_WP";
};
&gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio3>;
gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5",
"SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1",
"GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1",
"SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4",
"CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_2",
"USB_B_EN", "GPIO_B_3", "PCIe_CLKREQ#", "PCIe_A_PERST#",
"PCIe_WAKE#", "USB_A_EN";
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio4>;
gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN",
"GPIO_B_4", "BOOT_SEL0#", "BOOT_SEL1#", "",
"", "", "I2S_LRCLK", "I2S_BITCLK",
"I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "GPIO_B_5", "GPIO_B_6",
"GPIO_B_7", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6",
"I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS",
"UART_A_RTS", "", "", "",
"PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX";
};
&gpio5 {
gpio-line-names = "UART_B_TX", "SDIO_B_PWR_EN", "SDIO_B_WP", "PWM_2",
"PWM_1", "PWM_0", "", "",
"", "", "SPI_A_SCK", "SPI_A_SDO_(IO1)",
"SPI_A_SCK", "SPI_A_CS0#", "", "",
"I2C_A_SCL", "I2C_A_SDA", "I2C_B_SCL", "I2C_B_SDA",
"PCIe_SMCLK", "PCIe_SMDAT", "SPI_B_SCK", "SPI_B_SDO",
"SPI_B_SDI", "SPI_B_CS0#", "UART_CON_RX", "UART_CON_TX",
"UART_C_RX", "UART_C_TX";
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -205,22 +346,86 @@
};
};
eeprom: eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
address-width = <16>;
pagesize = <32>;
size = <8192>;
};
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>;
trickle-diode-disable;
interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
};
&uart3 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
vbus-supply = <&reg_usb1_vbus>;
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
vbus-supply = <&reg_usb2_vbus>;
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
@ -233,6 +438,26 @@
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vcc>;
vqmmc-supply = <&reg_nvcc_sd>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
vmmc-supply = <&reg_usdhc3_vcc>;
vqmmc-supply = <&reg_nvcc_sd>;
cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
@ -241,6 +466,12 @@
};
&iomuxc {
pinctrl_csi_mck: csimckgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 /* CAM_MCK */
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
@ -250,10 +481,140 @@
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 /* SPI_A_SDI_(IO0) */
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 /* SPI_A_SDO_(IO1) */
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 /* SPI_A_SCK */
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* SPI_A_CS0# */
>;
};
pinctrl_ecspi2_gpio: ecspi2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* SPI_A_/WP_(IO2) */
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* SPI_A_/HOLD_(IO3) */
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 /* SPI_B_SDI */
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 /* SPI_B_SDO */
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 /* SPI_B_SCK */
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* SPI_B_CS0# */
>;
};
pinctrl_enet_rgmii: enetrgmiigrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */
>;
};
pinctrl_enet_rmii: enetrmiigrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */
MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f /* ETH_A_(S)(R)(G)MII_TXD2 */
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 /* ETH_A_(S)(R)(G)MII_TXD1 */
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 /* ETH_A_(S)(R)(G)MII_TXD0 */
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 /* ETH_A_(S)(R)(G)MII_RXD1 */
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 /* ETH_A_(S)(R)(G)MII_RXD0 */
MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 /* ETH_A_(R)(G)MII_RX_CLK */
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 /* ETH_A_(R)(G)MII_RX_DV(_ER) */
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 /* ETH_A_(R)(G)MII_TX_EN(_ER) */
>;
};
pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* GPIO_A_0 */
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* GPIO_A_1 */
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* GPIO_A_2 */
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* GPIO_A_3 */
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* GPIO_A_4 */
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 /* GPIO_A_5 */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* GPIO_A_6 */
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* GPIO_A_7 */
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* GPIO_B_0 */
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* GPIO_B_1 */
>;
};
pinctrl_gpio3: gpio3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* GPIO_C_5 */
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* GPIO_C_4 */
MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* GPIO_C_0 */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* GPIO_C_1 */
MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* GPIO_C_2 */
MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* GPIO_C_3 */
MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* GPIO_B_2 */
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* GPIO_B_3 */
>;
};
pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* GPIO_C_7 */
MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* GPIO_B_4 */
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* BOOT_SEL0# */
MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* BOOT_SEL1# */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* GPIO_B_5 */
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* GPIO_B_6 */
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* GPIO_B_7 */
MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* GPIO_C_6 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 /* I2C_B_SCL */
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 /* I2C_B_SDA */
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 /* PCIe_SMCLK and I2C_CAM_SCL/CSI_TX_P */
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 /* PCIe_SMDAT and I2C_CAM_SDA/CSI_TX_N */
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* PCIe_CLKREQ# */
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* PCIe_A_PERST# */
MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* PCIe_WAKE# */
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* PCIe_SM_ALERT */
>;
};
@ -263,16 +624,113 @@
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19 /* PWM_0 */
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 /* PWM_1 */
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x19 /* PWM_2 */
>;
};
pinctrl_reg_usb1_vbus: regusb1vbusgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* USB_A_EN */
>;
};
pinctrl_reg_usb2_vbus: regusb2vbusgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* USB_B_EN */
>;
};
pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19 /* SDIO_A_PWR_EN */
>;
};
pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */
>;
};
pinctrl_reg_vdd_carrier: regvddcarriergrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* CARRIER_PWR_EN */
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 /* I2S_A_DATA_IN */
MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 /* I2S_A_DATA_OUT */
MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 /* I2S_B_DATA_IN */
MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 /* I2S_B_DATA_OUT */
MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 /* I2S_MCLK */
MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 /* I2S_LRCLK */
MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 /* I2S_BITCLK */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 /* UART_A_RX */
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 /* UART_A_TX */
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 /* UART_A_CTS */
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 /* UART_A_RTS */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 /* UART_B_RX */
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 /* UART_B_TX */
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 /* UART_B_CTS */
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 /* UART_B_RTS */
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 /* UART_CON_RX */
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 /* UART_CON_TX */
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x0 /* UART_C_RX */
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0 /* UART_C_TX */
>;
};
pinctrl_usb1: usb1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 /* USB_A_OC# */
>;
};
pinctrl_usb2: usb2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x19 /* USB_B_OC# */
>;
};
@ -327,6 +785,103 @@
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 /* SDIO_A_CLK */
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SDIO_A_CMD */
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 /* SDIO_A_CLK */
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 /* SDIO_A_CMD */
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 /* SDIO_A_CLK */
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 /* SDIO_A_CMD */
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 /* SDIO_A_CD# */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x90 /* SDIO_B_CLK */
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x90 /* SDIO_B_CMD */
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x90 /* SDIO_B_D0 */
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x90 /* SDIO_B_D1 */
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x90 /* SDIO_B_D2 */
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x90 /* SDIO_B_D3 */
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x90 /* SDIO_B_D4 */
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x90 /* SDIO_B_D5 */
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x90 /* SDIO_B_D6 */
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x90 /* SDIO_B_D7 */
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x94 /* SDIO_B_CLK */
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x94 /* SDIO_B_CMD */
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x94 /* SDIO_B_D0 */
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x94 /* SDIO_B_D1 */
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x94 /* SDIO_B_D2 */
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x94 /* SDIO_B_D3 */
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x94 /* SDIO_B_D4 */
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x94 /* SDIO_B_D5 */
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x94 /* SDIO_B_D6 */
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x94 /* SDIO_B_D7 */
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x96 /* SDIO_B_CLK */
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x96 /* SDIO_B_CMD */
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x96 /* SDIO_B_D0 */
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x96 /* SDIO_B_D1 */
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x96 /* SDIO_B_D2 */
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x96 /* SDIO_B_D3 */
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x96 /* SDIO_B_D4 */
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x96 /* SDIO_B_D5 */
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x96 /* SDIO_B_D6 */
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x96 /* SDIO_B_D7 */
>;
};
pinctrl_usdhc3_gpio: usdhc3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* SDIO_B_CD# */
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6

4
arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi
View file

@ -237,8 +237,8 @@
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083
>;
};

14
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
View file

@ -5,6 +5,8 @@
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm-tqma8mqml.dtsi"
#include "mba8mx.dtsi"
@ -74,19 +76,23 @@
};
&pcie_phy {
clocks = <&pcie0_refclk>;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcieclk 2>;
clock-names = "ref";
status = "okay";
};
/* PCIe slot on X36 */
&pcie0 {
reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 3>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};

40
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
View file

@ -47,25 +47,20 @@
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_en>;
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&gpio1 {
@ -144,9 +139,10 @@
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
dr_mode = "otg";
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
@ -204,20 +200,13 @@
>;
};
pinctrl_reg_usb1_en: regusb1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};
@ -234,4 +223,11 @@
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
>;
};
};

14
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
View file

@ -285,7 +285,8 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
<&gpio4 24 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
@ -294,6 +295,12 @@
spi-max-frequency = <40000000>;
status = "okay";
};
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&fec1 {
@ -319,7 +326,7 @@
&gpio4 {
gpio-line-names = "", "", "", "",
"", "", "uart3_rs232#", "uart3_rs422#",
"dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#",
"uart3_rs485#", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
@ -842,6 +849,8 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIG1_CTL */
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000041 /* DIG2_CTL */
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
@ -987,6 +996,7 @@
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140
>;
};

2
arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts
View file

@ -99,8 +99,6 @@
};
&lcdif {
assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>;
assigned-clock-rates = <594000000>;
status = "okay";
};

36
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
View file

@ -110,6 +110,20 @@
spdif-out;
spdif-in;
};
sound-micfil {
compatible = "fsl,imx-audio-card";
model = "micfil-audio";
pri-dai-link {
link-name = "micfil hifi";
format = "i2s";
cpu {
sound-dai = <&micfil>;
};
};
};
};
&easrc {
@ -285,6 +299,16 @@
status = "okay";
};
&micfil {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX8MN_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <196608000>;
status = "okay";
};
&mipi_csi {
status = "okay";
@ -522,6 +546,18 @@
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6
MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6
MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6
MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141

2
arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts
View file

@ -10,7 +10,7 @@
/ {
model = "RVE gateway";
compatible = "rve,rve-gateway", "variscite,var-som-mx8mn", "fsl,imx8mn";
compatible = "rve,gateway", "variscite,var-som-mx8mn", "fsl,imx8mn";
crystal_duart_24m: crystal-duart-24m {
compatible = "fixed-clock";

64
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso Normal file
View file

@ -0,0 +1,64 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "imx8mn-pinfunc.h"
&{/} {
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
type = "micro";
label = "X19";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_connector>;
id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
port {
usb_dr_connector: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
&rst_usb_hub_hog {
output-low;
};
&sel_usb_hub_hog {
output-low;
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
power-active-high;
/delete-property/ disable-over-current;
over-current-active-low;
usb-role-switch;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&usb_dr_connector>;
};
};
};
&iomuxc {
pinctrl_usb1_connector: usb1-connectorgrp {
fsl,pins = <MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c0>;
};
};

5
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts
View file

@ -41,7 +41,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0hub_sel>;
sel-usb-hub-hog {
sel_usb_hub_hog: sel-usb-hub-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-high;
@ -198,8 +198,7 @@
pinctrl_usbotg: usbotggrp {
fsl,pins = <MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x84>,
<MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x84>,
<MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x1C4>;
<MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x84>;
};
pinctrl_usdhc2: usdhc2grp {

2
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View file

@ -1168,7 +1168,7 @@
<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rates = <266000000>,
<24000000>,
<594000000>,
<24000000>,
<500000000>,
<200000000>;
#power-domain-cells = <1>;

71
arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi
View file

@ -50,6 +50,8 @@
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
snps,force_thresh_dma_mode;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
status = "okay";
mdio {
@ -66,6 +68,71 @@
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
snps,map-to-dma-channel = <0>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
snps,map-to-dma-channel = <1>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
snps,map-to-dma-channel = <2>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
snps,map-to-dma-channel = <3>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
snps,map-to-dma-channel = <4>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
};
};
};
&flexspi {
@ -206,6 +273,10 @@
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8997-bt";
};
};
&usdhc1 {

82
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
View file

@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/net/qca-ar803x.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp.dtsi"
/ {
@ -45,6 +46,19 @@
clock-frequency = <25000000>;
};
clk_pwm4: clock-pwm4 {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
clock-output-names = "codec-pwm4";
/*
* 1 / 83 ns ~= 12 MHz , but since the PWM input clock is 24 MHz
* and the calculated PWM period is 1 and duty cycle is 50%, the
* result is exactly 12 MHz, which is fine for SGTL5000 MCLK.
*/
pwms = <&pwm4 0 83 0>;
};
panel: panel {
/* Compatible string is filled in by panel board DT Overlay. */
backlight = <&backlight>;
@ -82,6 +96,24 @@
vin-supply = <&buck4>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "SGTL5000-Card";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,widgets = "Headphone", "Headphone Jack";
simple-audio-card,routing = "Headphone Jack", "HP_OUT";
cpu_dai: simple-audio-card,cpu {
sound-dai = <&sai3>;
};
codec_dai: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
};
};
watchdog { /* TPS3813 */
compatible = "linux,wdt-gpio";
pinctrl-names = "default";
@ -121,7 +153,7 @@
flash@0 { /* W25Q128JVEI */
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>; /* Up to 133 MHz */
spi-max-frequency = <40000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
@ -288,6 +320,15 @@
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clk_pwm4>;
VDDA-supply = <&buck4>;
VDDIO-supply = <&buck4>;
};
usb-hub@2c {
compatible = "microchip,usb2514bi";
reg = <0x2c>;
@ -429,6 +470,21 @@
status = "okay";
};
&pcie_phy {
clocks = <&pcieclk 0>;
clock-names = "ref";
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
fsl,max-link-speed = <3>;
reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel_pwm>;
@ -436,6 +492,23 @@
status = "disabled";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&sai3 {
#clock-cells = <0>;
#sound-dai-cells = <0>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
status = "okay";
};
/* SD slot */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
@ -785,6 +858,12 @@
>;
};
pinctrl_pwm4: pwm4-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0xd6
>;
};
pinctrl_rtc: rtc-grp {
fsl,pins = <
/* RTC_IRQ# */
@ -816,7 +895,6 @@
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
>;
};

33
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View file

@ -23,7 +23,7 @@
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&adv7533_out>;
remote-endpoint = <&adv7535_out>;
};
};
};
@ -107,6 +107,13 @@
enable-active-high;
};
reg_vext_3v3: regulator-vext-3v3 {
compatible = "regulator-fixed";
regulator-name = "VEXT_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8960-audio";
@ -364,7 +371,7 @@
regulator-always-on;
};
BUCK5 {
reg_buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
@ -415,14 +422,16 @@
hdmi@3d {
compatible = "adi,adv7535";
reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
reg-names = "main", "cec", "edid", "packet";
reg = <0x3d>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
adi,dsi-lanes = <4>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
avdd-supply = <&reg_buck5>;
dvdd-supply = <&reg_buck5>;
pvdd-supply = <&reg_buck5>;
a2vdd-supply = <&reg_buck5>;
v3p3-supply = <&reg_vext_3v3>;
v1p2-supply = <&reg_buck5>;
ports {
#address-cells = <1>;
@ -431,7 +440,7 @@
port@0 {
reg = <0>;
adv7533_in: endpoint {
adv7535_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
@ -439,7 +448,7 @@
port@1 {
reg = <1>;
adv7533_out: endpoint {
adv7535_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
@ -524,7 +533,7 @@
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&adv7533_in>;
remote-endpoint = <&adv7535_in>;
data-lanes = <1 2 3 4>;
};
};

107
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
View file

@ -19,6 +19,30 @@
stdout-path = &uart1;
};
backlight_lvds: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds1>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <11>;
enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
num-interpolated-steps = <2>;
power-supply = <&reg_lvds1_reg_en>;
pwms = <&pwm3 0 50000 0>;
};
panel1_lvds: panel-lvds {
compatible = "edt,etml1010g3dra";
backlight = <&backlight_lvds>;
power-supply = <&reg_vcc_3v3_sw>;
port {
panel1_in: endpoint {
remote-endpoint = <&ldb_lvds_ch1>;
};
};
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -39,6 +63,15 @@
regulator-name = "can2-stby";
};
reg_lvds1_reg_en: regulator-lvds1 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
regulator-max-microvolt = <1200000>;
regulator-min-microvolt = <1200000>;
regulator-name = "lvds1_reg_en";
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -61,6 +94,13 @@
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
reg_vcc_3v3_sw: regulator-vcc-3v3-sw {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3_SW";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&eqos {
@ -135,10 +175,41 @@
};
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
status = "okay";
ports {
port@2 {
ldb_lvds_ch1: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
};
&snvs_pwrkey {
status = "okay";
};
&pwm3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
};
&rv3028 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio4>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
trickle-resistor-ohms = <3000>;
};
/* debug console */
&uart1 {
pinctrl-names = "default";
@ -239,12 +310,12 @@
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
>;
};
@ -289,16 +360,34 @@
>;
};
pinctrl_lvds1: lvds1grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
>;
};
@ -319,7 +408,7 @@
pinctrl_usdhc2_pins: usdhc2-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40
>;
};

1
arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
View file

@ -175,7 +175,6 @@
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
trickle-resistor-ohms = <3000>;
};
};

10
arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
View file

@ -63,8 +63,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&gpio4 {
@ -228,6 +235,7 @@
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};

3
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
View file

@ -552,7 +552,7 @@
regulator-name = "On-module +V3.3_ADC (LDO4)";
};
LDO5 {
reg_vdd_sdio: LDO5 {
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
@ -885,6 +885,7 @@
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&reg_vdd_sdio>;
};
/* On-module eMMC */

12
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View file

@ -1636,8 +1636,10 @@
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <500000000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
status = "disabled";
@ -1670,8 +1672,10 @@
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <266000000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
status = "disabled";

24
arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
View file

@ -28,18 +28,6 @@
id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie1_refclk: pcie1-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_otg_vbus: regulator-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -103,23 +91,24 @@
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
};
/* PCIe slot on X36 */
&pcie0 {
reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&pcie0_refclk>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcieclk 3>,
<&pcieclk 2>,
<&clk IMX8MQ_CLK_PCIE1_AUX>;
status = "okay";
};
/*
* miniPCIe, also usable for cards with USB. Therefore configure the reset as
* miniPCIe on X28, also usable for cards with USB. Therefore configure the reset as
* static gpio hog.
*/
&pcie1 {
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&pcie1_refclk>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcieclk 1>,
<&pcieclk 0>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
status = "okay";
};
@ -171,6 +160,7 @@
};
&usb3_phy1 {
vbus-supply = <&reg_hub_vbus>;
status = "okay";
};

16
arch/arm64/boot/dts/freescale/imx8qm-apalis-eval-v1.2.dts Normal file
View file

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024 Toradex
*/
/dts-v1/;
#include "imx8qm-apalis.dtsi"
#include "imx8-apalis-eval-v1.2.dtsi"
/ {
model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board V1.2";
compatible = "toradex,apalis-imx8-eval-v1.2",
"toradex,apalis-imx8",
"fsl,imx8qm";
};

2
arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include "imx8qm-apalis.dtsi"
#include "imx8-apalis-eval.dtsi"
#include "imx8-apalis-eval-v1.1.dtsi"
/ {
model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board";

26
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts Normal file
View file

@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024 Toradex
*/
/dts-v1/;
#include "imx8qm-apalis-v1.1.dtsi"
#include "imx8-apalis-eval-v1.2.dtsi"
/ {
model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board V1.2";
compatible = "toradex,apalis-imx8-v1.1-eval-v1.2",
"toradex,apalis-imx8-v1.1",
"fsl,imx8qm";
};
/* Apalis MMC1 */
&usdhc2 {
/delete-property/ no-1-8-v;
};
/* Apalis SD1 */
&usdhc3 {
/delete-property/ no-1-8-v;
};

2
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include "imx8qm-apalis-v1.1.dtsi"
#include "imx8-apalis-eval.dtsi"
#include "imx8-apalis-eval-v1.1.dtsi"
/ {
model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board";

26
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View file

@ -41,6 +41,18 @@
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
@ -104,6 +116,20 @@
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c
>;
};
pinctrl_i2c1_gpio: i2c1gpio-grp {
fsl,pins = <
IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c
IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020

5
arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
View file

@ -6,20 +6,25 @@
&fec1 {
compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
iommus = <&smmu 0x12 0x7f80>;
};
&fec2 {
compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
iommus = <&smmu 0x12 0x7f80>;
};
&usdhc1 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
iommus = <&smmu 0x11 0x7f80>;
};
&usdhc2 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
iommus = <&smmu 0x11 0x7f80>;
};
&usdhc3 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
iommus = <&smmu 0x11 0x7f80>;
};

55
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
View file

@ -17,6 +17,32 @@
power-domains = <&pd IMX_SC_R_UART_4>;
};
i2c4: i2c@5a840000 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a840000 0x4000>;
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&i2c4_lpcg 0>,
<&i2c4_lpcg 1>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_4>;
status = "disabled";
};
i2c4_lpcg: clock-controller@5ac40000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac40000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c4_lpcg_clk",
"i2c4_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_4>;
};
can1_lpcg: clock-controller@5ace0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ace0000 0x10000>;
@ -96,15 +122,30 @@
status = "okay";
};
/* It is eDMA1 in 8QM RM, but 8QXP it is eDMA3 */
&edma3 {
reg = <0x5a9f0000 0x210000>;
dma-channels = <10>;
interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
<&pd IMX_SC_R_DMA_1_CH1>,
<&pd IMX_SC_R_DMA_1_CH2>,
<&pd IMX_SC_R_DMA_1_CH3>,
<&pd IMX_SC_R_DMA_1_CH4>,
<&pd IMX_SC_R_DMA_1_CH5>,
<&pd IMX_SC_R_DMA_1_CH6>,
<&pd IMX_SC_R_DMA_1_CH7>;
<&pd IMX_SC_R_DMA_1_CH1>,
<&pd IMX_SC_R_DMA_1_CH2>,
<&pd IMX_SC_R_DMA_1_CH3>,
<&pd IMX_SC_R_DMA_1_CH4>,
<&pd IMX_SC_R_DMA_1_CH5>,
<&pd IMX_SC_R_DMA_1_CH6>,
<&pd IMX_SC_R_DMA_1_CH7>,
<&pd IMX_SC_R_DMA_1_CH8>,
<&pd IMX_SC_R_DMA_1_CH9>;
};
&flexcan1 {

41
arch/arm64/boot/dts/freescale/imx8qm.dtsi
View file

@ -265,6 +265,47 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
};
smmu: iommu@51400000 {
compatible = "arm,mmu-500";
interrupt-parent = <&gic>;
reg = <0 0x51400000 0 0x40000>;
#global-interrupts = <1>;
#iommu-cells = <2>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
system-controller {
compatible = "fsl,imx-scu";
mbox-names = "tx0",

16
arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp-mba8xx.dts Normal file
View file

@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
/*
* Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
#include "imx8qxp-tqma8xqp.dtsi"
#include "mba8xx.dtsi"
/ {
model = "TQ-Systems i.MX8QXP TQMa8XQP on MBa8Xx";
compatible = "tq,imx8qxp-tqma8xqp-mba8xx", "tq,imx8qxp-tqma8xqp", "fsl,imx8qxp";
};

14
arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqp.dtsi Normal file
View file

@ -0,0 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
/*
* Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
#include "imx8qxp.dtsi"
#include "tqma8xx.dtsi"
/ {
model = "TQ-Systems i.MX8QXP TQMa8XQP";
compatible = "tq,imx8qxp-tqma8xqp", "fsl,imx8qxp";
};

8
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View file

@ -260,6 +260,13 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
};
clk_dummy: clock-dummy {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "clk_dummy";
};
xtal32k: clock-xtal32k {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -310,6 +317,7 @@
/* sorted in register address */
#include "imx8-ss-img.dtsi"
#include "imx8-ss-vpu.dtsi"
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"

2
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
View file

@ -37,7 +37,7 @@
no-map;
};
rsc_table: rsc-table@1fff8000{
rsc_table: rsc-table@1fff8000 {
reg = <0 0x1fff8000 0 0x1000>;
no-map;
};

117
arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts Normal file
View file

@ -0,0 +1,117 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
*
* Product homepage:
* phyBOARD-Segin carrier board is reused for the i.MX93 design.
* https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
*/
/dts-v1/;
#include "imx93-phycore-som.dtsi"
/{
model = "PHYTEC phyBOARD-Segin-i.MX93";
compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som",
"fsl,imx93";
chosen {
stdout-path = &lpuart1;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VCC_SD";
};
};
/* Console */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* eMMC */
&usdhc1 {
no-1-8-v;
};
/* SD-Card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
bus-width = <4>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
no-mmc;
no-sdio;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x30e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
>;
};
pinctrl_usdhc2_cd: usdhc2cdgrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
};

126
arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi Normal file
View file

@ -0,0 +1,126 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
*
* Product homepage:
* https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
*/
#include <dt-bindings/leds/common.h>
#include "imx93.dtsi"
/{
model = "PHYTEC phyCORE-i.MX93";
compatible = "phytec,imx93-phycore-som", "fsl,imx93";
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux,cma {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0 0x80000000 0 0x40000000>;
size = <0 0x10000000>;
linux,cma-default;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
/* Ethernet */
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
fsl,magic-packet;
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
<&clk IMX93_CLK_ENET_REF>,
<&clk IMX93_CLK_ENET_REF_PHY>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <100000000>, <50000000>, <50000000>;
status = "okay";
mdio: mdio {
clock-frequency = <5000000>;
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
};
/* Watchdog */
&wdog3 {
status = "okay";
};
&iomuxc {
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e
MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e
MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};
};

4
arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
View file

@ -122,10 +122,8 @@
/* protectable identification memory (part of M24C64-D @57) */
eeprom@5f {
compatible = "st,24c64", "atmel,24c64";
compatible = "atmel,24c64d-wl";
reg = <0x5f>;
size = <32>;
pagesize = <32>;
vcc-supply = <&reg_v3v3>;
};

351
arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts Normal file
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@ -0,0 +1,351 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
* Copyright 2023 Variscite Ltd.
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "imx93-var-som.dtsi"
/{
model = "Variscite VAR-SOM-MX93 on Symphony evaluation board";
compatible = "variscite,var-som-mx93-symphony",
"variscite,var-som-mx93", "fsl,imx93";
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
};
chosen {
stdout-path = &lpuart1;
};
/*
* Needed only for Symphony <= v1.5
*/
reg_fec_phy: regulator-fec-phy {
compatible = "regulator-fixed";
regulator-name = "fec-phy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <20000>;
gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ethosu_mem: ethosu-region@88000000 {
compatible = "shared-dma-pool";
reusable;
reg = <0x0 0x88000000 0x0 0x8000000>;
};
vdev0vring0: vdev0vring0@87ee0000 {
reg = <0 0x87ee0000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@87ee8000 {
reg = <0 0x87ee8000 0 0x8000>;
no-map;
};
vdev1vring0: vdev1vring0@87ef0000 {
reg = <0 0x87ef0000 0 0x8000>;
no-map;
};
vdev1vring1: vdev1vring1@87ef8000 {
reg = <0 0x87ef8000 0 0x8000>;
no-map;
};
rsc_table: rsc-table@2021f000 {
reg = <0 0x2021f000 0 0x1000>;
no-map;
};
vdevbuffer: vdevbuffer@87f00000 {
compatible = "shared-dma-pool";
reg = <0 0x87f00000 0 0x100000>;
no-map;
};
ele_reserved: ele-reserved@87de0000 {
compatible = "shared-dma-pool";
reg = <0 0x87de0000 0 0x100000>;
no-map;
};
};
gpio-keys {
compatible = "gpio-keys";
key-back {
label = "Back";
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
key-home {
label = "Home";
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
key-menu {
label = "Menu";
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
/* Use external instead of internal RTC*/
&bbnsm_rtc {
status = "disabled";
};
&eqos {
mdio {
ethphy1: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <5>;
qca,disable-smarteee;
eee-broken-1000t;
reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
vddio-supply = <&vddio1>;
vddio1: vddio-regulator {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
phy-supply = <&reg_fec_phy>;
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
status = "okay";
/* DS1337 RTC module */
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
&lpi2c5 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c5>;
pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
pinctrl-2 = <&pinctrl_lpi2c5_gpio>;
scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
status = "okay";
pca9534: gpio@20 {
compatible = "nxp,pca9534";
reg = <0x20>;
gpio-controller;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9534>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
#gpio-cells = <2>;
wakeup-source;
};
};
/* Console */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* J18.7, J18.9 */
&lpuart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
status = "okay";
};
/* SD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
no-sdio;
no-mmc;
};
/* Watchdog */
&wdog3 {
status = "okay";
};
&iomuxc {
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX93_PAD_PDM_CLK__CAN1_TX 0x139e
MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c1_gpio: lpi2c1gpiogrp {
fsl,pins = <
MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e
MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
>;
};
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = <
MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
>;
};
pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
fsl,pins = <
MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e
MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e
>;
};
pinctrl_pca9534: pca9534grp {
fsl,pins = <
MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e
MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
};

110
arch/arm64/boot/dts/freescale/imx93-var-som.dtsi Normal file
View file

@ -0,0 +1,110 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 NXP
* Copyright 2023 Variscite Ltd.
*/
/dts-v1/;
#include "imx93.dtsi"
/{
model = "Variscite VAR-SOM-MX93 module";
compatible = "variscite,var-som-mx93", "fsl,imx93";
mmc_pwrseq: mmc-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
reg_eqos_phy: regulator-eqos-phy {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_eqos_phy>;
regulator-name = "eth_phy_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100000>;
regulator-always-on;
};
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <1000000>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
eee-broken-1000t;
};
};
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
>;
};
pinctrl_reg_eqos_phy: regeqosgrp {
fsl,pins = <
MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
};

4
arch/arm64/boot/dts/freescale/imx93.dtsi
View file

@ -294,7 +294,7 @@
status = "disabled";
};
i3c1: i3c-master@44330000 {
i3c1: i3c@44330000 {
compatible = "silvaco,i3c-master-v1";
reg = <0x44330000 0x10000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
@ -671,7 +671,7 @@
status = "disabled";
};
i3c2: i3c-master@42520000 {
i3c2: i3c@42520000 {
compatible = "silvaco,i3c-master-v1";
reg = <0x42520000 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;

21
arch/arm64/boot/dts/freescale/mba8mx.dtsi
View file

@ -29,6 +29,12 @@
stdout-path = &uart3;
};
clk_xtal25: clk-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@ -100,12 +106,6 @@
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_12v: regulator-12v {
compatible = "regulator-fixed";
regulator-name = "MBA8MX_12V";
@ -219,7 +219,7 @@
line-name = "BOOT_CFG_OE#";
};
rst-usb-hub-hog {
rst_usb_hub_hog: rst-usb-hub-hog {
gpio-hog;
gpios = <13 0>;
output-high;
@ -264,6 +264,13 @@
pagesize = <16>;
vcc-supply = <&reg_vcc_3v3>;
};
pcieclk: clk@68 {
compatible = "renesas,9fgv0441";
reg = <0x68>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
};
&i2c3 {

554
arch/arm64/boot/dts/freescale/mba8xx.dtsi Normal file
View file

@ -0,0 +1,554 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
/*
* Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
adc {
compatible = "iio-hwmon";
io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>;
};
aliases {
rtc0 = &pcf85063;
rtc1 = &rtc;
};
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bl_lvds>;
pwms = <&adma_pwm 0 5000000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_12v0>;
enable-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
chosen {
stdout-path = &lpuart1;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiobuttons>;
autorepeat;
switch-a {
label = "switcha";
linux,code = <BTN_0>;
gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>;
};
switch-b {
label = "switchb";
linux,code = <BTN_1>;
gpios = <&lsio_gpio1 14 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
led1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&expander 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
led2 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&expander 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
/* TODO LVDS panels */
reg_12v0: regulator-12v0 {
compatible = "regulator-fixed";
regulator-name = "V_12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&expander 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_pcie_1v5: regulator-pcie-1v5 {
compatible = "regulator-fixed";
regulator-name = "MBA8XX_PCIE_1V5";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_pcie_1v5>;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&lsio_gpio0 30 GPIO_ACTIVE_HIGH>;
startup-delay-us = <1000>;
enable-active-high;
};
reg_pcie_3v3: regulator-pcie-3v3 {
compatible = "regulator-fixed";
regulator-name = "MBA8XX_PCIE_3V3";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_pcie_3v3>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
startup-delay-us = <1000>;
enable-active-high;
regulator-always-on;
};
reg_3v3_mb: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "V_3V3_MB";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
model = "tqm-tlv320aic32";
audio-codec = <&tlv320aic3x04>;
ssi-controller = <&sai1>;
};
};
&adc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0>;
vref-supply = <&reg_1v8>;
#io-channel-cells = <1>;
status = "okay";
};
&adma_pwm {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_admapwm>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ethphy0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
reset-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
interrupt-parent = <&lsio_gpio3>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
};
ethphy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ethphy3>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
interrupt-parent = <&lsio_gpio3>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy3>;
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0>;
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&i2c1 {
tlv320aic3x04: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
clocks = <&mclkout0_lpcg 0>;
clock-names = "mclk";
iov-supply = <&reg_1v8>;
ldoin-supply = <&reg_3v3>;
};
se97b_1c: temperature-sensor@1c {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1c>;
};
at24c02_54: eeprom@54 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x54>;
pagesize = <16>;
vcc-supply = <&reg_3v3>;
};
expander: gpio@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9538>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&lsio_gpio4>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
vcc-supply = <&reg_1v8>;
gpio-line-names = "", "LED_A",
"LED_B", "",
"DSI_EN", "USB_RESET#",
"V_12V_EN", "PCIE_DIS#";
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-1 = <&pinctrl_lpi2c2gpio>;
scl-gpios = <&lsio_gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&lsio_gpio2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* TODO LDB */
&lpspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
&lpspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&lpspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi3>;
num-cs = <2>;
cs-gpios = <&lsio_gpio0 16 GPIO_ACTIVE_LOW>;
status = "okay";
};
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>;
status = "okay";
};
&lsio_gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lsgpio3>;
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "X4_15",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
/* TODO: Mini-PCIe */
&sai1 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&sai1_lpcg 0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
srp-disable;
hnp-disable;
adp-disable;
power-active-high;
over-current-active-low;
dr_mode = "otg";
status = "okay";
};
&usbotg3 {
status = "okay";
};
&usbotg3_cdns3 {
dr_mode = "host";
status = "okay";
};
&usbphy1 {
status = "okay";
};
&usb3_phy {
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_3v3_mb>;
no-1-8-v;
no-sdio;
no-mmc;
status = "okay";
};
&iomuxc {
pinctrl_adc0: adc0grp {
fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x02000060>,
<IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x02000060>,
<IMX8QXP_ADC_IN2_ADMA_ADC_IN2 0x02000060>,
<IMX8QXP_ADC_IN3_ADMA_ADC_IN3 0x02000060>;
};
pinctrl_admapwm: admapwmgrp {
fsl,pins = <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000021>;
};
pinctrl_bl_lvds: bllvdsgrp {
fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 0x00000021>;
};
pinctrl_can0: can0grp {
fsl,pins = <IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX 0x00000021>,
<IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX 0x00000021>;
};
pinctrl_can1: can1grp {
fsl,pins = <IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021>,
<IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021>;
};
pinctrl_ethphy0: ethphy0grp {
fsl,pins = <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x00000040>,
<IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x00000040>;
};
pinctrl_ethphy3: ethphy3grp {
fsl,pins = <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x00000040>,
<IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x00000040>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000041>,
<IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000041>,
<IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000040>,
<IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000040>,
<IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000040>,
<IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000040>,
<IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000040>,
<IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000040>,
<IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000040>,
<IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000040>,
<IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000040>,
<IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000040>,
<IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000040>,
<IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000040>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000040>,
<IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000040>,
<IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000040>,
<IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000040>,
<IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000040>,
<IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000040>,
<IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000040>,
<IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000040>,
<IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000040>,
<IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000040>,
<IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000040>,
<IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000040>;
};
pinctrl_gpiobuttons: gpiobuttonsgrp {
fsl,pins = <IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 0x00000020>,
<IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 0x00000020>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL 0x06000021>,
<IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA 0x06000021>;
};
pinctrl_lpi2c2gpio: lpi2c2gpiogrp {
fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021>,
<IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x06000021>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020>,
<IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020>,
<IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>;
};
pinctrl_lsgpio3: lsgpio3grp {
fsl,pins = <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000021>;
};
pinctrl_pca9538: pca9538grp {
fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000020>;
};
pinctrl_pcieb: pcieagrp {
fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>,
<IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>,
<IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>;
};
pinctrl_reg_pcie_1v5: regpcie1v5grp {
fsl,pins = <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x00000021>;
};
pinctrl_reg_pcie_3v3: regpcie3v3grp {
fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000021>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x06000041>,
<IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000041>,
<IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000041>,
<IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000041>,
<IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000041>;
};
pinctrl_spi1: spi1grp {
fsl,pins = <IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI 0x00000041>,
<IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO 0x00000041>,
<IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK 0x00000041>,
<IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x00000021>,
<IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x00000021>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x00000041>,
<IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x00000041>,
<IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x00000041>,
<IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x00000021>;
};
pinctrl_spi3: spi3grp {
fsl,pins = <IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK 0x00000041>,
<IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI 0x00000041>,
<IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO 0x00000041>,
<IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 0x00000021>,
<IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 0x00000021>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>,
<IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC 0x00000021>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021>,
<IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>,
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>,
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>,
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>,
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>,
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>,
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>;
};
};

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arch/arm64/boot/dts/freescale/tqma8xx.dtsi Normal file
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@ -0,0 +1,265 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
/*
* Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/ {
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "V_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* global autoconfigured region for contiguous allocations
* must not exceed memory size and region
*/
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x20000000>;
alloc-ranges = <0 0x96000000 0 0x30000000>;
linux,cma-default;
};
};
};
/* TQMa8Xx only uses industrial grade, reduce trip points accordingly */
&cpu_alert0 {
temperature = <95000>;
};
&cpu_crit0 {
temperature = <100000>;
};
/* end of temperature grade adjustments */
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <66000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
};
};
/* TODO GPU */
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1gpio>;
scl-gpios = <&lsio_gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&lsio_gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
se97: temperature-sensor@1b {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1b>;
};
pcf85063: rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
quartz-load-femtofarads = <7000>;
};
at24c02: eeprom@53 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
read-only;
vcc-supply = <&reg_3v3>;
};
m24c64: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
vcc-supply = <&reg_3v3>;
};
};
&mu_m0 {
status = "okay";
};
&mu1_m0 {
status = "okay";
};
&thermal_zones {
pmic_thermal: pmic-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
trips {
pmic_alert0: trip0 {
temperature = <110000>;
hysteresis = <2000>;
type = "passive";
};
pmic_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&pmic_alert0>;
cooling-device =
<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&reg_1v8>;
vmmc-supply = <&reg_3v3>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&vpu {
compatible = "nxp,imx8qxp-vpu";
status = "okay";
};
&vpu_core0 {
memory-region = <&decoder_boot>, <&decoder_rpc>;
status = "okay";
};
&vpu_core1 {
memory-region = <&encoder_boot>, <&encoder_rpc>;
status = "okay";
};
&iomuxc {
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004d
IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004d
IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004d
IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004d
IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004d
IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004d
IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004d
IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004d
IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004d
IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004d
IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004d
IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004d
IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004d
IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004d
IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004d
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021
IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021
>;
};
pinctrl_lpi2c1gpio: lpi2c1gpiogrp {
fsl,pins = <
IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 0x06000021
IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
>;
};
};