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arm64: Filter out SVE hwcaps when FEAT_SVE isn't implemented
The hwcaps code that exposes SVE features to userspace only
considers ID_AA64ZFR0_EL1, while this is only valid when
ID_AA64PFR0_EL1.SVE advertises that SVE is actually supported.
The expectations are that when ID_AA64PFR0_EL1.SVE is 0, the
ID_AA64ZFR0_EL1 register is also 0. So far, so good.
Things become a bit more interesting if the HW implements SME.
In this case, a few ID_AA64ZFR0_EL1 fields indicate *SME*
features. And these fields overlap with their SVE interpretations.
But the architecture says that the SME and SVE feature sets must
match, so we're still hunky-dory.
This goes wrong if the HW implements SME, but not SVE. In this
case, we end-up advertising some SVE features to userspace, even
if the HW has none. That's because we never consider whether SVE
is actually implemented. Oh well.
Fix it by restricting all SVE capabilities to ID_AA64PFR0_EL1.SVE
being non-zero. The HWCAPS documentation is amended to reflect the
actually checks performed by the kernel.
Fixes: 06a916feca ("arm64: Expose SVE2 features for userspace")
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: stable@vger.kernel.org
Reviewed-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20250107-arm64-2024-dpisa-v5-1-7578da51fc3d@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Marc Zyngier
Will Deacon
parent
d3c7c48d00
commit
064737920b
2 changed files with 53 additions and 26 deletions
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@ -178,22 +178,28 @@ HWCAP2_DCPODP
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Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.
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HWCAP2_SVE2
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Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0001.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.SVEver == 0b0001.
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HWCAP2_SVEAES
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Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.AES == 0b0001.
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HWCAP2_SVEPMULL
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Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.AES == 0b0010.
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HWCAP2_SVEBITPERM
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Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.BitPerm == 0b0001.
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HWCAP2_SVESHA3
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Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.SHA3 == 0b0001.
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HWCAP2_SVESM4
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Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.SM4 == 0b0001.
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HWCAP2_FLAGM2
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Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
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@ -202,16 +208,20 @@ HWCAP2_FRINT
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Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.
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HWCAP2_SVEI8MM
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Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.I8MM == 0b0001.
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HWCAP2_SVEF32MM
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Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.F32MM == 0b0001.
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HWCAP2_SVEF64MM
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Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.F64MM == 0b0001.
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HWCAP2_SVEBF16
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Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.BF16 == 0b0001.
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HWCAP2_I8MM
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Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.
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@ -277,7 +287,8 @@ HWCAP2_EBF16
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Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.
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HWCAP2_SVE_EBF16
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Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0010.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.BF16 == 0b0010.
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HWCAP2_CSSC
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Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001.
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@ -286,7 +297,8 @@ HWCAP2_RPRFM
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Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.
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HWCAP2_SVE2P1
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Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.SVEver == 0b0010.
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HWCAP2_SME2
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Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0001.
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@ -313,7 +325,8 @@ HWCAP2_HBC
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Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001.
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HWCAP2_SVE_B16B16
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Functionality implied by ID_AA64ZFR0_EL1.B16B16 == 0b0001.
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
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ID_AA64ZFR0_EL1.B16B16 == 0b0001.
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HWCAP2_LRCPC3
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Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0011.
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@ -3008,6 +3008,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.matches = match, \
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}
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#define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \
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{ \
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__HWCAP_CAP(#cap, cap_type, cap) \
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HWCAP_CPUID_MATCH(reg, field, min_value) \
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.matches = match, \
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}
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#ifdef CONFIG_ARM64_PTR_AUTH
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static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
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{
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@ -3036,6 +3043,13 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
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};
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#endif
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#ifdef CONFIG_ARM64_SVE
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static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope)
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{
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return system_supports_sve() && has_user_cpuid_feature(cap, scope);
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}
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#endif
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static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL),
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HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES),
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@ -3078,19 +3092,19 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),
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#ifdef CONFIG_ARM64_SVE
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HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
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HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),
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HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
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HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
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HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
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HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
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HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16),
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HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
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HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),
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HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
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HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
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HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
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HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
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HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
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HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
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#endif
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#ifdef CONFIG_ARM64_GCS
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HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS),
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