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drm/amd/display: add stream ID and otg instance in dc_stream_state
[why] stream ID allows DMs to avoid memory address comparisons to compare stream equality. otg_instance allows DC to more rigorously define when otg_instance can change. specifically, it is now defined to be only mutable when dc_stream_state changes. This is better than a "get status" function which prevents efficient caching of otherwise very stable information. [how] stream ID follows similar pattern to sink ID, which is already implemented otg_instance is an output which occurs on all dc_stream modification functions Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4 changed files with 21 additions and 0 deletions
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@ -669,6 +669,7 @@ static bool construct(struct dc *dc,
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dc_ctx->dc = dc;
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dc_ctx->dc = dc;
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dc_ctx->asic_id = init_params->asic_id;
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dc_ctx->asic_id = init_params->asic_id;
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dc_ctx->dc_sink_id_count = 0;
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dc_ctx->dc_sink_id_count = 0;
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dc_ctx->dc_stream_id_count = 0;
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dc->ctx = dc_ctx;
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dc->ctx = dc_ctx;
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dc->current_state = dc_create_state();
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dc->current_state = dc_create_state();
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@ -1045,6 +1046,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
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/* Program all planes within new context*/
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/* Program all planes within new context*/
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for (i = 0; i < context->stream_count; i++) {
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for (i = 0; i < context->stream_count; i++) {
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const struct dc_link *link = context->streams[i]->link;
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const struct dc_link *link = context->streams[i]->link;
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struct dc_stream_status *status;
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if (!context->streams[i]->mode_changed)
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if (!context->streams[i]->mode_changed)
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continue;
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continue;
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@ -1069,6 +1071,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
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}
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}
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}
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}
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status = dc_stream_get_status(context->streams[i]);
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context->streams[i]->out.otg_offset = status->primary_otg_inst;
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CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
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CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
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context->streams[i]->timing.h_addressable,
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context->streams[i]->timing.h_addressable,
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context->streams[i]->timing.v_addressable,
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context->streams[i]->timing.v_addressable,
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@ -107,6 +107,9 @@ static void construct(struct dc_stream_state *stream,
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stream->out_transfer_func = dc_create_transfer_func();
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stream->out_transfer_func = dc_create_transfer_func();
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stream->out_transfer_func->type = TF_TYPE_BYPASS;
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stream->out_transfer_func->type = TF_TYPE_BYPASS;
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stream->out_transfer_func->ctx = stream->ctx;
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stream->out_transfer_func->ctx = stream->ctx;
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stream->stream_id = stream->ctx->dc_stream_id_count;
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stream->ctx->dc_stream_id_count++;
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}
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}
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static void destruct(struct dc_stream_state *stream)
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static void destruct(struct dc_stream_state *stream)
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@ -127,6 +127,18 @@ struct dc_stream_state {
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/* Computed state bits */
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/* Computed state bits */
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bool mode_changed : 1;
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bool mode_changed : 1;
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/* Output from DC when stream state is committed or altered
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* DC may only access these values during:
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* dc_commit_state, dc_commit_state_no_check, dc_commit_streams
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* values may not change outside of those calls
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*/
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struct {
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// For interrupt management, some hardware instance
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// offsets need to be exposed to DM
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uint8_t otg_offset;
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} out;
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uint32_t stream_id;
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};
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};
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struct dc_stream_update {
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struct dc_stream_update {
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@ -99,6 +99,7 @@ struct dc_context {
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struct gpio_service *gpio_service;
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struct gpio_service *gpio_service;
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struct i2caux *i2caux;
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struct i2caux *i2caux;
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uint32_t dc_sink_id_count;
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uint32_t dc_sink_id_count;
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uint32_t dc_stream_id_count;
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uint64_t fbc_gpu_addr;
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uint64_t fbc_gpu_addr;
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};
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};
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