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drm/amdgpu: add rlc TOC header file for soc24

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Add RLC autoload TOC header file for soc24 ASIC.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao 2023-06-28 12:23:58 +08:00 • committed by Alex Deucher
parent e3a911bb38
commit 00c9035633
1 changed files with 47 additions and 0 deletions
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47
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
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@ -112,6 +112,53 @@ typedef enum _SOC21_FIRMWARE_ID_ {
SOC21_FIRMWARE_ID_MAX = 37
} SOC21_FIRMWARE_ID;
typedef enum _SOC24_FIRMWARE_ID_ {
SOC24_FIRMWARE_ID_INVALID = 0,
SOC24_FIRMWARE_ID_RLC_G_UCODE = 1,
SOC24_FIRMWARE_ID_RLC_TOC = 2,
SOC24_FIRMWARE_ID_RLCG_SCRATCH = 3,
SOC24_FIRMWARE_ID_RLC_SRM_ARAM = 4,
SOC24_FIRMWARE_ID_RLC_P_UCODE = 5,
SOC24_FIRMWARE_ID_RLC_V_UCODE = 6,
SOC24_FIRMWARE_ID_RLX6_UCODE = 7,
SOC24_FIRMWARE_ID_RLX6_UCODE_CORE1 = 8,
SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT = 9,
SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT_CORE1 = 10,
SOC24_FIRMWARE_ID_SDMA_UCODE_TH0 = 11,
SOC24_FIRMWARE_ID_SDMA_UCODE_TH1 = 12,
SOC24_FIRMWARE_ID_CP_PFP = 13,
SOC24_FIRMWARE_ID_CP_ME = 14,
SOC24_FIRMWARE_ID_CP_MEC = 15,
SOC24_FIRMWARE_ID_RS64_MES_P0 = 16,
SOC24_FIRMWARE_ID_RS64_MES_P1 = 17,
SOC24_FIRMWARE_ID_RS64_PFP = 18,
SOC24_FIRMWARE_ID_RS64_ME = 19,
SOC24_FIRMWARE_ID_RS64_MEC = 20,
SOC24_FIRMWARE_ID_RS64_MES_P0_STACK = 21,
SOC24_FIRMWARE_ID_RS64_MES_P1_STACK = 22,
SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK = 23,
SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK = 24,
SOC24_FIRMWARE_ID_RS64_ME_P0_STACK = 25,
SOC24_FIRMWARE_ID_RS64_ME_P1_STACK = 26,
SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK = 27,
SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK = 28,
SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK = 29,
SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK = 30,
SOC24_FIRMWARE_ID_RLC_SRM_DRAM_SR = 31,
SOC24_FIRMWARE_ID_RLCG_SCRATCH_SR = 32,
SOC24_FIRMWARE_ID_RLCP_SCRATCH_SR = 33,
SOC24_FIRMWARE_ID_RLCV_SCRATCH_SR = 34,
SOC24_FIRMWARE_ID_RLX6_DRAM_SR = 35,
SOC24_FIRMWARE_ID_RLX6_DRAM_SR_CORE1 = 36,
SOC24_FIRMWARE_ID_RLCDEBUGLOG = 37,
SOC24_FIRMWARE_ID_SRIOV_DEBUG = 38,
SOC24_FIRMWARE_ID_SRIOV_CSA_RLC = 39,
SOC24_FIRMWARE_ID_SRIOV_CSA_SDMA = 40,
SOC24_FIRMWARE_ID_SRIOV_CSA_CP = 41,
SOC24_FIRMWARE_ID_UMF_ZONE_PAD = 42,
SOC24_FIRMWARE_ID_MAX = 43
} SOC24_FIRMWARE_ID;
typedef struct _RLC_TABLE_OF_CONTENT {
union {
unsigned int DW0;