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linux/tools/power/x86/intel-speed-select/isst.h

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tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Intel Speed Select -- Enumerate and control features
* Copyright (c) 2019 Intel Corporation.
*/
#ifndef _ISST_H_
#define _ISST_H_
#include <stdio.h>
#include <unistd.h>
#include <sys/types.h>
#include <sched.h>
#include <sys/stat.h>
#include <sys/resource.h>
#include <getopt.h>
#include <err.h>
#include <fcntl.h>
#include <signal.h>
#include <sys/time.h>
#include <limits.h>
#include <stdlib.h>
#include <string.h>
#include <cpuid.h>
#include <dirent.h>
#include <errno.h>
#include <stdarg.h>
#include <sys/ioctl.h>
tools/power/x86/intel-speed-select: Unify TRL levels TRL supports different levels including SSE/AVX2/AVX512. Avoid using hardcoded level name and structure fields, so that a loop can be used to parse each TRL level instead. This reduces several lines of source code. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:11:21 +08:00
#include <linux/isst_if.h>
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
#define BIT(x) (1 << (x))
tools/power/x86/intel-speed-select: Fix invalid core mask The core mask display is wrong in some cases. This is showing more cpus than the mask has. This is because mask is 64 bit but it used with BIT() macro to get the presence of CPU which doesn't support unsigned long long. Added a new macro for BIT_ULL and use that to get the presence of a CPU. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2020-05-19 16:28:34 -07:00
#define BIT_ULL(nr) (1ULL << (nr))
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (sizeof(long) * 8 - 1 - (h))))
#define GENMASK_ULL(h, l) \
(((~0ULL) << (l)) & (~0ULL >> (sizeof(long long) * 8 - 1 - (h))))
#define CONFIG_TDP 0x7f
#define CONFIG_TDP_GET_LEVELS_INFO 0x00
#define CONFIG_TDP_GET_TDP_CONTROL 0x01
#define CONFIG_TDP_SET_TDP_CONTROL 0x02
#define CONFIG_TDP_GET_TDP_INFO 0x03
#define CONFIG_TDP_GET_PWR_INFO 0x04
#define CONFIG_TDP_GET_TJMAX_INFO 0x05
#define CONFIG_TDP_GET_CORE_MASK 0x06
#define CONFIG_TDP_GET_TURBO_LIMIT_RATIOS 0x07
#define CONFIG_TDP_SET_LEVEL 0x08
#define CONFIG_TDP_GET_UNCORE_P0_P1_INFO 0X09
#define CONFIG_TDP_GET_P1_INFO 0x0a
#define CONFIG_TDP_GET_MEM_FREQ 0x0b
tools/power/x86/intel-speed-select: Fix display of uncore min frequency Uncore P1 is not uncore minmum frequency. This is uncore base frequency. Correct display from uncore-frequency-min(MHz) to uncore-frequency-base(Mhz). To get uncore min frequency use mailbox command CONFIG_TDP_GET_RATIO_INFO. Use this mailbox to get uncore frequency limits when present. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2022-12-09 11:23:02 -08:00
#define CONFIG_TDP_GET_RATIO_INFO 0x0c
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
#define CONFIG_TDP_GET_FACT_HP_TURBO_LIMIT_NUMCORES 0x10
#define CONFIG_TDP_GET_FACT_HP_TURBO_LIMIT_RATIOS 0x11
#define CONFIG_TDP_GET_FACT_LP_CLIPPING_RATIO 0x12
#define CONFIG_TDP_PBF_GET_CORE_MASK_INFO 0x20
#define CONFIG_TDP_PBF_GET_P1HI_P1LO_INFO 0x21
#define CONFIG_TDP_PBF_GET_TJ_MAX_INFO 0x22
#define CONFIG_TDP_PBF_GET_TDP_INFO 0X23
#define CONFIG_CLOS 0xd0
#define CLOS_PQR_ASSOC 0x00
#define CLOS_PM_CLOS 0x01
#define CLOS_PM_QOS_CONFIG 0x02
#define CLOS_STATUS 0x03
#define MBOX_CMD_WRITE_BIT 0x08
#define PM_QOS_INFO_OFFSET 0x00
#define PM_QOS_CONFIG_OFFSET 0x04
#define PM_CLOS_OFFSET 0x08
#define PQR_ASSOC_OFFSET 0x20
tools/power/x86/intel-speed-select: Add support for core-power discovery It is possible that BIOS may not enable core-power feature. In this case this additional interface will allow to enable from this utility. Also the information dump, includes the current status of core-power. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-01-14 11:22:14 -08:00
#define READ_PM_CONFIG 0x94
#define WRITE_PM_CONFIG 0x95
#define PM_FEATURE 0x03
tools/power/x86/intel-speed-select: Implement 'perf-profile info' on CascadeLake-N Add functionality for "perf-profile info" on CascadeLake-N. Sample output: intel-speed-select perf-profile info Intel(R) Speed Select Technology Executing on CPU model:85[0x55] package-0 die-0 cpu-0 perf-profile-level-0 cpu-count:20 enable-cpu-mask:00000000,000fffff enable-cpu-list:0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19 thermal-design-power-ratio:23 base-frequency(MHz):2300 speed-select-turbo-freq:unsupported speed-select-base-freq:enabled speed-select-base-freq high-priority-base-frequency(MHz):2700000 high-priority-cpu-mask:00000000,0000e8c0 high-priority-cpu-list:6,7,11,13,14,15 low-priority-base-frequency(MHz):2100000 package-1 die-0 cpu-20 perf-profile-level-0 cpu-count:20 enable-cpu-mask:000000ff,fff00000 enable-cpu-list:20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39 thermal-design-power-ratio:23 base-frequency(MHz):2300 speed-select-turbo-freq:unsupported speed-select-base-freq:enabled speed-select-base-freq high-priority-base-frequency(MHz):2700000 high-priority-cpu-mask:0000000e,8c000000 high-priority-cpu-list:26,27,31,33,34,35 low-priority-base-frequency(MHz):2100000 Signed-off-by: Prarit Bhargava <prarit@redhat.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-10-10 13:29:44 -07:00
#define DISP_FREQ_MULTIPLIER 100
tools/power/x86/intel-speed-select: Support more than 8 sockets. MAX_PACKAGE_COUNT limits the intel-speed-select to systems with 8 sockets or fewer. On a system with more than 8 sockets intel-speed-select silently ignores everything beyond the 8th socket, rendering the tool useless for those systems. Increase MAX_PACKAGE_COUNT to support systems with up to 32 sockets. Signed-off-by: Frank Ramsay <frank.ramsay@hpe.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-07-20 11:08:03 -05:00
#define MAX_PACKAGE_COUNT 32
tools/power/x86/intel-speed-select: Increase die count TPMI platform information supports up to 16 compute dies. So increase the range. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2024-03-07 15:45:54 -08:00
#define MAX_DIE_PER_PACKAGE 16
tools/power/x86/intel-speed-select: Introduce punit to isst_id Punit id can also be retrieved from ISST_IF_GET_PHY_ID. punit id is unique within a Package/Die, and together with Package id and Die id, they can be used to refer to a specific SST power domain. For current platforms, Punit id is always Zero. So no functional changes are expected for the current platforms. While here, prevent issuing IOCTL if the file /dev/isst_interface can't be opened. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-17 14:51:40 +08:00
#define MAX_PUNIT_PER_DIE 8
tools/power/x86/intel-speed-select: OOB daemon mode It is possible that some out of band agent changed config level. In this case CPUs need to be online/offline to support this config change. Add a command line option --oob, so that this tool can run as daemon and poll for config level change and take action. The poll interval is configurable in seconds using config option --poll-interval. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-01-18 15:02:57 -08:00
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
/* Unified structure to specific a CPU or a Power Domain */
struct isst_id {
int cpu;
tools/power/x86/intel-speed-select: Add pkg and die in isst_id Code uses pkg_id and die_id to refer to a specific power domain. The pkg/die information is already settled at start time. Adding package id and die id information into struct isst_id so that code does not need to retrieve them at runtime. More code cleanups can be done with the package/die info available. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:19 +08:00
int pkg;
int die;
tools/power/x86/intel-speed-select: Introduce punit to isst_id Punit id can also be retrieved from ISST_IF_GET_PHY_ID. punit id is unique within a Package/Die, and together with Package id and Die id, they can be used to refer to a specific SST power domain. For current platforms, Punit id is always Zero. So no functional changes are expected for the current platforms. While here, prevent issuing IOCTL if the file /dev/isst_interface can't be opened. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-17 14:51:40 +08:00
int punit;
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
};
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
struct isst_clos_config {
tools/power/x86/intel-speed-select: Support large clos_min/max clos_min/max in TPMI interface is frequency in MHz, thus clos_min/max needs to support larger values. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-16 21:20:00 +08:00
unsigned int clos_min;
unsigned int clos_max;
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
unsigned char epp;
unsigned char clos_prop_prio;
unsigned char clos_desired;
};
struct isst_fact_bucket_info {
tools/power/x86/intel-speed-select: Follow TRL nameing for FACT info SST-TF high priority core count and ratios and low priority core ratios are also per TRL level. Cleanup the code to follow the same nameing convention as TRL. This removes hardcoded TRL level names and variables. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:33:01 +08:00
int hp_cores;
int hp_ratios[TRL_MAX_LEVELS];
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
};
struct isst_pbf_info {
int pbf_acticated;
int pbf_available;
size_t core_cpumask_size;
cpu_set_t *core_cpumask;
int p1_high;
int p1_low;
int t_control;
int t_prochot;
int tdp;
};
#define ISST_TRL_MAX_ACTIVE_CORES 8
#define ISST_FACT_MAX_BUCKETS 8
struct isst_fact_info {
tools/power/x86/intel-speed-select: Follow TRL nameing for FACT info SST-TF high priority core count and ratios and low priority core ratios are also per TRL level. Cleanup the code to follow the same nameing convention as TRL. This removes hardcoded TRL level names and variables. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:33:01 +08:00
int lp_ratios[TRL_MAX_LEVELS];
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
struct isst_fact_bucket_info bucket_info[ISST_FACT_MAX_BUCKETS];
};
struct isst_pkg_ctdp_level_info {
int processed;
int control_cpu;
int pkg_id;
int die_id;
int level;
int fact_support;
int pbf_support;
int fact_enabled;
int pbf_enabled;
tools/power/x86/intel-speed-select: Add support for core-power discovery It is possible that BIOS may not enable core-power feature. In this case this additional interface will allow to enable from this utility. Also the information dump, includes the current status of core-power. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-01-14 11:22:14 -08:00
int sst_cp_support;
int sst_cp_enabled;
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
int tdp_ratio;
int active;
int tdp_control;
int pkg_tdp;
int pkg_min_power;
int pkg_max_power;
int fact;
int t_proc_hot;
tools/power/x86/intel-speed-select: Introduce TPMI interface support TPMI (Topology Aware Register and PM Capsule Interface) creates a flexible, extendable and software-PCIe-driver-enumerable MMIO interface for PM features. SST feature is exposed via the TPMI interface on newer Xeon platforms. Kernel TPMI based SST driver provides a series of new IOCTLs for userspace to use. Introduce support for the platforms that do SST control via TPMI interface. Compared with previous platforms, Newer Xeons also supports multi-punit in a package/die, including cpu punit and non-cpu punit. These have already been handled in the generic code. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-09 00:01:00 +08:00
int cooling_type;
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
int uncore_p0;
int uncore_p1;
tools/power/x86/intel-speed-select: Fix display of uncore min frequency Uncore P1 is not uncore minmum frequency. This is uncore base frequency. Correct display from uncore-frequency-min(MHz) to uncore-frequency-base(Mhz). To get uncore min frequency use mailbox command CONFIG_TDP_GET_RATIO_INFO. Use this mailbox to get uncore frequency limits when present. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2022-12-09 11:23:02 -08:00
int uncore_pm;
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
int sse_p1;
int avx2_p1;
int avx512_p1;
tools/power/x86/intel-speed-select: Introduce TPMI interface support TPMI (Topology Aware Register and PM Capsule Interface) creates a flexible, extendable and software-PCIe-driver-enumerable MMIO interface for PM features. SST feature is exposed via the TPMI interface on newer Xeon platforms. Kernel TPMI based SST driver provides a series of new IOCTLs for userspace to use. Introduce support for the platforms that do SST control via TPMI interface. Compared with previous platforms, Newer Xeons also supports multi-punit in a package/die, including cpu punit and non-cpu punit. These have already been handled in the generic code. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-09 00:01:00 +08:00
int amx_p1;
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
int mem_freq;
size_t core_cpumask_size;
cpu_set_t *core_cpumask;
int cpu_count;
tools/power/x86/intel-speed-select: Unify TRL levels TRL supports different levels including SSE/AVX2/AVX512. Avoid using hardcoded level name and structure fields, so that a loop can be used to parse each TRL level instead. This reduces several lines of source code. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:11:21 +08:00
unsigned long long trl_cores; /* Buckets info */
int trl_ratios[TRL_MAX_LEVELS][ISST_TRL_MAX_ACTIVE_CORES];
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
int kobj_bucket_index;
int active_bucket;
int fact_max_index;
int fact_max_config;
int pbf_found;
int pbf_active;
struct isst_pbf_info pbf_info;
struct isst_fact_info fact_info;
};
#define ISST_MAX_TDP_LEVELS (4 + 1) /* +1 for base config */
struct isst_pkg_ctdp {
int locked;
int version;
int processed;
int levels;
int current_level;
int enabled;
struct isst_pkg_ctdp_level_info ctdp_level[ISST_MAX_TDP_LEVELS];
};
tools/power/x86/intel-speed-select: Move mbox functions to isst-core.c isst-config.c should only contain generic code. Move mbox functions which are platform specific code to isst-core.c. As there are some platform specific parameters set via generic application options, introduce isst_update_platform_param to pass these parameters to platform specific code. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:38:11 +08:00
enum isst_platform_param {
ISST_PARAM_MBOX_DELAY,
ISST_PARAM_MBOX_RETRIES,
};
tools/power/x86/intel-speed-select: Introduce isst-core-mbox.c isst-core.c should contain generic core APIs only. Platform specific implementations/configurations should be removed from this file. Introduce isst-core-mbox.c and move all mbox/mmio specific functions to this file. Introduce struct isst_platform_ops which contains a series of callbacks that used by the core APIs but need platform specific implementation. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:59:54 +08:00
struct isst_platform_ops {
int (*get_disp_freq_multiplier)(void);
int (*get_trl_max_levels)(void);
char *(*get_trl_level_name)(int level);
tools/power/x86/intel-speed-select: Allow api_version based platform callbacks Different api_version suggests different kernel driver used and different interface is used to communication with the hardware. Allow setting platform specific callbacks based on api_version. Currently, all platforms with api_version 1 uses Mbox/MMIO interfaces. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 20:40:48 +08:00
void (*update_platform_param)(enum isst_platform_param param, int value);
tools/power/x86/intel-speed-select: Abstract is_punit_valid Allow platform specific implementation to identify a valid punit. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 19:39:52 +08:00
int (*is_punit_valid)(struct isst_id *id);
tools/power/x86/intel-speed-select: Abstract read_pm_config Allow platform specific implementation to get SST-CP capability and current state. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 23:19:55 +08:00
int (*read_pm_config)(struct isst_id *id, int *cp_state, int *cp_cap);
tools/power/x86/intel-speed-select: Abstract get_config_levels Allow platform specific implementation to get SST-PP level. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 20:23:26 +08:00
int (*get_config_levels)(struct isst_id *id, struct isst_pkg_ctdp *pkg_ctdp);
tools/power/x86/intel-speed-select: Abstract get_ctdp_control Allow platform specific implementation to get SST-TF/BF/CP capabilities and status. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 20:28:06 +08:00
int (*get_ctdp_control)(struct isst_id *id, int config_index, struct isst_pkg_ctdp_level_info *ctdp_level);
tools/power/x86/intel-speed-select: Abstract get_tdp_info Allow platform specific implementation to get TDP information. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 20:31:38 +08:00
int (*get_tdp_info)(struct isst_id *id, int config_index, struct isst_pkg_ctdp_level_info *ctdp_level);
tools/power/x86/intel-speed-select: Abstract get_pwr_info Allow platform specific implementation to get min and max power for a given SST-PP level. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 20:34:45 +08:00
int (*get_pwr_info)(struct isst_id *id, int config_index, struct isst_pkg_ctdp_level_info *ctdp_level);
tools/power/x86/intel-speed-select: Abstract get_coremask_info Allow platform specific implementation to get the core mask for a given SST-PP level. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-09 00:34:34 +08:00
int (*get_coremask_info)(struct isst_id *id, int config_index, struct isst_pkg_ctdp_level_info *ctdp_level);
tools/power/x86/intel-speed-select: Abstract get_get_trl Allow platform specific implementation to get turbo ratio limit of the selected SST-PP level, and AVX level. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-17 23:19:15 +08:00
int (*get_get_trl)(struct isst_id *id, int level, int avx_level, int *trl);
tools/power/x86/intel-speed-select: Abstract get_get_trls Allow platform specific implementation to get turbo ratio limits of each AVX level, for a selected SST-PP level. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-09 01:52:11 +08:00
int (*get_get_trls)(struct isst_id *id, int level, struct isst_pkg_ctdp_level_info *ctdp_level);
tools/power/x86/intel-speed-select: Abstract get_trl_bucket_info Allow platform specific implementation to get buckets info. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 21:01:08 +08:00
int (*get_trl_bucket_info)(struct isst_id *id, int level, unsigned long long *buckets_info);
tools/power/x86/intel-speed-select: Abstract set_tdp_level Allow platform specific implementation to set a SST-PP level. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-09 01:49:48 +08:00
int (*set_tdp_level)(struct isst_id *id, int tdp_level);
tools/power/x86/intel-speed-select: Abstract get_pbf_info Allow platform specific implementation to get SST-BF information. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 21:13:59 +08:00
int (*get_pbf_info)(struct isst_id *id, int level, struct isst_pbf_info *pbf_info);
tools/power/x86/intel-speed-select: Abstract set_pbf_fact_status Allow platform specific implementation to enable/disable SST-TF/BF. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 21:44:04 +08:00
int (*set_pbf_fact_status)(struct isst_id *id, int pbf, int enable);
tools/power/x86/intel-speed-select: Abstract get_fact_info Allow platform specific implementation to get SST-TF info. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 21:52:17 +08:00
int (*get_fact_info)(struct isst_id *id, int level, int fact_bucket, struct isst_fact_info *fact_info);
tools/power/x86/intel-speed-select: Abstract adjust_uncore_freq Allow platform specific implementation to adjust the uncore frequency. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-02-02 15:52:42 +08:00
void (*adjust_uncore_freq)(struct isst_id *id, int config_index, struct isst_pkg_ctdp_level_info *ctdp_level);
tools/power/x86/intel-speed-select: Abstract get_clos_information Allow platform specific implementation to get CLOS config setting. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 22:42:47 +08:00
int (*get_clos_information)(struct isst_id *id, int *enable, int *type);
tools/power/x86/intel-speed-select: Abstract pm_qos_config Allow platform specific implementation to set CLOS config settings. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 22:46:57 +08:00
int (*pm_qos_config)(struct isst_id *id, int enable_clos, int priority_type);
tools/power/x86/intel-speed-select: Abstract pm_get_clos Allow platform specific implementation to get CLOS priority setting. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 22:50:28 +08:00
int (*pm_get_clos)(struct isst_id *id, int clos, struct isst_clos_config *clos_config);
tools/power/x86/intel-speed-select: Abstract set_clos Allow platform specific implementation to set CLOS priority setting. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 22:53:48 +08:00
int (*set_clos)(struct isst_id *id, int clos, struct isst_clos_config *clos_config);
tools/power/x86/intel-speed-select: Abstract clos_get_assoc_status Allow platform specific implementation to get per core CLOS setting. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 22:55:51 +08:00
int (*clos_get_assoc_status)(struct isst_id *id, int *clos_id);
tools/power/x86/intel-speed-select: Abstract clos_associate Allow platform specific implementation to set per core CLOS setting. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-08 22:57:55 +08:00
int (*clos_associate)(struct isst_id *id, int clos_id);
tools/power/x86/intel-speed-select: Introduce isst-core-mbox.c isst-core.c should contain generic core APIs only. Platform specific implementations/configurations should be removed from this file. Introduce isst-core-mbox.c and move all mbox/mmio specific functions to this file. Introduce struct isst_platform_ops which contains a series of callbacks that used by the core APIs but need platform specific implementation. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:59:54 +08:00
};
tools/power/x86/intel-speed-select: Introduce is_cpu_in_power_domain helper struct isst_id contains cpu, package and die info, and it can represent a specific SST power domain. Introduce is_cpu_in_power_domain() helper to identify if a cpu is in a specified power_domain. And cleanup the code to use the new helper. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:22 +08:00
extern int is_cpu_in_power_domain(int cpu, struct isst_id *id);
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
extern int get_topo_max_cpus(void);
tools/power/x86/intel-speed-select: Convert more function to use isst_id With pkg and die info added into struct isst_id, more functions can be converted to use struct isst_id as parameter. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:20 +08:00
extern int get_cpu_count(struct isst_id *id);
extern int get_max_punit_core_id(struct isst_id *id);
tools/power/x86/intel-speed-select: Introduce api_version helper In some cases, the output format may be different with different api_version because of different capabilities or for backward capabilities reason. Introduce api_version() to get the api_version of the platform running. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 20:51:33 +08:00
extern int api_version(void);
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
/* Common interfaces */
tools/power/x86/intel-speed-select: Add an API for error/information print Add a common API which can be used to print all error and information messages. In this way a common format can be used. For json output an error index in suffixed to make unique error key. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-03-05 14:45:22 -08:00
FILE *get_output_file(void);
tools/power/x86/intel-speed-select: Introduce is_debug_enabled() Platform specific code also needs to give debug output. Introduce is_debug_enabled() for this purpose. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-09 01:56:04 +08:00
extern int is_debug_enabled(void);
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
extern void debug_printf(const char *format, ...);
extern int out_format_is_json(void);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern void set_isst_id(struct isst_id *id, int cpu);
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
extern size_t alloc_cpu_set(cpu_set_t **cpu_set);
extern void free_cpu_set(cpu_set_t *cpu_set);
extern int find_phy_core_num(int logical_cpu);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern void set_cpu_mask_from_punit_coremask(struct isst_id *id,
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
unsigned long long core_mask,
size_t core_cpumask_size,
cpu_set_t *core_cpumask,
int *cpu_cnt);
extern int isst_send_msr_command(unsigned int cpu, unsigned int command,
int write, unsigned long long *req_resp);
tools/power/x86/intel-speed-select: Allow api_version based platform callbacks Different api_version suggests different kernel driver used and different interface is used to communication with the hardware. Allow setting platform specific callbacks based on api_version. Currently, all platforms with api_version 1 uses Mbox/MMIO interfaces. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 20:40:48 +08:00
extern int isst_set_platform_ops(int api_version);
tools/power/x86/intel-speed-select: Move mbox functions to isst-core.c isst-config.c should only contain generic code. Move mbox functions which are platform specific code to isst-core.c. As there are some platform specific parameters set via generic application options, introduce isst_update_platform_param to pass these parameters to platform specific code. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:38:11 +08:00
extern void isst_update_platform_param(enum isst_platform_param, int vale);
tools/power/x86/intel-speed-select: Introduce isst_get_disp_freq_multiplier Remove hardcoded DISP_FREQ_MULTIPLIER in the code and use isst_get_disp_freq_multiplier() instead. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:44:59 +08:00
extern int isst_get_disp_freq_multiplier(void);
tools/power/x86/intel-speed-select: Unify TRL levels TRL supports different levels including SSE/AVX2/AVX512. Avoid using hardcoded level name and structure fields, so that a loop can be used to parse each TRL level instead. This reduces several lines of source code. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:11:21 +08:00
extern int isst_get_trl_max_levels(void);
extern char *isst_get_trl_level_name(int level);
tools/power/x86/intel-speed-select: Introduce isst_is_punit_valid() Introduce isst_is_punit_valid() for checking a valid domain. For current platforms, it requires a punit 0 in a valid Package/Die. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-17 15:33:23 +08:00
extern int isst_is_punit_valid(struct isst_id *id);
tools/power/x86/intel-speed-select: Unify TRL levels TRL supports different levels including SSE/AVX2/AVX512. Avoid using hardcoded level name and structure fields, so that a loop can be used to parse each TRL level instead. This reduces several lines of source code. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:11:21 +08:00
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern int isst_get_ctdp_levels(struct isst_id *id, struct isst_pkg_ctdp *pkg_dev);
extern int isst_get_ctdp_control(struct isst_id *id, int config_index,
tools/power/x86/intel-speed-select: Enhance --info option Add additional information, which will allow user to detect available features. This will allow users to check presence of features before continue to test. A sample output: $sudo ./intel-speed-select --info Intel(R) Speed Select Technology Executing on CPU model:85[0x55] Platform: API version : 1 Platform: Driver version : 1 Platform: mbox supported : 1 Platform: mmio supported : 0 Intel(R) SST-PP (feature perf-profile) is not supported Only performance level 0 (base level) is present TDP level change control is locked Intel(R) SST-TF (feature turbo-freq) is supported Intel(R) SST-BF (feature base-freq) is supported Intel(R) SST-CP (feature core-power) is supported Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-03-05 14:45:21 -08:00
struct isst_pkg_ctdp_level_info *ctdp_level);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern int isst_get_coremask_info(struct isst_id *id, int config_index,
tools/power/x86/intel-speed-select: Allow online/offline based on tdp Using enable core mask, do online offline CPUs. There is a new option --online|-o for set-config-level. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-09-14 12:45:44 -07:00
struct isst_pkg_ctdp_level_info *ctdp_level);
tools/power/x86/intel-speed-select: Abstract adjust_uncore_freq Allow platform specific implementation to adjust the uncore frequency. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-02-02 15:52:42 +08:00
extern void isst_adjust_uncore_freq(struct isst_id *id, int config_index,
tools/power/x86/intel-speed-select: Fix display of uncore min frequency Uncore P1 is not uncore minmum frequency. This is uncore base frequency. Correct display from uncore-frequency-min(MHz) to uncore-frequency-base(Mhz). To get uncore min frequency use mailbox command CONFIG_TDP_GET_RATIO_INFO. Use this mailbox to get uncore frequency limits when present. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2022-12-09 11:23:02 -08:00
struct isst_pkg_ctdp_level_info *ctdp_level);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern int isst_get_process_ctdp(struct isst_id *id, int tdp_level,
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
struct isst_pkg_ctdp *pkg_dev);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern void isst_get_process_ctdp_complete(struct isst_id *id,
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
struct isst_pkg_ctdp *pkg_dev);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern void isst_ctdp_display_information(struct isst_id *id, FILE *outf, int tdp_level,
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
struct isst_pkg_ctdp *pkg_dev);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern void isst_ctdp_display_core_info(struct isst_id *id, FILE *outf, char *prefix,
tools/power/x86/intel-speed-select: Improve output of perf-profile commands Improve output of perf-profile commands: get-config-enabled get-lock-status Instead of showing 0/1, show meaningful strings. Also show error when command is failed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-03-05 14:45:27 -08:00
unsigned int val, char *str0, char *str1);
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
extern void isst_ctdp_display_information_start(FILE *outf);
extern void isst_ctdp_display_information_end(FILE *outf);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern void isst_pbf_display_information(struct isst_id *id, FILE *outf, int level,
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
struct isst_pbf_info *info);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern int isst_set_tdp_level(struct isst_id *id, int tdp_level);
extern int isst_set_pbf_fact_status(struct isst_id *id, int pbf, int enable);
extern int isst_get_pbf_info(struct isst_id *id, int level,
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
struct isst_pbf_info *pbf_info);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern int isst_get_fact_info(struct isst_id *id, int level, int fact_bucket,
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
struct isst_fact_info *fact_info);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern void isst_fact_display_information(struct isst_id *id, FILE *outf, int level,
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
int fact_bucket, int fact_avx,
struct isst_fact_info *fact_info);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern int isst_set_trl(struct isst_id *id, unsigned long long trl);
extern int isst_get_trl(struct isst_id *id, unsigned long long *trl);
extern int isst_set_trl_from_current_tdp(struct isst_id *id, unsigned long long trl);
extern int isst_get_config_tdp_lock_status(struct isst_id *id);
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern int isst_pm_qos_config(struct isst_id *id, int enable_clos, int priority_type);
extern int isst_pm_get_clos(struct isst_id *id, int clos,
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
struct isst_clos_config *clos_config);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern int isst_set_clos(struct isst_id *id, int clos,
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
struct isst_clos_config *clos_config);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern int isst_clos_associate(struct isst_id *id, int clos);
extern int isst_clos_get_assoc_status(struct isst_id *id, int *clos_id);
extern void isst_clos_display_information(struct isst_id *id, FILE *outf, int clos,
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
struct isst_clos_config *clos_config);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern void isst_clos_display_assoc_information(struct isst_id *id, FILE *outf, int clos);
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern void isst_display_result(struct isst_id *id, FILE *outf, char *feature, char *cmd,
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
int result);
tools/power/x86/intel-speed-select: Extend core-power command set Add additional command to get the clos enable and priority type. The current info option is actually dumping per clos QOS config, so name the command appropriately to get-config. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-09-14 12:45:47 -07:00
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern int isst_clos_get_clos_information(struct isst_id *id, int *enable, int *type);
extern void isst_clos_display_clos_information(struct isst_id *id, FILE *outf,
tools/power/x86/intel-speed-select: Enhance core-power info command In addition to CLOS enable status, also show the core-power feature status. This will help why clos enable status didn't give desired results as the core-power feature may be disabled or unsupported. The new display looks as follows: $intel-speed-select core-power info Intel(R) Speed Select Technology .. package-0 die-0 cpu-0 core-power support-status:supported enable-status:enabled clos-enable-status:1 priority-type:0 In the above display "support-status" and "enable-status", shows the status of the core-power feature and "clos-enable-status", shows the status of the clos. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-03-05 14:45:14 -08:00
int clos_enable, int type,
int state, int cap);
tools/power/x86/intel-speed-select: Implement 'perf-profile info' on CascadeLake-N Add functionality for "perf-profile info" on CascadeLake-N. Sample output: intel-speed-select perf-profile info Intel(R) Speed Select Technology Executing on CPU model:85[0x55] package-0 die-0 cpu-0 perf-profile-level-0 cpu-count:20 enable-cpu-mask:00000000,000fffff enable-cpu-list:0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19 thermal-design-power-ratio:23 base-frequency(MHz):2300 speed-select-turbo-freq:unsupported speed-select-base-freq:enabled speed-select-base-freq high-priority-base-frequency(MHz):2700000 high-priority-cpu-mask:00000000,0000e8c0 high-priority-cpu-list:6,7,11,13,14,15 low-priority-base-frequency(MHz):2100000 package-1 die-0 cpu-20 perf-profile-level-0 cpu-count:20 enable-cpu-mask:000000ff,fff00000 enable-cpu-list:20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39 thermal-design-power-ratio:23 base-frequency(MHz):2300 speed-select-turbo-freq:unsupported speed-select-base-freq:enabled speed-select-base-freq high-priority-base-frequency(MHz):2700000 high-priority-cpu-mask:0000000e,8c000000 high-priority-cpu-list:26,27,31,33,34,35 low-priority-base-frequency(MHz):2100000 Signed-off-by: Prarit Bhargava <prarit@redhat.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-10-10 13:29:44 -07:00
extern int is_clx_n_platform(void);
tools/power/x86/intel-speed-select: Support platform with limited Intel(R) Speed Select There are some platforms, where there limited support of Intel(R) SST features. Here perf-profile has only one base configuration and limited support of commands. But still has support for discovery of base-freq and turbo-freq features. So it is important to show minimum features to use base-freq and turbo-freq features. Here the change are: - When there is no support of CONFIG_TDP_GET_LEVELS_INFO, then instead of treating this as fatal error, treat this with number of config levels = 0, that means only base level 0 is present. - There is no support of mail box commands to get base frequencies or turbo frequencies. Here present base frequency by reading cpufreq base freq and turbo frequency by reading MSR 0x1AD. - Don't display any field, which has value == 0. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-11-04 03:02:44 -08:00
extern int get_cpufreq_base_freq(int cpu);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern int isst_read_pm_config(struct isst_id *id, int *cp_state, int *cp_cap);
tools/power/x86/intel-speed-select: Add an API for error/information print Add a common API which can be used to print all error and information messages. In this way a common format can be used. For json output an error index in suffixed to make unique error key. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-03-05 14:45:22 -08:00
extern void isst_display_error_info_message(int error, char *msg, int arg_valid, int arg);
tools/power/x86/intel-speed-select: Read TRL from mailbox When SST-PP feature is not present, the TRL (Turbo Ratio Limits) is read from MSRs. This is done as the mailbox command will fail on Skylake-X based platform. But for IceLake servers, mailbox commands can still be used. So add a check to allow for non Skylake based platforms to read from mail box commands. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Link: https://lore.kernel.org/platform-driver-x86/57d6648282491906e0e1f70fe3b9a44f72cec90d.camel@intel.com/ Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2020-11-23 16:56:05 -08:00
extern int is_skx_based_platform(void);
tools/power/x86/intel-speed-select: Fix uncore memory frequency display The uncore memory frequency value from the mailbox command CONFIG_TDP_GET_MEM_FREQ needs to be scaled based on the platform for display. There is no single constant multiplier. This change introduces CPU model specific memory frequency multiplier. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-05-12 03:17:32 -07:00
extern int is_spr_platform(void);
tools/power/x86/intel-speed-select: Identify Emerald Rapids There are some differences compared to Sapphire Rapids. So, add a separate API. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-02-22 22:53:02 -08:00
extern int is_emr_platform(void);
tools/power/x86/intel-speed-select: Fix uncore memory frequency display The uncore memory frequency value from the mailbox command CONFIG_TDP_GET_MEM_FREQ needs to be scaled based on the platform for display. There is no single constant multiplier. This change introduces CPU model specific memory frequency multiplier. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-05-12 03:17:32 -07:00
extern int is_icx_platform(void);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern void isst_trl_display_information(struct isst_id *id, FILE *outf, unsigned long long trl);
tools/power/x86/intel-speed-select: OOB daemon mode It is possible that some out of band agent changed config level. In this case CPUs need to be online/offline to support this config change. Add a command line option --oob, so that this tool can run as daemon and poll for config level change and take action. The poll interval is configurable in seconds using config option --poll-interval. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-01-18 15:02:57 -08:00
extern void set_cpu_online_offline(int cpu, int state);
tools/power/x86/intel-speed-select: Rename for_each_online_package_in_set for_each_online_package_in_set is actually used to invoke callback for each power domain. This is not a problem when there is a single power domain within a package/die, but it does not reflect the truth in multi-punit case. Rename for_each_online_package_in_set to for_each_online_power_domain_in_set. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-17 15:50:43 +08:00
extern void for_each_online_power_domain_in_set(void (*callback)(struct isst_id *, void *, void *,
tools/power/x86/intel-speed-select: OOB daemon mode It is possible that some out of band agent changed config level. In this case CPUs need to be online/offline to support this config change. Add a command line option --oob, so that this tool can run as daemon and poll for config level change and take action. The poll interval is configurable in seconds using config option --poll-interval. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-01-18 15:02:57 -08:00
void *, void *),
void *arg1, void *arg2, void *arg3,
void *arg4);
extern int isst_daemon(int debug_mode, int poll_interval, int no_daemon);
tools/power/x86/intel-speed-select: Introduce struct isst_id SST control is power-domain based rather than cpu based, on all the systems including Sapphire Rapids and ealier. SST core APIs uses cpu id as parameter, and use the underlying pkg_id and die_id information to find a power domain, this is not straight forward and introduces obscure logics in the code. Introduce struct isst_id to represent a SST Power Domain. All core APIs are converted to use struct isst_id as parameter instead of using cpu id. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 23:58:18 +08:00
extern void process_level_change(struct isst_id *id);
tools/power/x86/intel-speed-select: HFI support Read HFI (Hardware Feedback Interface) events to process config level changes in oob mode. When HFI is supported there is no need for polling to check config level change. Subscribe to Linux thermal netlink messages and process message: THERMAL_GENL_EVENT_CPU_CAPABILITY_CHANGE. This message contains cpu number, performance and energy efficiency. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-01-18 16:44:20 -08:00
extern int hfi_main(void);
extern void hfi_exit(void);
tools/power/x86/intel-speed-select: Introduce isst-core-mbox.c isst-core.c should contain generic core APIs only. Platform specific implementations/configurations should be removed from this file. Introduce isst-core-mbox.c and move all mbox/mmio specific functions to this file. Introduce struct isst_platform_ops which contains a series of callbacks that used by the core APIs but need platform specific implementation. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:59:54 +08:00
/* Interface specific callbacks */
extern struct isst_platform_ops *mbox_get_platform_ops(void);
tools/power/x86/intel-speed-select: Introduce TPMI interface support TPMI (Topology Aware Register and PM Capsule Interface) creates a flexible, extendable and software-PCIe-driver-enumerable MMIO interface for PM features. SST feature is exposed via the TPMI interface on newer Xeon platforms. Kernel TPMI based SST driver provides a series of new IOCTLs for userspace to use. Introduce support for the platforms that do SST control via TPMI interface. Compared with previous platforms, Newer Xeons also supports multi-punit in a package/die, including cpu punit and non-cpu punit. These have already been handled in the generic code. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-09 00:01:00 +08:00
extern struct isst_platform_ops *tpmi_get_platform_ops(void);
tools/power/x86/intel-speed-select: Introduce isst-core-mbox.c isst-core.c should contain generic core APIs only. Platform specific implementations/configurations should be removed from this file. Introduce isst-core-mbox.c and move all mbox/mmio specific functions to this file. Introduce struct isst_platform_ops which contains a series of callbacks that used by the core APIs but need platform specific implementation. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2022-08-20 18:59:54 +08:00
tools/power/x86/intel-speed-select: Use cgroup v2 isolation On supported systems, it is possiible to isolate CPUs instead of CPU online/offline. This is optional and can be specified using -g option when running as daemon or in combination with -o option for SST-PP level change. CPU isolation doesn't isolate IRQs. So IRQs needs to be moved away from isoolated CPUs. This can be done via IRQ sysfs or irqbalance daemon. The IRQ balance daemon is also capable to parse thermal HFI messages to move IRQs away from CPUS, which are supposed be isolated. But this requires version released after July 2022. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-02-22 03:42:19 -08:00
/* Cgroup related interface */
extern int enable_cpuset_controller(void);
tools/power/x86/intel-speed-select: Use cgroup isolate for CPU 0 From kernel version 6.5, CPU 0 hotplug capability is deprecated. If some SST profile doesn't have CPU 0, then it is no longer possible to offline CPU 0. This means that user space threads will still run on CPU 0. To workaround this issue, use cgroup v2 isolation feature. Whenever there /sys/devices/system/cpu/cpu0/online file is absent or open fails, isolate CPU 0 via CPU cgroup v2 isolation. Also add a command line option to force even if the /sys/devices/system/cpu/cpu0/online is present. The previous commit "01bcb56f059e ("tools/power/x86/intel-speed-select: Prevent CPU 0 offline") was just warning about this issue based on the kernel version 6.5 and above. With this new approach, instead of warning take action to mitigate the issue. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-10-03 14:46:30 -07:00
extern int isolate_cpus(struct isst_id *id, int mask_size, cpu_set_t *cpu_mask,
int level, int cpu_0_only);
tools/power/x86/intel-speed-select: Use cgroup v2 isolation On supported systems, it is possiible to isolate CPUs instead of CPU online/offline. This is optional and can be specified using -g option when running as daemon or in combination with -o option for SST-PP level change. CPU isolation doesn't isolate IRQs. So IRQs needs to be moved away from isoolated CPUs. This can be done via IRQ sysfs or irqbalance daemon. The IRQ balance daemon is also capable to parse thermal HFI messages to move IRQs away from CPUS, which are supposed be isolated. But this requires version released after July 2022. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-02-22 03:42:19 -08:00
extern int use_cgroupv2(void);
tools/power/x86: A tool to validate Intel Speed Select commands The Intel(R) Speed select technologies contains four features. Performance profile:An non architectural mechanism that allows multiple optimized performance profiles per system via static and/or dynamic adjustment of core count, workload, Tjmax, and TDP, etc. aka ISS in the documentation. Base Frequency: Enables users to increase guaranteed base frequency on certain cores (high priority cores) in exchange for lower base frequency on remaining cores (low priority cores). aka PBF in the documenation. Turbo frequency: Enables the ability to set different turbo ratio limits to cores based on priority. aka FACT in the documentation. Core power: An Interface that allows user to define per core/tile priority. There is a multi level help for commands and options. This can be used to check required arguments for each feature and commands for the feature. To start navigating the features start with $sudo intel-speed-select --help For help on a specific feature for example $sudo intel-speed-select perf-profile --help To get help for a command for a feature for example $sudo intel-speed-select perf-profile get-lock-status --help Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Len Brown <len.brown@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-06-30 10:14:08 -07:00
#endif
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