2020-12-10 00:06:03 +02:00
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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2024-02-06 18:02:08 +02:00
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* Copyright (C) 2005-2014, 2018-2024 Intel Corporation
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2020-12-10 00:06:03 +02:00
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* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
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* Copyright (C) 2016-2017 Intel Deutschland GmbH
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*/
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2012-03-26 08:27:40 -07:00
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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2011-07-03 15:21:01 -04:00
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#include <linux/module.h>
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2011-05-24 11:39:02 +03:00
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#include <linux/pci.h>
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iwlwifi: pcie: retrieve and parse ACPI power limitations
Some platforms may have power limitations on PCIe cards connected to
specific root ports.
This information is encoded as part of the ACPI tables, for instance:
<snip>
Name (SPLX, Package (0x02)
{
Zero,
Package (0x03)
{
0x07,
0x00000500,
0x80000000
}
})
Method (SPLC, 0, Serialized)
{
Return (SPLX)
}
</snip>
The structure returned contains the domain type, the default power
limitation and the default time window (reserved for future use).
Upon PCI probing, call the relevant ACPI method, parse the returned
structure, and save the power limitation.
Signed-off-by: Ido Yariv <idox.yariv@intel.com>
Reviewed-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
2014-01-16 21:00:11 -05:00
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#include <linux/acpi.h>
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2011-05-24 11:39:02 +03:00
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2017-09-19 12:35:18 +03:00
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#include "fw/acpi.h"
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iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-25 23:10:48 -07:00
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#include "iwl-trans.h"
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2012-02-07 14:18:40 +02:00
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#include "iwl-drv.h"
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2018-08-02 17:08:40 +03:00
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#include "iwl-prph.h"
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2012-05-16 19:13:54 +02:00
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#include "internal.h"
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2011-06-10 11:23:36 -07:00
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2021-03-30 16:24:58 +03:00
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#define TRANS_CFG_MARKER BIT(0)
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#define _IS_A(cfg, _struct) __builtin_types_compatible_p(typeof(cfg), \
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struct _struct)
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extern int _invalid_type;
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#define _TRANS_CFG_MARKER(cfg) \
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(__builtin_choose_expr(_IS_A(cfg, iwl_cfg_trans_params), \
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TRANS_CFG_MARKER, \
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__builtin_choose_expr(_IS_A(cfg, iwl_cfg), 0, _invalid_type)))
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#define _ASSIGN_CFG(cfg) (_TRANS_CFG_MARKER(cfg) + (kernel_ulong_t)&(cfg))
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2011-05-24 11:39:02 +03:00
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#define IWL_PCI_DEVICE(dev, subdev, cfg) \
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.vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
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.subvendor = PCI_ANY_ID, .subdevice = (subdev), \
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2021-03-30 16:24:58 +03:00
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.driver_data = _ASSIGN_CFG(cfg)
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2011-05-24 11:39:02 +03:00
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/* Hardware specific file defines the PCI IDs table for that hardware module */
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2024-03-19 10:10:16 +02:00
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VISIBLE_IF_IWLWIFI_KUNIT const struct pci_device_id iwl_hw_card_ids[] = {
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2013-06-10 16:12:52 +02:00
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#if IS_ENABLED(CONFIG_IWLDVM)
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2011-05-24 11:39:02 +03:00
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{IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
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/* 5300 Series WiFi */
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{IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
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/* 5350 Series WiFi/WiMax */
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{IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
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/* 5150 Series Wifi/WiMax */
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{IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
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2013-07-18 19:11:26 +03:00
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{IWL_PCI_DEVICE(0x423C, 0x1326, iwl5150_abg_cfg)}, /* Half Mini Card */
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2011-05-24 11:39:02 +03:00
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{IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
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{IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
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{IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
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/* 6x00 Series */
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{IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
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2013-09-24 19:34:26 +03:00
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{IWL_PCI_DEVICE(0x422B, 0x1108, iwl6000_3agn_cfg)},
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2011-05-24 11:39:02 +03:00
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{IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
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2013-09-24 19:34:26 +03:00
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{IWL_PCI_DEVICE(0x422B, 0x1128, iwl6000_3agn_cfg)},
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2011-05-24 11:39:02 +03:00
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{IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
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{IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
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{IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
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{IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
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{IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
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{IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
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2013-09-24 19:34:26 +03:00
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{IWL_PCI_DEVICE(0x4238, 0x1118, iwl6000_3agn_cfg)},
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2011-05-24 11:39:02 +03:00
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{IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
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{IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
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/* 6x05 Series */
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{IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
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{IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
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{IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
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2013-09-24 19:34:26 +03:00
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{IWL_PCI_DEVICE(0x0082, 0x1308, iwl6005_2agn_cfg)},
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2011-05-24 11:39:02 +03:00
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{IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
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{IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
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2013-09-24 19:34:26 +03:00
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{IWL_PCI_DEVICE(0x0082, 0x1328, iwl6005_2agn_cfg)},
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2011-05-24 11:39:02 +03:00
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{IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
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2013-09-24 19:34:26 +03:00
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{IWL_PCI_DEVICE(0x0085, 0x1318, iwl6005_2agn_cfg)},
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2011-05-24 11:39:02 +03:00
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{IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
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2011-08-25 23:10:56 -07:00
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{IWL_PCI_DEVICE(0x0082, 0xC020, iwl6005_2agn_sff_cfg)},
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2011-09-15 11:46:36 -07:00
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{IWL_PCI_DEVICE(0x0085, 0xC220, iwl6005_2agn_sff_cfg)},
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2013-09-24 19:34:26 +03:00
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{IWL_PCI_DEVICE(0x0085, 0xC228, iwl6005_2agn_sff_cfg)},
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2012-02-22 10:21:09 -08:00
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{IWL_PCI_DEVICE(0x0082, 0x4820, iwl6005_2agn_d_cfg)},
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{IWL_PCI_DEVICE(0x0082, 0x1304, iwl6005_2agn_mow1_cfg)},/* low 5GHz active */
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{IWL_PCI_DEVICE(0x0082, 0x1305, iwl6005_2agn_mow2_cfg)},/* high 5GHz active */
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2011-05-24 11:39:02 +03:00
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/* 6x30 Series */
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{IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
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{IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
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{IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
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{IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
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{IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
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{IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
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{IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
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{IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
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{IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
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{IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
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{IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
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{IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
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{IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
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{IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
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{IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
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{IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
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/* 6x50 WiFi/WiMax Series */
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{IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
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{IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
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{IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
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{IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
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{IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
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{IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
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/* 6150 WiFi/WiMax Series */
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{IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
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{IWL_PCI_DEVICE(0x0885, 0x1307, iwl6150_bg_cfg)},
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{IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
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{IWL_PCI_DEVICE(0x0885, 0x1327, iwl6150_bg_cfg)},
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{IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
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{IWL_PCI_DEVICE(0x0886, 0x1317, iwl6150_bg_cfg)},
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/* 1000 Series WiFi */
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{IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
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{IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
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{IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
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{IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
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{IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
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{IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
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{IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
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{IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
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{IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
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{IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
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{IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
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{IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
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/* 100 Series WiFi */
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{IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
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{IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
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{IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
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{IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
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{IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
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{IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
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/* 130 Series WiFi */
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{IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
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{IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
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{IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
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{IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
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|
{IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
|
|
|
|
|
|
|
|
/* 2x00 Series */
|
|
|
|
{IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
|
2011-08-25 23:11:17 -07:00
|
|
|
{IWL_PCI_DEVICE(0x0890, 0x4822, iwl2000_2bgn_d_cfg)},
|
2011-05-24 11:39:02 +03:00
|
|
|
|
|
|
|
/* 2x30 Series */
|
|
|
|
{IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
|
|
|
|
|
|
|
|
/* 6x35 Series */
|
|
|
|
{IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
|
2013-09-24 19:34:26 +03:00
|
|
|
{IWL_PCI_DEVICE(0x088E, 0x406A, iwl6035_2agn_sff_cfg)},
|
2011-05-24 11:39:02 +03:00
|
|
|
{IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
|
2013-09-24 19:34:26 +03:00
|
|
|
{IWL_PCI_DEVICE(0x088F, 0x426A, iwl6035_2agn_sff_cfg)},
|
2011-05-24 11:39:02 +03:00
|
|
|
{IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
|
2013-09-24 19:34:26 +03:00
|
|
|
{IWL_PCI_DEVICE(0x088E, 0x446A, iwl6035_2agn_sff_cfg)},
|
2012-02-22 08:18:55 -08:00
|
|
|
{IWL_PCI_DEVICE(0x088E, 0x4860, iwl6035_2agn_cfg)},
|
2013-03-30 14:26:37 +08:00
|
|
|
{IWL_PCI_DEVICE(0x088F, 0x5260, iwl6035_2agn_cfg)},
|
2011-05-24 11:39:02 +03:00
|
|
|
|
|
|
|
/* 105 Series */
|
|
|
|
{IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_bgn_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x0895, 0x0222, iwl105_bgn_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x0894, 0x0422, iwl105_bgn_cfg)},
|
2011-10-10 07:27:01 -07:00
|
|
|
{IWL_PCI_DEVICE(0x0894, 0x0822, iwl105_bgn_d_cfg)},
|
2011-05-24 11:39:02 +03:00
|
|
|
|
|
|
|
/* 135 Series */
|
|
|
|
{IWL_PCI_DEVICE(0x0892, 0x0062, iwl135_bgn_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x0893, 0x0262, iwl135_bgn_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x0892, 0x0462, iwl135_bgn_cfg)},
|
2013-06-10 16:12:52 +02:00
|
|
|
#endif /* CONFIG_IWLDVM */
|
2011-05-24 11:39:02 +03:00
|
|
|
|
2013-06-10 16:12:52 +02:00
|
|
|
#if IS_ENABLED(CONFIG_IWLMVM)
|
2013-10-08 08:03:07 +02:00
|
|
|
/* 7260 Series */
|
2013-01-24 13:52:01 +01:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4070, iwl7260_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4072, iwl7260_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4170, iwl7260_2ac_cfg)},
|
2014-09-17 10:31:56 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4C60, iwl7260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4C70, iwl7260_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4060, iwl7260_2n_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x406A, iwl7260_2n_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4160, iwl7260_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4062, iwl7260_n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4162, iwl7260_n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0x4270, iwl7260_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0x4272, iwl7260_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0x4260, iwl7260_2n_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0x426A, iwl7260_2n_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0x4262, iwl7260_n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4470, iwl7260_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4472, iwl7260_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4460, iwl7260_2n_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x446A, iwl7260_2n_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4462, iwl7260_n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4870, iwl7260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x486E, iwl7260_2ac_cfg)},
|
2013-07-24 14:49:18 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4A70, iwl7260_2ac_cfg_high_temp)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4A6E, iwl7260_2ac_cfg_high_temp)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4A6C, iwl7260_2ac_cfg_high_temp)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4570, iwl7260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4560, iwl7260_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0x4370, iwl7260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0x4360, iwl7260_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x5070, iwl7260_2ac_cfg)},
|
2013-10-23 15:44:25 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x5072, iwl7260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x5170, iwl7260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x5770, iwl7260_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4020, iwl7260_2n_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x402A, iwl7260_2n_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0x4220, iwl7260_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0x4420, iwl7260_2n_cfg)},
|
2013-01-24 13:52:01 +01:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC070, iwl7260_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC072, iwl7260_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC170, iwl7260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC060, iwl7260_2n_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC06A, iwl7260_2n_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC160, iwl7260_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC062, iwl7260_n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC162, iwl7260_n_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC770, iwl7260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC760, iwl7260_2n_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0xC270, iwl7260_2ac_cfg)},
|
2014-09-17 10:31:56 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xCC70, iwl7260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xCC60, iwl7260_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0xC272, iwl7260_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0xC260, iwl7260_2n_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0xC26A, iwl7260_n_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0xC262, iwl7260_n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC470, iwl7260_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC472, iwl7260_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC460, iwl7260_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC462, iwl7260_n_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC570, iwl7260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC560, iwl7260_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0xC370, iwl7260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC360, iwl7260_2n_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC020, iwl7260_2n_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC02A, iwl7260_2n_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B2, 0xC220, iwl7260_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B1, 0xC420, iwl7260_2n_cfg)},
|
|
|
|
|
|
|
|
/* 3160 Series */
|
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x0070, iwl3160_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x0072, iwl3160_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x0170, iwl3160_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x0172, iwl3160_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x0060, iwl3160_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x0062, iwl3160_n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B4, 0x0270, iwl3160_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B4, 0x0272, iwl3160_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x0470, iwl3160_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x0472, iwl3160_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B4, 0x0370, iwl3160_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x8070, iwl3160_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x8072, iwl3160_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x8170, iwl3160_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x8172, iwl3160_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x8060, iwl3160_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x8062, iwl3160_n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B4, 0x8270, iwl3160_2ac_cfg)},
|
2014-09-08 08:57:05 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B4, 0x8370, iwl3160_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B4, 0x8272, iwl3160_2ac_cfg)},
|
2013-04-23 18:19:11 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x8470, iwl3160_2ac_cfg)},
|
2013-09-22 08:23:23 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x8570, iwl3160_2ac_cfg)},
|
2013-10-23 15:44:25 +03:00
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x1070, iwl3160_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x08B3, 0x1170, iwl3160_2ac_cfg)},
|
2013-10-08 08:03:07 +02:00
|
|
|
|
2014-09-08 08:57:05 +03:00
|
|
|
/* 3165 Series */
|
|
|
|
{IWL_PCI_DEVICE(0x3165, 0x4010, iwl3165_2ac_cfg)},
|
2014-12-02 22:09:55 +02:00
|
|
|
{IWL_PCI_DEVICE(0x3165, 0x4012, iwl3165_2ac_cfg)},
|
2015-06-22 13:44:05 +03:00
|
|
|
{IWL_PCI_DEVICE(0x3166, 0x4212, iwl3165_2ac_cfg)},
|
2014-12-02 22:09:55 +02:00
|
|
|
{IWL_PCI_DEVICE(0x3165, 0x4410, iwl3165_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x3165, 0x4510, iwl3165_2ac_cfg)},
|
2015-03-19 12:46:06 +02:00
|
|
|
{IWL_PCI_DEVICE(0x3165, 0x4110, iwl3165_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x3166, 0x4310, iwl3165_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x3166, 0x4210, iwl3165_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x3165, 0x8010, iwl3165_2ac_cfg)},
|
2015-06-22 13:44:05 +03:00
|
|
|
{IWL_PCI_DEVICE(0x3165, 0x8110, iwl3165_2ac_cfg)},
|
2014-09-08 08:57:05 +03:00
|
|
|
|
2015-11-01 15:07:48 +02:00
|
|
|
/* 3168 Series */
|
2016-01-21 11:18:34 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24FB, 0x2010, iwl3168_2ac_cfg)},
|
2015-11-01 15:07:48 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24FB, 0x2110, iwl3168_2ac_cfg)},
|
2016-01-21 11:18:34 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24FB, 0x2050, iwl3168_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FB, 0x2150, iwl3168_2ac_cfg)},
|
2015-11-01 15:07:48 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24FB, 0x0000, iwl3168_2ac_cfg)},
|
|
|
|
|
2013-10-08 08:03:07 +02:00
|
|
|
/* 7265 Series */
|
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5010, iwl7265_2ac_cfg)},
|
2013-11-19 03:48:19 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5110, iwl7265_2ac_cfg)},
|
2014-01-23 01:19:33 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5100, iwl7265_2ac_cfg)},
|
2013-11-19 03:48:19 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095B, 0x5310, iwl7265_2ac_cfg)},
|
2014-03-04 14:47:39 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095B, 0x5302, iwl7265_n_cfg)},
|
2013-11-19 03:48:19 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095B, 0x5210, iwl7265_2ac_cfg)},
|
2015-12-17 14:17:00 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5C10, iwl7265_2ac_cfg)},
|
2013-12-19 05:07:21 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5012, iwl7265_2ac_cfg)},
|
2014-03-04 14:47:39 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5412, iwl7265_2ac_cfg)},
|
2013-11-19 03:48:19 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5410, iwl7265_2ac_cfg)},
|
2014-05-25 16:31:58 +03:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5510, iwl7265_2ac_cfg)},
|
2013-12-19 05:07:21 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5400, iwl7265_2ac_cfg)},
|
2013-11-19 03:48:19 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x1010, iwl7265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5000, iwl7265_2n_cfg)},
|
2014-01-23 01:19:33 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x500A, iwl7265_2n_cfg)},
|
2013-11-19 03:48:19 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095B, 0x5200, iwl7265_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5002, iwl7265_n_cfg)},
|
2014-04-02 14:04:20 +03:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5102, iwl7265_n_cfg)},
|
2013-11-19 03:48:19 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095B, 0x5202, iwl7265_n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x9010, iwl7265_2ac_cfg)},
|
2014-01-23 01:19:33 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x9012, iwl7265_2ac_cfg)},
|
2014-09-08 08:57:05 +03:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x900A, iwl7265_2ac_cfg)},
|
2013-12-19 05:07:21 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x9110, iwl7265_2ac_cfg)},
|
2014-01-23 01:19:33 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x9112, iwl7265_2ac_cfg)},
|
2015-12-17 14:17:00 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095B, 0x9210, iwl7265_2ac_cfg)},
|
2014-05-25 16:31:58 +03:00
|
|
|
{IWL_PCI_DEVICE(0x095B, 0x9200, iwl7265_2ac_cfg)},
|
2013-12-19 05:07:21 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x9510, iwl7265_2ac_cfg)},
|
2015-12-17 14:17:00 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095B, 0x9310, iwl7265_2ac_cfg)},
|
2013-11-19 03:48:19 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x9410, iwl7265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5020, iwl7265_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x502A, iwl7265_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5420, iwl7265_2n_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5090, iwl7265_2ac_cfg)},
|
2013-12-19 05:07:21 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5190, iwl7265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5590, iwl7265_2ac_cfg)},
|
2013-11-19 03:48:19 +02:00
|
|
|
{IWL_PCI_DEVICE(0x095B, 0x5290, iwl7265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5490, iwl7265_2ac_cfg)},
|
2015-09-22 09:44:39 +03:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x5F10, iwl7265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095B, 0x5212, iwl7265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095B, 0x520A, iwl7265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x9000, iwl7265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x9400, iwl7265_2ac_cfg)},
|
2017-08-16 08:47:38 +03:00
|
|
|
{IWL_PCI_DEVICE(0x095A, 0x9E10, iwl7265_2ac_cfg)},
|
2013-11-20 07:28:58 +02:00
|
|
|
|
|
|
|
/* 8000 Series */
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0010, iwl8260_2ac_cfg)},
|
2015-03-04 16:26:45 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x1010, iwl8260_2ac_cfg)},
|
2016-05-23 09:58:17 +03:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x10B0, iwl8260_2ac_cfg)},
|
iwlwifi: Add new PCI IDs for the 8260 series
Add some new PCI IDs for the 8260 series which were missing.
The following sub-system IDs were added:
0x0130, 0x1130, 0x0132, 0x1132, 0x1150, 0x8110, 0x9110, 0x8130,
0x9130, 0x8132, 0x9132, 0x8150, 0x9150, 0x0044, 0x0930
CC: <stable@vger.kernel.org> [4.1+]
Signed-off-by: Oren Givon <oren.givon@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
2015-10-28 12:32:20 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0130, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x1130, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0132, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x1132, iwl8260_2ac_cfg)},
|
2015-03-09 11:25:59 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0110, iwl8260_2ac_cfg)},
|
iwlwifi: Add new PCI IDs for the 8260 series
Add some new PCI IDs for the 8260 series which were missing.
The following sub-system IDs were added:
0x0130, 0x1130, 0x0132, 0x1132, 0x1150, 0x8110, 0x9110, 0x8130,
0x9130, 0x8132, 0x9132, 0x8150, 0x9150, 0x0044, 0x0930
CC: <stable@vger.kernel.org> [4.1+]
Signed-off-by: Oren Givon <oren.givon@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
2015-10-28 12:32:20 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x01F0, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0012, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x1012, iwl8260_2ac_cfg)},
|
2015-03-09 11:25:59 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x1110, iwl8260_2ac_cfg)},
|
2015-03-04 16:26:45 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0050, iwl8260_2ac_cfg)},
|
2015-03-09 11:25:59 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0250, iwl8260_2ac_cfg)},
|
2015-03-04 16:26:45 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x1050, iwl8260_2ac_cfg)},
|
2015-03-09 11:25:59 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0150, iwl8260_2ac_cfg)},
|
iwlwifi: Add new PCI IDs for the 8260 series
Add some new PCI IDs for the 8260 series which were missing.
The following sub-system IDs were added:
0x0130, 0x1130, 0x0132, 0x1132, 0x1150, 0x8110, 0x9110, 0x8130,
0x9130, 0x8132, 0x9132, 0x8150, 0x9150, 0x0044, 0x0930
CC: <stable@vger.kernel.org> [4.1+]
Signed-off-by: Oren Givon <oren.givon@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
2015-10-28 12:32:20 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x1150, iwl8260_2ac_cfg)},
|
2013-11-20 07:28:58 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F4, 0x0030, iwl8260_2ac_cfg)},
|
2015-03-04 16:26:45 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F4, 0x1030, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0xC010, iwl8260_2ac_cfg)},
|
2015-06-22 13:44:05 +03:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0xC110, iwl8260_2ac_cfg)},
|
2015-03-04 16:26:45 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0xD010, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0xC050, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0xD050, iwl8260_2ac_cfg)},
|
2016-05-23 09:58:17 +03:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0xD0B0, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0xB0B0, iwl8260_2ac_cfg)},
|
2015-03-04 16:26:45 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x8010, iwl8260_2ac_cfg)},
|
iwlwifi: Add new PCI IDs for the 8260 series
Add some new PCI IDs for the 8260 series which were missing.
The following sub-system IDs were added:
0x0130, 0x1130, 0x0132, 0x1132, 0x1150, 0x8110, 0x9110, 0x8130,
0x9130, 0x8132, 0x9132, 0x8150, 0x9150, 0x0044, 0x0930
CC: <stable@vger.kernel.org> [4.1+]
Signed-off-by: Oren Givon <oren.givon@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
2015-10-28 12:32:20 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x8110, iwl8260_2ac_cfg)},
|
2015-03-04 16:26:45 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x9010, iwl8260_2ac_cfg)},
|
iwlwifi: Add new PCI IDs for the 8260 series
Add some new PCI IDs for the 8260 series which were missing.
The following sub-system IDs were added:
0x0130, 0x1130, 0x0132, 0x1132, 0x1150, 0x8110, 0x9110, 0x8130,
0x9130, 0x8132, 0x9132, 0x8150, 0x9150, 0x0044, 0x0930
CC: <stable@vger.kernel.org> [4.1+]
Signed-off-by: Oren Givon <oren.givon@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
2015-10-28 12:32:20 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x9110, iwl8260_2ac_cfg)},
|
2015-03-04 16:26:45 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F4, 0x8030, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F4, 0x9030, iwl8260_2ac_cfg)},
|
2017-10-24 17:36:43 +03:00
|
|
|
{IWL_PCI_DEVICE(0x24F4, 0xC030, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F4, 0xD030, iwl8260_2ac_cfg)},
|
iwlwifi: Add new PCI IDs for the 8260 series
Add some new PCI IDs for the 8260 series which were missing.
The following sub-system IDs were added:
0x0130, 0x1130, 0x0132, 0x1132, 0x1150, 0x8110, 0x9110, 0x8130,
0x9130, 0x8132, 0x9132, 0x8150, 0x9150, 0x0044, 0x0930
CC: <stable@vger.kernel.org> [4.1+]
Signed-off-by: Oren Givon <oren.givon@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
2015-10-28 12:32:20 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x8130, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x9130, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x8132, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x9132, iwl8260_2ac_cfg)},
|
2015-03-04 16:26:45 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x8050, iwl8260_2ac_cfg)},
|
iwlwifi: Add new PCI IDs for the 8260 series
Add some new PCI IDs for the 8260 series which were missing.
The following sub-system IDs were added:
0x0130, 0x1130, 0x0132, 0x1132, 0x1150, 0x8110, 0x9110, 0x8130,
0x9130, 0x8132, 0x9132, 0x8150, 0x9150, 0x0044, 0x0930
CC: <stable@vger.kernel.org> [4.1+]
Signed-off-by: Oren Givon <oren.givon@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
2015-10-28 12:32:20 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x8150, iwl8260_2ac_cfg)},
|
2015-03-04 16:26:45 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x9050, iwl8260_2ac_cfg)},
|
iwlwifi: Add new PCI IDs for the 8260 series
Add some new PCI IDs for the 8260 series which were missing.
The following sub-system IDs were added:
0x0130, 0x1130, 0x0132, 0x1132, 0x1150, 0x8110, 0x9110, 0x8130,
0x9130, 0x8132, 0x9132, 0x8150, 0x9150, 0x0044, 0x0930
CC: <stable@vger.kernel.org> [4.1+]
Signed-off-by: Oren Givon <oren.givon@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
2015-10-28 12:32:20 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x9150, iwl8260_2ac_cfg)},
|
2015-03-04 16:26:45 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0004, iwl8260_2n_cfg)},
|
iwlwifi: Add new PCI IDs for the 8260 series
Add some new PCI IDs for the 8260 series which were missing.
The following sub-system IDs were added:
0x0130, 0x1130, 0x0132, 0x1132, 0x1150, 0x8110, 0x9110, 0x8130,
0x9130, 0x8132, 0x9132, 0x8150, 0x9150, 0x0044, 0x0930
CC: <stable@vger.kernel.org> [4.1+]
Signed-off-by: Oren Givon <oren.givon@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
2015-10-28 12:32:20 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0044, iwl8260_2n_cfg)},
|
2014-12-23 10:39:48 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F5, 0x0010, iwl4165_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F6, 0x0030, iwl4165_2ac_cfg)},
|
2015-03-04 16:26:45 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0810, iwl8260_2ac_cfg)},
|
2015-03-09 11:25:59 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0910, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0850, iwl8260_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0950, iwl8260_2ac_cfg)},
|
iwlwifi: Add new PCI IDs for the 8260 series
Add some new PCI IDs for the 8260 series which were missing.
The following sub-system IDs were added:
0x0130, 0x1130, 0x0132, 0x1132, 0x1150, 0x8110, 0x9110, 0x8130,
0x9130, 0x8132, 0x9132, 0x8150, 0x9150, 0x0044, 0x0930
CC: <stable@vger.kernel.org> [4.1+]
Signed-off-by: Oren Givon <oren.givon@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
2015-10-28 12:32:20 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0930, iwl8260_2ac_cfg)},
|
2015-12-17 13:44:06 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x0000, iwl8265_2ac_cfg)},
|
2017-10-24 17:36:43 +03:00
|
|
|
{IWL_PCI_DEVICE(0x24F3, 0x4010, iwl8260_2ac_cfg)},
|
2015-11-01 15:27:58 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x0010, iwl8265_2ac_cfg)},
|
2016-03-24 10:20:28 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x0110, iwl8265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x1110, iwl8265_2ac_cfg)},
|
2016-05-23 09:58:17 +03:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x1130, iwl8265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x0130, iwl8265_2ac_cfg)},
|
2016-03-24 10:20:28 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x1010, iwl8265_2ac_cfg)},
|
2016-08-25 13:15:24 +03:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x10D0, iwl8265_2ac_cfg)},
|
2016-03-24 10:20:28 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x0050, iwl8265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x0150, iwl8265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x9010, iwl8265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x8110, iwl8265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x8050, iwl8265_2ac_cfg)},
|
2015-12-17 13:44:06 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x8010, iwl8265_2ac_cfg)},
|
2016-01-21 11:11:11 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x0810, iwl8265_2ac_cfg)},
|
2016-03-24 10:20:28 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x9110, iwl8265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x8130, iwl8265_2ac_cfg)},
|
2016-05-23 09:58:17 +03:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x0910, iwl8265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x0930, iwl8265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x0950, iwl8265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x0850, iwl8265_2ac_cfg)},
|
2017-02-12 11:08:08 +02:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x1014, iwl8265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x3E02, iwl8275_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x3E01, iwl8275_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x1012, iwl8275_2ac_cfg)},
|
2016-07-07 09:11:56 +03:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x0012, iwl8275_2ac_cfg)},
|
2017-10-24 17:38:12 +03:00
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x0014, iwl8265_2ac_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x24FD, 0x9074, iwl8265_2ac_cfg)},
|
2015-06-01 08:27:17 +03:00
|
|
|
|
|
|
|
/* 9000 Series */
|
2019-11-04 21:02:47 +02:00
|
|
|
{IWL_PCI_DEVICE(0x2526, PCI_ANY_ID, iwl9000_trans_cfg)},
|
2020-10-08 18:09:49 +03:00
|
|
|
{IWL_PCI_DEVICE(0x271B, PCI_ANY_ID, iwl9000_trans_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x271C, PCI_ANY_ID, iwl9000_trans_cfg)},
|
2020-10-08 18:12:38 +03:00
|
|
|
{IWL_PCI_DEVICE(0x30DC, PCI_ANY_ID, iwl9560_long_latency_trans_cfg)},
|
2019-11-04 21:02:47 +02:00
|
|
|
{IWL_PCI_DEVICE(0x31DC, PCI_ANY_ID, iwl9560_shared_clk_trans_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x9DF0, PCI_ANY_ID, iwl9560_trans_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0xA370, PCI_ANY_ID, iwl9560_trans_cfg)},
|
|
|
|
|
|
|
|
/* Qu devices */
|
|
|
|
{IWL_PCI_DEVICE(0x02F0, PCI_ANY_ID, iwl_qu_trans_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x06F0, PCI_ANY_ID, iwl_qu_trans_cfg)},
|
2020-04-18 11:08:55 +03:00
|
|
|
|
|
|
|
{IWL_PCI_DEVICE(0x34F0, PCI_ANY_ID, iwl_qu_medium_latency_trans_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x3DF0, PCI_ANY_ID, iwl_qu_medium_latency_trans_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x4DF0, PCI_ANY_ID, iwl_qu_medium_latency_trans_cfg)},
|
2019-11-04 22:51:54 +02:00
|
|
|
|
|
|
|
{IWL_PCI_DEVICE(0x43F0, PCI_ANY_ID, iwl_qu_long_latency_trans_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0xA0F0, PCI_ANY_ID, iwl_qu_long_latency_trans_cfg)},
|
2019-10-08 13:21:02 +03:00
|
|
|
|
2020-03-09 09:16:19 +02:00
|
|
|
{IWL_PCI_DEVICE(0x2723, PCI_ANY_ID, iwl_ax200_trans_cfg)},
|
|
|
|
|
2021-02-05 11:06:35 +02:00
|
|
|
/* So devices */
|
|
|
|
{IWL_PCI_DEVICE(0x2725, PCI_ANY_ID, iwl_so_trans_cfg)},
|
2022-03-04 13:21:22 +02:00
|
|
|
{IWL_PCI_DEVICE(0x7A70, PCI_ANY_ID, iwl_so_long_latency_imr_trans_cfg)},
|
2021-02-05 11:06:35 +02:00
|
|
|
{IWL_PCI_DEVICE(0x7AF0, PCI_ANY_ID, iwl_so_trans_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x51F0, PCI_ANY_ID, iwl_so_long_latency_trans_cfg)},
|
2022-03-04 13:21:22 +02:00
|
|
|
{IWL_PCI_DEVICE(0x51F1, PCI_ANY_ID, iwl_so_long_latency_imr_trans_cfg)},
|
2021-02-05 11:06:35 +02:00
|
|
|
{IWL_PCI_DEVICE(0x54F0, PCI_ANY_ID, iwl_so_long_latency_trans_cfg)},
|
2022-02-10 18:22:28 +02:00
|
|
|
{IWL_PCI_DEVICE(0x7F70, PCI_ANY_ID, iwl_so_trans_cfg)},
|
2018-11-19 16:44:05 +02:00
|
|
|
|
2020-09-24 16:23:38 +03:00
|
|
|
/* Ma devices */
|
|
|
|
{IWL_PCI_DEVICE(0x2729, PCI_ANY_ID, iwl_ma_trans_cfg)},
|
2021-02-10 13:56:37 +02:00
|
|
|
{IWL_PCI_DEVICE(0x7E40, PCI_ANY_ID, iwl_ma_trans_cfg)},
|
2020-09-24 16:23:38 +03:00
|
|
|
|
2021-03-30 16:24:53 +03:00
|
|
|
/* Bz devices */
|
|
|
|
{IWL_PCI_DEVICE(0x2727, PCI_ANY_ID, iwl_bz_trans_cfg)},
|
2024-01-29 21:22:00 +02:00
|
|
|
{IWL_PCI_DEVICE(0x272D, PCI_ANY_ID, iwl_bz_trans_cfg)},
|
2023-04-14 13:11:53 +03:00
|
|
|
{IWL_PCI_DEVICE(0x272b, PCI_ANY_ID, iwl_bz_trans_cfg)},
|
2022-01-30 11:52:55 +02:00
|
|
|
{IWL_PCI_DEVICE(0xA840, PCI_ANY_ID, iwl_bz_trans_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x7740, PCI_ANY_ID, iwl_bz_trans_cfg)},
|
2024-04-15 11:54:39 +03:00
|
|
|
{IWL_PCI_DEVICE(0x4D40, PCI_ANY_ID, iwl_bz_trans_cfg)},
|
2023-06-21 13:12:07 +03:00
|
|
|
|
|
|
|
/* Sc devices */
|
|
|
|
{IWL_PCI_DEVICE(0xE440, PCI_ANY_ID, iwl_sc_trans_cfg)},
|
2024-02-06 18:02:08 +02:00
|
|
|
{IWL_PCI_DEVICE(0xE340, PCI_ANY_ID, iwl_sc_trans_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0xD340, PCI_ANY_ID, iwl_sc_trans_cfg)},
|
|
|
|
{IWL_PCI_DEVICE(0x6E70, PCI_ANY_ID, iwl_sc_trans_cfg)},
|
2013-06-10 16:12:52 +02:00
|
|
|
#endif /* CONFIG_IWLMVM */
|
2013-01-24 13:52:01 +01:00
|
|
|
|
2011-05-24 11:39:02 +03:00
|
|
|
{0}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
|
2024-03-19 10:10:16 +02:00
|
|
|
EXPORT_SYMBOL_IF_IWLWIFI_KUNIT(iwl_hw_card_ids);
|
2011-05-24 11:39:02 +03:00
|
|
|
|
2019-11-04 17:29:55 +02:00
|
|
|
#define _IWL_DEV_INFO(_device, _subdevice, _mac_type, _mac_step, _rf_type, \
|
2023-06-21 13:12:14 +03:00
|
|
|
_rf_id, _rf_step, _no_160, _cores, _cdb, _cfg, _name) \
|
2023-04-14 13:11:52 +03:00
|
|
|
{ .device = (_device), .subdevice = (_subdevice), .cfg = &(_cfg), \
|
|
|
|
.name = _name, .mac_type = _mac_type, .rf_type = _rf_type, .rf_step = _rf_step, \
|
|
|
|
.no_160 = _no_160, .cores = _cores, .rf_id = _rf_id, \
|
2023-06-21 13:12:14 +03:00
|
|
|
.mac_step = _mac_step, .cdb = _cdb, .jacket = IWL_CFG_ANY }
|
2020-03-09 09:16:09 +02:00
|
|
|
|
|
|
|
#define IWL_DEV_INFO(_device, _subdevice, _cfg, _name) \
|
2023-06-21 13:12:14 +03:00
|
|
|
_IWL_DEV_INFO(_device, _subdevice, IWL_CFG_ANY, IWL_CFG_ANY, \
|
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY, \
|
|
|
|
IWL_CFG_ANY, _cfg, _name)
|
2019-10-10 16:30:11 +03:00
|
|
|
|
2024-01-23 20:08:09 +02:00
|
|
|
VISIBLE_IF_IWLWIFI_KUNIT const struct iwl_dev_info iwl_dev_info_table[] = {
|
2019-10-10 16:30:11 +03:00
|
|
|
#if IS_ENABLED(CONFIG_IWLMVM)
|
2020-03-09 09:16:19 +02:00
|
|
|
/* 9000 */
|
2020-03-09 09:16:08 +02:00
|
|
|
IWL_DEV_INFO(0x2526, 0x1550, iwl9260_2ac_cfg, iwl9260_killer_1550_name),
|
|
|
|
IWL_DEV_INFO(0x2526, 0x1551, iwl9560_2ac_cfg_soc, iwl9560_killer_1550s_name),
|
|
|
|
IWL_DEV_INFO(0x2526, 0x1552, iwl9560_2ac_cfg_soc, iwl9560_killer_1550i_name),
|
2020-03-09 09:16:16 +02:00
|
|
|
IWL_DEV_INFO(0x30DC, 0x1551, iwl9560_2ac_cfg_soc, iwl9560_killer_1550s_name),
|
|
|
|
IWL_DEV_INFO(0x30DC, 0x1552, iwl9560_2ac_cfg_soc, iwl9560_killer_1550i_name),
|
2019-11-04 12:31:22 +02:00
|
|
|
IWL_DEV_INFO(0x31DC, 0x1551, iwl9560_2ac_cfg_soc, iwl9560_killer_1550s_name),
|
|
|
|
IWL_DEV_INFO(0x31DC, 0x1552, iwl9560_2ac_cfg_soc, iwl9560_killer_1550i_name),
|
2020-07-14 11:19:11 +02:00
|
|
|
IWL_DEV_INFO(0xA370, 0x1551, iwl9560_2ac_cfg_soc, iwl9560_killer_1550s_name),
|
|
|
|
IWL_DEV_INFO(0xA370, 0x1552, iwl9560_2ac_cfg_soc, iwl9560_killer_1550i_name),
|
2021-10-17 16:59:47 +03:00
|
|
|
IWL_DEV_INFO(0x54F0, 0x1551, iwl9560_2ac_cfg_soc, iwl9560_killer_1550s_160_name),
|
|
|
|
IWL_DEV_INFO(0x54F0, 0x1552, iwl9560_2ac_cfg_soc, iwl9560_killer_1550i_name),
|
2021-06-21 10:37:38 +03:00
|
|
|
IWL_DEV_INFO(0x51F0, 0x1552, iwl9560_2ac_cfg_soc, iwl9560_killer_1550s_160_name),
|
|
|
|
IWL_DEV_INFO(0x51F0, 0x1551, iwl9560_2ac_cfg_soc, iwl9560_killer_1550i_160_name),
|
2021-10-17 16:59:47 +03:00
|
|
|
IWL_DEV_INFO(0x51F0, 0x1691, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690s_name),
|
|
|
|
IWL_DEV_INFO(0x51F0, 0x1692, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690i_name),
|
2023-06-20 13:03:59 +03:00
|
|
|
IWL_DEV_INFO(0x51F1, 0x1692, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690i_name),
|
2021-10-17 16:59:47 +03:00
|
|
|
IWL_DEV_INFO(0x54F0, 0x1691, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690s_name),
|
|
|
|
IWL_DEV_INFO(0x54F0, 0x1692, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690i_name),
|
|
|
|
IWL_DEV_INFO(0x7A70, 0x1691, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690s_name),
|
|
|
|
IWL_DEV_INFO(0x7A70, 0x1692, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690i_name),
|
2023-06-19 17:02:34 +02:00
|
|
|
IWL_DEV_INFO(0x7AF0, 0x1691, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690s_name),
|
|
|
|
IWL_DEV_INFO(0x7AF0, 0x1692, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690i_name),
|
2020-03-09 09:16:09 +02:00
|
|
|
|
2020-03-09 09:16:14 +02:00
|
|
|
IWL_DEV_INFO(0x271C, 0x0214, iwl9260_2ac_cfg, iwl9260_1_name),
|
2023-06-21 13:12:17 +03:00
|
|
|
IWL_DEV_INFO(0x7E40, 0x1691, iwl_cfg_ma, iwl_ax411_killer_1690s_name),
|
|
|
|
IWL_DEV_INFO(0x7E40, 0x1692, iwl_cfg_ma, iwl_ax411_killer_1690i_name),
|
2020-03-09 09:16:14 +02:00
|
|
|
|
2019-11-04 21:02:47 +02:00
|
|
|
/* AX200 */
|
2021-10-24 16:54:57 +03:00
|
|
|
IWL_DEV_INFO(0x2723, IWL_CFG_ANY, iwl_ax200_cfg_cc, iwl_ax200_name),
|
2019-11-04 21:02:47 +02:00
|
|
|
IWL_DEV_INFO(0x2723, 0x1653, iwl_ax200_cfg_cc, iwl_ax200_killer_1650w_name),
|
|
|
|
IWL_DEV_INFO(0x2723, 0x1654, iwl_ax200_cfg_cc, iwl_ax200_killer_1650x_name),
|
|
|
|
|
2020-04-24 19:47:04 +03:00
|
|
|
/* Qu with Hr */
|
2019-11-04 21:02:47 +02:00
|
|
|
IWL_DEV_INFO(0x43F0, 0x0070, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x43F0, 0x0074, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x43F0, 0x0078, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x43F0, 0x007C, iwl_ax201_cfg_qu_hr, NULL),
|
2021-09-24 15:21:54 +03:00
|
|
|
IWL_DEV_INFO(0x43F0, 0x1651, killer1650s_2ax_cfg_qu_b0_hr_b0, iwl_ax201_killer_1650s_name),
|
|
|
|
IWL_DEV_INFO(0x43F0, 0x1652, killer1650i_2ax_cfg_qu_b0_hr_b0, iwl_ax201_killer_1650i_name),
|
2019-11-04 21:02:47 +02:00
|
|
|
IWL_DEV_INFO(0x43F0, 0x2074, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x43F0, 0x4070, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0xA0F0, 0x0070, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0xA0F0, 0x0074, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0xA0F0, 0x0078, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0xA0F0, 0x007C, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0xA0F0, 0x0A10, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0xA0F0, 0x1651, killer1650s_2ax_cfg_qu_b0_hr_b0, NULL),
|
|
|
|
IWL_DEV_INFO(0xA0F0, 0x1652, killer1650i_2ax_cfg_qu_b0_hr_b0, NULL),
|
|
|
|
IWL_DEV_INFO(0xA0F0, 0x2074, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0xA0F0, 0x4070, iwl_ax201_cfg_qu_hr, NULL),
|
2021-07-02 17:31:53 -05:00
|
|
|
IWL_DEV_INFO(0xA0F0, 0x6074, iwl_ax201_cfg_qu_hr, NULL),
|
2019-11-04 21:02:47 +02:00
|
|
|
IWL_DEV_INFO(0x02F0, 0x0070, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x02F0, 0x0074, iwl_ax201_cfg_quz_hr, NULL),
|
2020-10-08 18:09:42 +03:00
|
|
|
IWL_DEV_INFO(0x02F0, 0x6074, iwl_ax201_cfg_quz_hr, NULL),
|
2019-11-04 21:02:47 +02:00
|
|
|
IWL_DEV_INFO(0x02F0, 0x0078, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x02F0, 0x007C, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x02F0, 0x0310, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x02F0, 0x1651, iwl_ax1650s_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x02F0, 0x1652, iwl_ax1650i_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x02F0, 0x2074, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x02F0, 0x4070, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x06F0, 0x0070, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x06F0, 0x0074, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x06F0, 0x0078, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x06F0, 0x007C, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x06F0, 0x0310, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x06F0, 0x1651, iwl_ax1650s_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x06F0, 0x1652, iwl_ax1650i_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x06F0, 0x2074, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x06F0, 0x4070, iwl_ax201_cfg_quz_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x34F0, 0x0070, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x34F0, 0x0074, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x34F0, 0x0078, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x34F0, 0x007C, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x34F0, 0x0310, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x34F0, 0x1651, killer1650s_2ax_cfg_qu_b0_hr_b0, NULL),
|
|
|
|
IWL_DEV_INFO(0x34F0, 0x1652, killer1650i_2ax_cfg_qu_b0_hr_b0, NULL),
|
|
|
|
IWL_DEV_INFO(0x34F0, 0x2074, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x34F0, 0x4070, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
|
|
|
|
IWL_DEV_INFO(0x3DF0, 0x0070, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x3DF0, 0x0074, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x3DF0, 0x0078, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x3DF0, 0x007C, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x3DF0, 0x0310, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x3DF0, 0x1651, killer1650s_2ax_cfg_qu_b0_hr_b0, NULL),
|
|
|
|
IWL_DEV_INFO(0x3DF0, 0x1652, killer1650i_2ax_cfg_qu_b0_hr_b0, NULL),
|
|
|
|
IWL_DEV_INFO(0x3DF0, 0x2074, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x3DF0, 0x4070, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
|
2020-04-18 11:08:52 +03:00
|
|
|
IWL_DEV_INFO(0x4DF0, 0x0070, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x4DF0, 0x0074, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x4DF0, 0x0078, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x4DF0, 0x007C, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x4DF0, 0x0310, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x4DF0, 0x1651, killer1650s_2ax_cfg_qu_b0_hr_b0, NULL),
|
|
|
|
IWL_DEV_INFO(0x4DF0, 0x1652, killer1650i_2ax_cfg_qu_b0_hr_b0, NULL),
|
|
|
|
IWL_DEV_INFO(0x4DF0, 0x2074, iwl_ax201_cfg_qu_hr, NULL),
|
|
|
|
IWL_DEV_INFO(0x4DF0, 0x4070, iwl_ax201_cfg_qu_hr, NULL),
|
2021-03-26 12:57:19 +02:00
|
|
|
IWL_DEV_INFO(0x4DF0, 0x6074, iwl_ax201_cfg_qu_hr, NULL),
|
2019-11-04 21:29:55 +02:00
|
|
|
|
2021-02-05 11:06:35 +02:00
|
|
|
/* So with HR */
|
|
|
|
IWL_DEV_INFO(0x2725, 0x0090, iwlax211_2ax_cfg_so_gf_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x2725, 0x0020, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
2021-02-10 13:56:26 +02:00
|
|
|
IWL_DEV_INFO(0x2725, 0x2020, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x2725, 0x0024, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
2021-02-05 11:06:35 +02:00
|
|
|
IWL_DEV_INFO(0x2725, 0x0310, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x2725, 0x0510, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x2725, 0x0A10, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
2021-02-10 13:56:26 +02:00
|
|
|
IWL_DEV_INFO(0x2725, 0xE020, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x2725, 0xE024, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x2725, 0x4020, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x2725, 0x6020, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x2725, 0x6024, iwlax210_2ax_cfg_ty_gf_a0, NULL),
|
2021-03-31 12:14:44 +03:00
|
|
|
IWL_DEV_INFO(0x2725, 0x1673, iwlax210_2ax_cfg_ty_gf_a0, iwl_ax210_killer_1675w_name),
|
|
|
|
IWL_DEV_INFO(0x2725, 0x1674, iwlax210_2ax_cfg_ty_gf_a0, iwl_ax210_killer_1675x_name),
|
2021-02-05 11:06:35 +02:00
|
|
|
IWL_DEV_INFO(0x7A70, 0x0090, iwlax211_2ax_cfg_so_gf_a0_long, NULL),
|
|
|
|
IWL_DEV_INFO(0x7A70, 0x0098, iwlax211_2ax_cfg_so_gf_a0_long, NULL),
|
|
|
|
IWL_DEV_INFO(0x7A70, 0x00B0, iwlax411_2ax_cfg_so_gf4_a0_long, NULL),
|
|
|
|
IWL_DEV_INFO(0x7A70, 0x0310, iwlax211_2ax_cfg_so_gf_a0_long, NULL),
|
|
|
|
IWL_DEV_INFO(0x7A70, 0x0510, iwlax211_2ax_cfg_so_gf_a0_long, NULL),
|
|
|
|
IWL_DEV_INFO(0x7A70, 0x0A10, iwlax211_2ax_cfg_so_gf_a0_long, NULL),
|
|
|
|
IWL_DEV_INFO(0x7AF0, 0x0090, iwlax211_2ax_cfg_so_gf_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x7AF0, 0x0098, iwlax211_2ax_cfg_so_gf_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x7AF0, 0x00B0, iwlax411_2ax_cfg_so_gf4_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x7AF0, 0x0310, iwlax211_2ax_cfg_so_gf_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x7AF0, 0x0510, iwlax211_2ax_cfg_so_gf_a0, NULL),
|
|
|
|
IWL_DEV_INFO(0x7AF0, 0x0A10, iwlax211_2ax_cfg_so_gf_a0, NULL),
|
|
|
|
|
2021-10-17 16:59:47 +03:00
|
|
|
/* So with JF */
|
|
|
|
IWL_DEV_INFO(0x7A70, 0x1551, iwl9560_2ac_cfg_soc, iwl9560_killer_1550s_160_name),
|
|
|
|
IWL_DEV_INFO(0x7A70, 0x1552, iwl9560_2ac_cfg_soc, iwl9560_killer_1550i_160_name),
|
|
|
|
IWL_DEV_INFO(0x7AF0, 0x1551, iwl9560_2ac_cfg_soc, iwl9560_killer_1550s_160_name),
|
|
|
|
IWL_DEV_INFO(0x7AF0, 0x1552, iwl9560_2ac_cfg_soc, iwl9560_killer_1550i_160_name),
|
|
|
|
|
2021-12-19 13:28:25 +02:00
|
|
|
/* SO with GF2 */
|
|
|
|
IWL_DEV_INFO(0x2726, 0x1671, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675s_name),
|
|
|
|
IWL_DEV_INFO(0x2726, 0x1672, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675i_name),
|
|
|
|
IWL_DEV_INFO(0x51F0, 0x1671, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675s_name),
|
|
|
|
IWL_DEV_INFO(0x51F0, 0x1672, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675i_name),
|
2023-06-21 13:12:20 +03:00
|
|
|
IWL_DEV_INFO(0x51F1, 0x1671, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675s_name),
|
|
|
|
IWL_DEV_INFO(0x51F1, 0x1672, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675i_name),
|
2021-12-19 13:28:25 +02:00
|
|
|
IWL_DEV_INFO(0x54F0, 0x1671, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675s_name),
|
|
|
|
IWL_DEV_INFO(0x54F0, 0x1672, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675i_name),
|
|
|
|
IWL_DEV_INFO(0x7A70, 0x1671, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675s_name),
|
|
|
|
IWL_DEV_INFO(0x7A70, 0x1672, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675i_name),
|
|
|
|
IWL_DEV_INFO(0x7AF0, 0x1671, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675s_name),
|
|
|
|
IWL_DEV_INFO(0x7AF0, 0x1672, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675i_name),
|
2022-02-10 18:22:28 +02:00
|
|
|
IWL_DEV_INFO(0x7F70, 0x1671, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675s_name),
|
|
|
|
IWL_DEV_INFO(0x7F70, 0x1672, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675i_name),
|
2021-12-19 13:28:25 +02:00
|
|
|
|
|
|
|
/* MA with GF2 */
|
2023-06-21 13:12:17 +03:00
|
|
|
IWL_DEV_INFO(0x7E40, 0x1671, iwl_cfg_ma, iwl_ax211_killer_1675s_name),
|
|
|
|
IWL_DEV_INFO(0x7E40, 0x1672, iwl_cfg_ma, iwl_ax211_killer_1675i_name),
|
2021-12-19 13:28:25 +02:00
|
|
|
|
2020-03-09 09:16:16 +02:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
2019-11-04 17:29:55 +02:00
|
|
|
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2020-03-09 09:16:16 +02:00
|
|
|
iwl9560_2ac_cfg_soc, iwl9461_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
2019-11-04 17:29:55 +02:00
|
|
|
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2020-03-09 09:16:16 +02:00
|
|
|
iwl9560_2ac_cfg_soc, iwl9461_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
2019-11-04 17:29:55 +02:00
|
|
|
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2020-03-09 09:16:16 +02:00
|
|
|
iwl9560_2ac_cfg_soc, iwl9462_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
2019-11-04 17:29:55 +02:00
|
|
|
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2020-03-09 09:16:16 +02:00
|
|
|
iwl9560_2ac_cfg_soc, iwl9462_name),
|
|
|
|
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
2019-11-04 17:29:55 +02:00
|
|
|
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2020-03-09 09:16:16 +02:00
|
|
|
iwl9560_2ac_cfg_soc, iwl9560_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
2019-11-04 17:29:55 +02:00
|
|
|
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2020-03-09 09:16:16 +02:00
|
|
|
iwl9560_2ac_cfg_soc, iwl9560_name),
|
|
|
|
|
2020-03-09 09:16:11 +02:00
|
|
|
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
2019-11-04 17:29:55 +02:00
|
|
|
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_TH, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT_GNSS, IWL_CFG_NO_CDB,
|
2020-03-09 09:16:10 +02:00
|
|
|
iwl9260_2ac_cfg, iwl9270_160_name),
|
|
|
|
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
2019-11-04 17:29:55 +02:00
|
|
|
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_TH, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT_GNSS, IWL_CFG_NO_CDB,
|
2020-03-09 09:16:10 +02:00
|
|
|
iwl9260_2ac_cfg, iwl9270_name),
|
|
|
|
|
2020-03-09 09:16:13 +02:00
|
|
|
_IWL_DEV_INFO(0x271B, IWL_CFG_ANY,
|
2019-11-04 17:29:55 +02:00
|
|
|
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_TH1, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2020-03-09 09:16:13 +02:00
|
|
|
iwl9260_2ac_cfg, iwl9162_160_name),
|
|
|
|
_IWL_DEV_INFO(0x271B, IWL_CFG_ANY,
|
2019-11-04 17:29:55 +02:00
|
|
|
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_TH1, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2020-03-09 09:16:13 +02:00
|
|
|
iwl9260_2ac_cfg, iwl9162_name),
|
|
|
|
|
2020-03-09 09:16:10 +02:00
|
|
|
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
2019-11-04 17:29:55 +02:00
|
|
|
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_TH, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2020-03-09 09:16:09 +02:00
|
|
|
iwl9260_2ac_cfg, iwl9260_160_name),
|
|
|
|
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
|
2019-11-04 17:29:55 +02:00
|
|
|
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_TH, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2020-03-09 09:16:09 +02:00
|
|
|
iwl9260_2ac_cfg, iwl9260_name),
|
2020-03-09 09:16:19 +02:00
|
|
|
|
2020-04-24 19:47:04 +03:00
|
|
|
/* Qu with Jf */
|
2019-11-04 21:02:47 +02:00
|
|
|
/* Qu B step */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_b0_jf_b0_cfg, iwl9461_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_b0_jf_b0_cfg, iwl9461_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_b0_jf_b0_cfg, iwl9462_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_b0_jf_b0_cfg, iwl9462_name),
|
|
|
|
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_b0_jf_b0_cfg, iwl9560_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_b0_jf_b0_cfg, iwl9560_name),
|
|
|
|
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1551,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_b0_jf_b0_cfg, iwl9560_killer_1550s_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1552,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_b0_jf_b0_cfg, iwl9560_killer_1550i_name),
|
2020-03-09 09:16:19 +02:00
|
|
|
|
2019-11-04 21:02:47 +02:00
|
|
|
/* Qu C step */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_c0_jf_b0_cfg, iwl9461_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_c0_jf_b0_cfg, iwl9461_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_c0_jf_b0_cfg, iwl9462_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_c0_jf_b0_cfg, iwl9462_name),
|
|
|
|
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_c0_jf_b0_cfg, iwl9560_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_c0_jf_b0_cfg, iwl9560_name),
|
|
|
|
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1551,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_c0_jf_b0_cfg, iwl9560_killer_1550s_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1552,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_qu_c0_jf_b0_cfg, iwl9560_killer_1550i_name),
|
|
|
|
|
|
|
|
/* QuZ */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_quz_a0_jf_b0_cfg, iwl9461_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_quz_a0_jf_b0_cfg, iwl9461_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_quz_a0_jf_b0_cfg, iwl9462_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_quz_a0_jf_b0_cfg, iwl9462_name),
|
|
|
|
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_quz_a0_jf_b0_cfg, iwl9560_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_quz_a0_jf_b0_cfg, iwl9560_name),
|
|
|
|
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1551,
|
|
|
|
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_quz_a0_jf_b0_cfg, iwl9560_killer_1550s_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1552,
|
|
|
|
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl9560_quz_a0_jf_b0_cfg, iwl9560_killer_1550i_name),
|
2019-11-04 21:29:55 +02:00
|
|
|
|
2020-04-24 19:47:06 +03:00
|
|
|
/* Qu with Hr */
|
|
|
|
/* Qu B step */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2020-04-24 19:47:06 +03:00
|
|
|
iwl_qu_b0_hr1_b0, iwl_ax101_name),
|
2021-01-22 14:52:38 +02:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
2021-10-16 11:43:56 +03:00
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2021-01-22 14:52:38 +02:00
|
|
|
iwl_qu_b0_hr_b0, iwl_ax203_name),
|
2020-04-24 19:47:06 +03:00
|
|
|
|
|
|
|
/* Qu C step */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2020-04-24 19:47:06 +03:00
|
|
|
iwl_qu_c0_hr1_b0, iwl_ax101_name),
|
2021-01-22 14:52:38 +02:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2021-01-22 14:52:38 +02:00
|
|
|
iwl_qu_c0_hr_b0, iwl_ax203_name),
|
2021-12-04 17:49:40 +02:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2021-12-04 17:49:40 +02:00
|
|
|
iwl_qu_c0_hr_b0, iwl_ax201_name),
|
2020-04-24 19:47:06 +03:00
|
|
|
|
|
|
|
/* QuZ */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2020-04-24 19:47:06 +03:00
|
|
|
iwl_quz_a0_hr1_b0, iwl_ax101_name),
|
2021-02-06 13:01:10 +02:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QUZ, SILICON_B_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2021-02-06 13:01:10 +02:00
|
|
|
iwl_cfg_quz_a0_hr_b0, iwl_ax203_name),
|
2023-04-13 10:44:04 +03:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_QUZ, SILICON_B_STEP,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2023-04-13 10:44:04 +03:00
|
|
|
iwl_cfg_quz_a0_hr_b0, iwl_ax201_name),
|
2020-04-24 19:47:06 +03:00
|
|
|
|
2020-09-24 16:23:38 +03:00
|
|
|
/* Ma */
|
2021-02-10 14:29:24 +02:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:17 +03:00
|
|
|
IWL_CFG_MAC_TYPE_MA, IWL_CFG_ANY,
|
2023-04-18 12:28:04 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2023-06-21 13:12:17 +03:00
|
|
|
iwl_cfg_ma, iwl_ax201_name),
|
2023-04-18 12:28:04 +03:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:17 +03:00
|
|
|
IWL_CFG_MAC_TYPE_MA, IWL_CFG_ANY,
|
2023-04-18 12:28:04 +03:00
|
|
|
IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:17 +03:00
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
iwl_cfg_ma, iwl_ax211_name),
|
2023-04-18 12:28:04 +03:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:17 +03:00
|
|
|
IWL_CFG_MAC_TYPE_MA, IWL_CFG_ANY,
|
2023-04-18 12:28:04 +03:00
|
|
|
IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2023-06-21 13:12:17 +03:00
|
|
|
iwl_cfg_ma, iwl_ax231_name),
|
2020-12-09 23:16:45 +02:00
|
|
|
|
2021-02-06 13:01:10 +02:00
|
|
|
/* So with Hr */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2021-02-06 13:01:10 +02:00
|
|
|
iwl_cfg_so_a0_hr_a0, iwl_ax203_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2021-02-06 13:01:10 +02:00
|
|
|
iwl_cfg_so_a0_hr_a0, iwl_ax101_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2021-03-26 12:57:21 +02:00
|
|
|
iwl_cfg_so_a0_hr_a0, iwl_ax201_name),
|
|
|
|
|
|
|
|
/* So-F with Hr */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2021-03-26 12:57:21 +02:00
|
|
|
iwl_cfg_so_a0_hr_a0, iwl_ax203_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2021-03-26 12:57:21 +02:00
|
|
|
iwl_cfg_so_a0_hr_a0, iwl_ax101_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2021-03-26 12:57:21 +02:00
|
|
|
iwl_cfg_so_a0_hr_a0, iwl_ax201_name),
|
|
|
|
|
|
|
|
/* So-F with Gf */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2021-03-26 12:57:21 +02:00
|
|
|
iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_name),
|
2021-12-04 13:10:43 +02:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_CDB,
|
2021-12-04 13:10:43 +02:00
|
|
|
iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_name),
|
2020-09-24 16:23:38 +03:00
|
|
|
|
2021-03-30 16:24:53 +03:00
|
|
|
/* Bz */
|
2024-03-20 23:26:29 +02:00
|
|
|
/* FIXME: need to change the naming according to the actual CRF */
|
2021-03-30 16:24:53 +03:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_BZ, IWL_CFG_ANY,
|
2023-06-21 13:12:15 +03:00
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
|
2024-03-20 23:26:29 +02:00
|
|
|
iwl_cfg_bz, iwl_fm_name),
|
2021-12-04 08:35:47 +02:00
|
|
|
|
2024-03-20 23:26:30 +02:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_BZ_W, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
iwl_cfg_bz, iwl_fm_name),
|
|
|
|
|
2023-06-21 13:12:15 +03:00
|
|
|
/* Ga (Gl) */
|
2021-12-10 09:06:17 +02:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_GL, IWL_CFG_ANY,
|
2023-06-21 13:12:15 +03:00
|
|
|
IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, IWL_CFG_ANY,
|
2024-01-23 20:08:10 +02:00
|
|
|
IWL_CFG_320, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2024-03-20 23:26:29 +02:00
|
|
|
iwl_cfg_gl, iwl_gl_name),
|
2024-01-23 20:08:10 +02:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_GL, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_NO_320, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
|
|
|
iwl_cfg_gl, iwl_mtp_name),
|
2021-03-30 16:24:53 +03:00
|
|
|
|
2021-07-19 14:45:38 +02:00
|
|
|
/* SoF with JF2 */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2021-07-19 14:45:38 +02:00
|
|
|
iwlax210_2ax_cfg_so_jf_b0, iwl9560_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2021-07-19 14:45:38 +02:00
|
|
|
iwlax210_2ax_cfg_so_jf_b0, iwl9560_name),
|
|
|
|
|
|
|
|
/* SoF with JF */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2021-07-19 14:45:38 +02:00
|
|
|
iwlax210_2ax_cfg_so_jf_b0, iwl9461_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2021-07-19 14:45:38 +02:00
|
|
|
iwlax210_2ax_cfg_so_jf_b0, iwl9462_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2021-07-19 14:45:38 +02:00
|
|
|
iwlax210_2ax_cfg_so_jf_b0, iwl9461_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2021-07-19 14:45:38 +02:00
|
|
|
iwlax210_2ax_cfg_so_jf_b0, iwl9462_name),
|
|
|
|
|
2021-03-31 12:14:48 +03:00
|
|
|
/* So with GF */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
|
2021-07-19 14:45:39 +02:00
|
|
|
iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_name),
|
2021-12-04 13:10:43 +02:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_CDB,
|
2021-12-04 13:10:43 +02:00
|
|
|
iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_name),
|
2021-07-19 14:45:39 +02:00
|
|
|
|
|
|
|
/* So with JF2 */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2021-07-19 14:45:39 +02:00
|
|
|
iwlax210_2ax_cfg_so_jf_b0, iwl9560_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2021-07-19 14:45:39 +02:00
|
|
|
iwlax210_2ax_cfg_so_jf_b0, iwl9560_name),
|
|
|
|
|
|
|
|
/* So with JF */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2021-07-19 14:45:39 +02:00
|
|
|
iwlax210_2ax_cfg_so_jf_b0, iwl9461_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2021-07-19 14:45:39 +02:00
|
|
|
iwlax210_2ax_cfg_so_jf_b0, iwl9462_160_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2021-07-19 14:45:39 +02:00
|
|
|
iwlax210_2ax_cfg_so_jf_b0, iwl9461_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
|
2023-06-21 13:12:14 +03:00
|
|
|
IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
|
2022-01-29 13:16:17 +02:00
|
|
|
iwlax210_2ax_cfg_so_jf_b0, iwl9462_name),
|
|
|
|
|
2023-06-21 13:12:06 +03:00
|
|
|
/* Sc */
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
2023-06-21 13:12:16 +03:00
|
|
|
IWL_CFG_MAC_TYPE_SC, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
iwl_cfg_sc, iwl_sc_name),
|
2024-02-06 18:02:08 +02:00
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SC2, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
iwl_cfg_sc2, iwl_sc2_name),
|
|
|
|
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_MAC_TYPE_SC2F, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
|
|
|
|
iwl_cfg_sc2f, iwl_sc2f_name),
|
2019-10-10 16:30:11 +03:00
|
|
|
#endif /* CONFIG_IWLMVM */
|
|
|
|
};
|
2024-01-23 20:08:09 +02:00
|
|
|
EXPORT_SYMBOL_IF_IWLWIFI_KUNIT(iwl_dev_info_table);
|
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_IWLWIFI_KUNIT_TESTS)
|
|
|
|
const unsigned int iwl_dev_info_table_size = ARRAY_SIZE(iwl_dev_info_table);
|
|
|
|
EXPORT_SYMBOL_IF_IWLWIFI_KUNIT(iwl_dev_info_table_size);
|
|
|
|
#endif
|
2019-10-10 16:30:11 +03:00
|
|
|
|
2021-08-26 22:47:46 +03:00
|
|
|
/*
|
2022-12-05 10:35:43 +02:00
|
|
|
* Read rf id and cdb info from prph register and store it
|
2021-08-26 22:47:46 +03:00
|
|
|
*/
|
2023-12-07 04:50:13 +02:00
|
|
|
static void get_crf_id(struct iwl_trans *iwl_trans)
|
2021-08-26 22:47:46 +03:00
|
|
|
{
|
|
|
|
u32 sd_reg_ver_addr;
|
2022-12-05 10:35:43 +02:00
|
|
|
u32 val = 0;
|
2024-03-20 23:26:30 +02:00
|
|
|
u8 step;
|
2021-08-26 22:47:46 +03:00
|
|
|
|
2021-12-10 09:06:14 +02:00
|
|
|
if (iwl_trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
|
2021-08-26 22:47:46 +03:00
|
|
|
sd_reg_ver_addr = SD_REG_VER_GEN2;
|
2021-12-10 09:06:14 +02:00
|
|
|
else
|
2021-08-26 22:47:46 +03:00
|
|
|
sd_reg_ver_addr = SD_REG_VER;
|
|
|
|
|
|
|
|
/* Enable access to peripheral registers */
|
2021-12-10 09:06:14 +02:00
|
|
|
val = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG);
|
2023-09-26 11:07:17 +03:00
|
|
|
val |= WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK;
|
2021-12-10 09:06:14 +02:00
|
|
|
iwl_write_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG, val);
|
2021-08-26 22:47:46 +03:00
|
|
|
|
|
|
|
/* Read crf info */
|
2022-12-05 10:35:43 +02:00
|
|
|
iwl_trans->hw_crf_id = iwl_read_prph_no_grab(iwl_trans, sd_reg_ver_addr);
|
2021-08-26 22:47:46 +03:00
|
|
|
|
2023-04-14 13:11:52 +03:00
|
|
|
/* Read cnv info */
|
|
|
|
iwl_trans->hw_cnv_id =
|
|
|
|
iwl_read_prph_no_grab(iwl_trans, CNVI_AUX_MISC_CHIP);
|
|
|
|
|
2024-03-20 23:26:30 +02:00
|
|
|
/* For BZ-W, take B step also when A step is indicated */
|
|
|
|
if (CSR_HW_REV_TYPE(iwl_trans->hw_rev) == IWL_CFG_MAC_TYPE_BZ_W)
|
|
|
|
step = SILICON_B_STEP;
|
|
|
|
|
2024-02-05 00:06:09 +02:00
|
|
|
/* In BZ, the MAC step must be read from the CNVI aux register */
|
|
|
|
if (CSR_HW_REV_TYPE(iwl_trans->hw_rev) == IWL_CFG_MAC_TYPE_BZ) {
|
2024-03-20 23:26:30 +02:00
|
|
|
step = CNVI_AUX_MISC_CHIP_MAC_STEP(iwl_trans->hw_cnv_id);
|
2024-02-05 00:06:09 +02:00
|
|
|
|
|
|
|
/* For BZ-U, take B step also when A step is indicated */
|
|
|
|
if ((CNVI_AUX_MISC_CHIP_PROD_TYPE(iwl_trans->hw_cnv_id) ==
|
|
|
|
CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_U) &&
|
|
|
|
step == SILICON_A_STEP)
|
|
|
|
step = SILICON_B_STEP;
|
2024-03-20 23:26:30 +02:00
|
|
|
}
|
2024-02-05 00:06:09 +02:00
|
|
|
|
2024-03-20 23:26:30 +02:00
|
|
|
if (CSR_HW_REV_TYPE(iwl_trans->hw_rev) == IWL_CFG_MAC_TYPE_BZ ||
|
|
|
|
CSR_HW_REV_TYPE(iwl_trans->hw_rev) == IWL_CFG_MAC_TYPE_BZ_W) {
|
2024-02-05 00:06:09 +02:00
|
|
|
iwl_trans->hw_rev_step = step;
|
|
|
|
iwl_trans->hw_rev |= step;
|
|
|
|
}
|
|
|
|
|
2021-08-26 22:47:46 +03:00
|
|
|
/* Read cdb info (also contains the jacket info if needed in the future */
|
2023-04-14 13:11:52 +03:00
|
|
|
iwl_trans->hw_wfpm_id =
|
|
|
|
iwl_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR);
|
|
|
|
IWL_INFO(iwl_trans, "Detected crf-id 0x%x, cnv-id 0x%x wfpm id 0x%x\n",
|
|
|
|
iwl_trans->hw_crf_id, iwl_trans->hw_cnv_id,
|
|
|
|
iwl_trans->hw_wfpm_id);
|
2022-12-05 10:35:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In case that there is no OTP on the NIC, map the rf id and cdb info
|
|
|
|
* from the prph registers.
|
|
|
|
*/
|
|
|
|
static int map_crf_id(struct iwl_trans *iwl_trans)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
u32 val = iwl_trans->hw_crf_id;
|
2023-04-14 13:11:52 +03:00
|
|
|
u32 step_id = REG_CRF_ID_STEP(val);
|
|
|
|
u32 slave_id = REG_CRF_ID_SLAVE(val);
|
|
|
|
u32 jacket_id_cnv = REG_CRF_ID_SLAVE(iwl_trans->hw_cnv_id);
|
|
|
|
u32 jacket_id_wfpm = WFPM_OTP_CFG1_IS_JACKET(iwl_trans->hw_wfpm_id);
|
|
|
|
u32 cdb_id_wfpm = WFPM_OTP_CFG1_IS_CDB(iwl_trans->hw_wfpm_id);
|
2021-08-26 22:47:46 +03:00
|
|
|
|
|
|
|
/* Map between crf id to rf id */
|
|
|
|
switch (REG_CRF_ID_TYPE(val)) {
|
|
|
|
case REG_CRF_ID_TYPE_JF_1:
|
|
|
|
iwl_trans->hw_rf_id = (IWL_CFG_RF_TYPE_JF1 << 12);
|
|
|
|
break;
|
|
|
|
case REG_CRF_ID_TYPE_JF_2:
|
|
|
|
iwl_trans->hw_rf_id = (IWL_CFG_RF_TYPE_JF2 << 12);
|
|
|
|
break;
|
2023-04-14 13:11:52 +03:00
|
|
|
case REG_CRF_ID_TYPE_HR_NONE_CDB_1X1:
|
2021-08-26 22:47:46 +03:00
|
|
|
iwl_trans->hw_rf_id = (IWL_CFG_RF_TYPE_HR1 << 12);
|
|
|
|
break;
|
2023-04-14 13:11:52 +03:00
|
|
|
case REG_CRF_ID_TYPE_HR_NONE_CDB:
|
|
|
|
iwl_trans->hw_rf_id = (IWL_CFG_RF_TYPE_HR2 << 12);
|
|
|
|
break;
|
2021-08-26 22:47:46 +03:00
|
|
|
case REG_CRF_ID_TYPE_HR_CDB:
|
|
|
|
iwl_trans->hw_rf_id = (IWL_CFG_RF_TYPE_HR2 << 12);
|
|
|
|
break;
|
|
|
|
case REG_CRF_ID_TYPE_GF:
|
|
|
|
iwl_trans->hw_rf_id = (IWL_CFG_RF_TYPE_GF << 12);
|
|
|
|
break;
|
2023-04-14 13:11:52 +03:00
|
|
|
case REG_CRF_ID_TYPE_FM:
|
|
|
|
iwl_trans->hw_rf_id = (IWL_CFG_RF_TYPE_FM << 12);
|
|
|
|
break;
|
2023-09-21 11:58:10 +03:00
|
|
|
case REG_CRF_ID_TYPE_WHP:
|
|
|
|
iwl_trans->hw_rf_id = (IWL_CFG_RF_TYPE_WH << 12);
|
|
|
|
break;
|
2021-08-26 22:47:46 +03:00
|
|
|
default:
|
|
|
|
ret = -EIO;
|
|
|
|
IWL_ERR(iwl_trans,
|
2023-04-14 13:11:52 +03:00
|
|
|
"Can't find a correct rfid for crf id 0x%x\n",
|
2021-08-26 22:47:46 +03:00
|
|
|
REG_CRF_ID_TYPE(val));
|
2022-12-05 10:35:43 +02:00
|
|
|
goto out;
|
2021-08-26 22:47:46 +03:00
|
|
|
|
|
|
|
}
|
|
|
|
|
2023-04-14 13:11:52 +03:00
|
|
|
/* Set Step-id */
|
|
|
|
iwl_trans->hw_rf_id |= (step_id << 8);
|
|
|
|
|
2021-08-26 22:47:46 +03:00
|
|
|
/* Set CDB capabilities */
|
2023-04-14 13:11:52 +03:00
|
|
|
if (cdb_id_wfpm || slave_id) {
|
2021-08-26 22:47:46 +03:00
|
|
|
iwl_trans->hw_rf_id += BIT(28);
|
|
|
|
IWL_INFO(iwl_trans, "Adding cdb to rf id\n");
|
|
|
|
}
|
|
|
|
|
2023-04-14 13:11:52 +03:00
|
|
|
/* Set Jacket capabilities */
|
|
|
|
if (jacket_id_wfpm || jacket_id_cnv) {
|
|
|
|
iwl_trans->hw_rf_id += BIT(29);
|
|
|
|
IWL_INFO(iwl_trans, "Adding jacket to rf id\n");
|
|
|
|
}
|
2021-08-26 22:47:46 +03:00
|
|
|
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_INFO(iwl_trans,
|
|
|
|
"Detected rf-type 0x%x step-id 0x%x slave-id 0x%x from crf id 0x%x\n",
|
|
|
|
REG_CRF_ID_TYPE(val), step_id, slave_id, iwl_trans->hw_rf_id);
|
|
|
|
IWL_INFO(iwl_trans,
|
|
|
|
"Detected cdb-id 0x%x jacket-id 0x%x from wfpm id 0x%x\n",
|
|
|
|
cdb_id_wfpm, jacket_id_wfpm, iwl_trans->hw_wfpm_id);
|
|
|
|
IWL_INFO(iwl_trans, "Detected jacket-id 0x%x from cnvi id 0x%x\n",
|
|
|
|
jacket_id_cnv, iwl_trans->hw_cnv_id);
|
2021-08-26 22:47:46 +03:00
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-01-08 21:19:45 +02:00
|
|
|
/* PCI registers */
|
|
|
|
#define PCI_CFG_RETRY_TIMEOUT 0x041
|
|
|
|
|
2024-01-23 20:08:09 +02:00
|
|
|
VISIBLE_IF_IWLWIFI_KUNIT const struct iwl_dev_info *
|
2021-10-24 16:54:59 +03:00
|
|
|
iwl_pci_find_dev_info(u16 device, u16 subsystem_device,
|
2023-04-14 13:11:52 +03:00
|
|
|
u16 mac_type, u8 mac_step, u16 rf_type, u8 cdb,
|
|
|
|
u8 jacket, u8 rf_id, u8 no_160, u8 cores, u8 rf_step)
|
2021-10-24 16:54:59 +03:00
|
|
|
{
|
2021-11-18 15:21:02 +01:00
|
|
|
int num_devices = ARRAY_SIZE(iwl_dev_info_table);
|
2021-10-24 16:54:59 +03:00
|
|
|
int i;
|
|
|
|
|
2021-11-18 15:21:02 +01:00
|
|
|
if (!num_devices)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
for (i = num_devices - 1; i >= 0; i--) {
|
2021-10-24 16:54:59 +03:00
|
|
|
const struct iwl_dev_info *dev_info = &iwl_dev_info_table[i];
|
|
|
|
|
|
|
|
if (dev_info->device != (u16)IWL_CFG_ANY &&
|
|
|
|
dev_info->device != device)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (dev_info->subdevice != (u16)IWL_CFG_ANY &&
|
|
|
|
dev_info->subdevice != subsystem_device)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (dev_info->mac_type != (u16)IWL_CFG_ANY &&
|
|
|
|
dev_info->mac_type != mac_type)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (dev_info->mac_step != (u8)IWL_CFG_ANY &&
|
|
|
|
dev_info->mac_step != mac_step)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (dev_info->rf_type != (u16)IWL_CFG_ANY &&
|
|
|
|
dev_info->rf_type != rf_type)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (dev_info->cdb != (u8)IWL_CFG_ANY &&
|
|
|
|
dev_info->cdb != cdb)
|
|
|
|
continue;
|
|
|
|
|
2021-12-10 09:06:13 +02:00
|
|
|
if (dev_info->jacket != (u8)IWL_CFG_ANY &&
|
|
|
|
dev_info->jacket != jacket)
|
|
|
|
continue;
|
|
|
|
|
2021-10-24 16:54:59 +03:00
|
|
|
if (dev_info->rf_id != (u8)IWL_CFG_ANY &&
|
|
|
|
dev_info->rf_id != rf_id)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (dev_info->no_160 != (u8)IWL_CFG_ANY &&
|
|
|
|
dev_info->no_160 != no_160)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (dev_info->cores != (u8)IWL_CFG_ANY &&
|
|
|
|
dev_info->cores != cores)
|
|
|
|
continue;
|
|
|
|
|
2023-04-14 13:11:52 +03:00
|
|
|
if (dev_info->rf_step != (u8)IWL_CFG_ANY &&
|
|
|
|
dev_info->rf_step != rf_step)
|
|
|
|
continue;
|
|
|
|
|
2021-10-24 16:55:05 +03:00
|
|
|
return dev_info;
|
2021-10-24 16:54:59 +03:00
|
|
|
}
|
|
|
|
|
2021-10-24 16:55:05 +03:00
|
|
|
return NULL;
|
2021-10-24 16:54:59 +03:00
|
|
|
}
|
2024-01-23 20:08:09 +02:00
|
|
|
EXPORT_SYMBOL_IF_IWLWIFI_KUNIT(iwl_pci_find_dev_info);
|
2021-10-24 16:54:59 +03:00
|
|
|
|
2011-05-24 11:39:02 +03:00
|
|
|
static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
{
|
2021-03-30 16:24:58 +03:00
|
|
|
const struct iwl_cfg_trans_params *trans;
|
2014-11-18 15:39:51 +01:00
|
|
|
const struct iwl_cfg *cfg_7265d __maybe_unused = NULL;
|
2021-10-24 16:54:59 +03:00
|
|
|
const struct iwl_dev_info *dev_info;
|
2012-02-27 13:53:32 -08:00
|
|
|
struct iwl_trans *iwl_trans;
|
iwlwifi: allocate more receive buffers for HE devices
For HE-capable devices, we need to allocate more receive buffers as
there could be 256 frames aggregated into a single A-MPDU, and then
they might contain A-MSDUs as well. Until 22000 family, the devices
are able to put multiple frames into a single RB and the default RB
size is 4k, but starting from AX210 family this is no longer true.
On the other hand, those newer devices only use 2k receive buffers
(by default).
Modify the code and configuration to allocate an appropriate number
of RBs depending on the device capabilities:
* 4096 for AX210 HE devices, which use 2k buffers by default,
* 2048 for 22000 family devices which use 4k buffers by default,
* 512 for existing 9000 family devices, which doesn't really
change anything since that's the default before this patch,
* 512 also for AX210/22000 family devices that don't do HE.
Theoretically, for devices lower than AX210, we wouldn't have to
allocate that many RBs if the RB size was manually increased, but
to support that the code got more complex, and it didn't really
seem necessary as that's a use case for monitor mode only, where
hopefully the wasted memory isn't really much of a concern.
Note that AX210 devices actually support bigger than 12-bit VID,
which is required here as we want to allocate 4096 buffers plus
some for quick recycling, so adjust the code for that as well.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2019-09-27 10:36:02 +02:00
|
|
|
struct iwl_trans_pcie *trans_pcie;
|
2021-10-24 16:54:59 +03:00
|
|
|
int ret;
|
2021-03-30 16:24:58 +03:00
|
|
|
const struct iwl_cfg *cfg;
|
|
|
|
|
|
|
|
trans = (void *)(ent->driver_data & ~TRANS_CFG_MARKER);
|
|
|
|
|
2019-10-10 15:57:35 +03:00
|
|
|
/*
|
|
|
|
* This is needed for backwards compatibility with the old
|
|
|
|
* tables, so we don't need to change all the config structs
|
|
|
|
* at the same time. The cfg is used to compare with the old
|
|
|
|
* full cfg structs.
|
|
|
|
*/
|
2021-03-30 16:24:58 +03:00
|
|
|
cfg = (void *)(ent->driver_data & ~TRANS_CFG_MARKER);
|
2012-03-26 09:03:18 -07:00
|
|
|
|
2019-10-10 15:57:35 +03:00
|
|
|
/* make sure trans is the first element in iwl_cfg */
|
|
|
|
BUILD_BUG_ON(offsetof(struct iwl_cfg, trans));
|
2012-03-26 09:03:18 -07:00
|
|
|
|
2019-10-10 15:57:35 +03:00
|
|
|
iwl_trans = iwl_trans_pcie_alloc(pdev, ent, trans);
|
2013-08-10 16:35:45 +03:00
|
|
|
if (IS_ERR(iwl_trans))
|
|
|
|
return PTR_ERR(iwl_trans);
|
2012-03-26 09:03:18 -07:00
|
|
|
|
iwlwifi: allocate more receive buffers for HE devices
For HE-capable devices, we need to allocate more receive buffers as
there could be 256 frames aggregated into a single A-MPDU, and then
they might contain A-MSDUs as well. Until 22000 family, the devices
are able to put multiple frames into a single RB and the default RB
size is 4k, but starting from AX210 family this is no longer true.
On the other hand, those newer devices only use 2k receive buffers
(by default).
Modify the code and configuration to allocate an appropriate number
of RBs depending on the device capabilities:
* 4096 for AX210 HE devices, which use 2k buffers by default,
* 2048 for 22000 family devices which use 4k buffers by default,
* 512 for existing 9000 family devices, which doesn't really
change anything since that's the default before this patch,
* 512 also for AX210/22000 family devices that don't do HE.
Theoretically, for devices lower than AX210, we wouldn't have to
allocate that many RBs if the RB size was manually increased, but
to support that the code got more complex, and it didn't really
seem necessary as that's a use case for monitor mode only, where
hopefully the wasted memory isn't really much of a concern.
Note that AX210 devices actually support bigger than 12-bit VID,
which is required here as we want to allocate 4096 buffers plus
some for quick recycling, so adjust the code for that as well.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2019-09-27 10:36:02 +02:00
|
|
|
trans_pcie = IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
|
|
|
|
|
2021-10-17 16:59:45 +03:00
|
|
|
/*
|
|
|
|
* Let's try to grab NIC access early here. Sometimes, NICs may
|
|
|
|
* fail to initialize, and if that happens it's better if we see
|
|
|
|
* issues early on (and can reprobe, per the logic inside), than
|
|
|
|
* first trying to load the firmware etc. and potentially only
|
|
|
|
* detecting any problems when the first interface is brought up.
|
|
|
|
*/
|
2021-11-12 08:28:12 +02:00
|
|
|
ret = iwl_pcie_prepare_card_hw(iwl_trans);
|
|
|
|
if (!ret) {
|
|
|
|
ret = iwl_finish_nic_init(iwl_trans);
|
|
|
|
if (ret)
|
|
|
|
goto out_free_trans;
|
|
|
|
if (iwl_trans_grab_nic_access(iwl_trans)) {
|
2023-08-22 10:33:15 +03:00
|
|
|
get_crf_id(iwl_trans);
|
2021-11-12 08:28:12 +02:00
|
|
|
/* all good */
|
|
|
|
iwl_trans_release_nic_access(iwl_trans);
|
|
|
|
} else {
|
|
|
|
ret = -EIO;
|
|
|
|
goto out_free_trans;
|
|
|
|
}
|
2021-10-17 16:59:45 +03:00
|
|
|
}
|
|
|
|
|
2020-03-09 09:16:09 +02:00
|
|
|
iwl_trans->hw_rf_id = iwl_read32(iwl_trans, CSR_HW_RF_ID);
|
|
|
|
|
2021-08-26 22:47:46 +03:00
|
|
|
/*
|
|
|
|
* The RF_ID is set to zero in blank OTP so read version to
|
|
|
|
* extract the RF_ID.
|
|
|
|
* This is relevant only for family 9000 and up.
|
|
|
|
*/
|
|
|
|
if (iwl_trans->trans_cfg->rf_id &&
|
|
|
|
iwl_trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000 &&
|
2022-12-05 10:35:43 +02:00
|
|
|
!CSR_HW_RFID_TYPE(iwl_trans->hw_rf_id) && map_crf_id(iwl_trans)) {
|
2021-11-02 15:38:47 +08:00
|
|
|
ret = -EINVAL;
|
2021-08-26 22:47:46 +03:00
|
|
|
goto out_free_trans;
|
2021-11-02 15:38:47 +08:00
|
|
|
}
|
2021-08-26 22:47:46 +03:00
|
|
|
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_INFO(iwl_trans, "PCI dev %04x/%04x, rev=0x%x, rfid=0x%x\n",
|
|
|
|
pdev->device, pdev->subsystem_device,
|
|
|
|
iwl_trans->hw_rev, iwl_trans->hw_rf_id);
|
|
|
|
|
2021-10-24 16:54:59 +03:00
|
|
|
dev_info = iwl_pci_find_dev_info(pdev->device, pdev->subsystem_device,
|
|
|
|
CSR_HW_REV_TYPE(iwl_trans->hw_rev),
|
2021-12-07 16:05:51 +02:00
|
|
|
iwl_trans->hw_rev_step,
|
2021-10-24 16:54:59 +03:00
|
|
|
CSR_HW_RFID_TYPE(iwl_trans->hw_rf_id),
|
|
|
|
CSR_HW_RFID_IS_CDB(iwl_trans->hw_rf_id),
|
2021-12-10 09:06:13 +02:00
|
|
|
CSR_HW_RFID_IS_JACKET(iwl_trans->hw_rf_id),
|
2021-10-24 16:54:59 +03:00
|
|
|
IWL_SUBDEVICE_RF_ID(pdev->subsystem_device),
|
|
|
|
IWL_SUBDEVICE_NO_160(pdev->subsystem_device),
|
2023-04-14 13:11:52 +03:00
|
|
|
IWL_SUBDEVICE_CORES(pdev->subsystem_device),
|
|
|
|
CSR_HW_RFID_STEP(iwl_trans->hw_rf_id));
|
2021-10-24 16:54:59 +03:00
|
|
|
if (dev_info) {
|
|
|
|
iwl_trans->cfg = dev_info->cfg;
|
|
|
|
iwl_trans->name = dev_info->name;
|
2024-01-26 09:00:30 +02:00
|
|
|
iwl_trans->no_160 = dev_info->no_160 == IWL_CFG_NO_160;
|
2019-07-12 15:52:39 +03:00
|
|
|
}
|
|
|
|
|
2021-02-25 09:04:21 +02:00
|
|
|
#if IS_ENABLED(CONFIG_IWLMVM)
|
2014-11-18 15:39:51 +01:00
|
|
|
/*
|
|
|
|
* special-case 7265D, it has the same PCI IDs.
|
|
|
|
*
|
|
|
|
* Note that because we already pass the cfg to the transport above,
|
|
|
|
* all the parameters that the transport uses must, until that is
|
|
|
|
* changed, be identical to the ones in the 7265D configuration.
|
|
|
|
*/
|
|
|
|
if (cfg == &iwl7265_2ac_cfg)
|
|
|
|
cfg_7265d = &iwl7265d_2ac_cfg;
|
|
|
|
else if (cfg == &iwl7265_2n_cfg)
|
|
|
|
cfg_7265d = &iwl7265d_2n_cfg;
|
|
|
|
else if (cfg == &iwl7265_n_cfg)
|
|
|
|
cfg_7265d = &iwl7265d_n_cfg;
|
|
|
|
if (cfg_7265d &&
|
2018-08-02 17:08:40 +03:00
|
|
|
(iwl_trans->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_7265D)
|
2019-10-10 15:57:35 +03:00
|
|
|
iwl_trans->cfg = cfg_7265d;
|
2016-04-03 19:55:59 +03:00
|
|
|
|
2019-07-08 18:55:34 +03:00
|
|
|
/*
|
|
|
|
* This is a hack to switch from Qu B0 to Qu C0. We need to
|
2019-11-04 21:38:33 +02:00
|
|
|
* do this for all cfgs that use Qu B0, except for those using
|
|
|
|
* Jf, which have already been moved to the new table. The
|
|
|
|
* rest must be removed once we convert Qu with Hr as well.
|
2019-07-08 18:55:34 +03:00
|
|
|
*/
|
|
|
|
if (iwl_trans->hw_rev == CSR_HW_REV_TYPE_QU_C0) {
|
2020-04-24 19:47:06 +03:00
|
|
|
if (iwl_trans->cfg == &iwl_ax201_cfg_qu_hr)
|
2019-10-10 15:57:35 +03:00
|
|
|
iwl_trans->cfg = &iwl_ax201_cfg_qu_c0_hr_b0;
|
2019-11-04 21:02:47 +02:00
|
|
|
else if (iwl_trans->cfg == &killer1650s_2ax_cfg_qu_b0_hr_b0)
|
2019-10-10 15:57:35 +03:00
|
|
|
iwl_trans->cfg = &killer1650s_2ax_cfg_qu_c0_hr_b0;
|
2019-11-04 21:02:47 +02:00
|
|
|
else if (iwl_trans->cfg == &killer1650i_2ax_cfg_qu_b0_hr_b0)
|
2019-10-10 15:57:35 +03:00
|
|
|
iwl_trans->cfg = &killer1650i_2ax_cfg_qu_c0_hr_b0;
|
2019-07-08 18:55:34 +03:00
|
|
|
}
|
2019-08-16 15:55:54 +03:00
|
|
|
|
|
|
|
/* same thing for QuZ... */
|
|
|
|
if (iwl_trans->hw_rev == CSR_HW_REV_TYPE_QUZ) {
|
2020-04-24 19:47:06 +03:00
|
|
|
if (iwl_trans->cfg == &iwl_ax201_cfg_qu_hr)
|
2019-11-04 21:02:47 +02:00
|
|
|
iwl_trans->cfg = &iwl_ax201_cfg_quz_hr;
|
2020-04-24 12:20:08 +03:00
|
|
|
else if (iwl_trans->cfg == &killer1650s_2ax_cfg_qu_b0_hr_b0)
|
|
|
|
iwl_trans->cfg = &iwl_ax1650s_cfg_quz_hr;
|
|
|
|
else if (iwl_trans->cfg == &killer1650i_2ax_cfg_qu_b0_hr_b0)
|
|
|
|
iwl_trans->cfg = &iwl_ax1650i_cfg_quz_hr;
|
2019-08-16 15:55:54 +03:00
|
|
|
}
|
|
|
|
|
2014-11-18 15:39:51 +01:00
|
|
|
#endif
|
2019-10-10 15:57:35 +03:00
|
|
|
/*
|
2021-03-30 16:24:58 +03:00
|
|
|
* If we didn't set the cfg yet, the PCI ID table entry should have
|
|
|
|
* been a full config - if yes, use it, otherwise fail.
|
2019-10-10 15:57:35 +03:00
|
|
|
*/
|
2021-03-30 16:24:58 +03:00
|
|
|
if (!iwl_trans->cfg) {
|
|
|
|
if (ent->driver_data & TRANS_CFG_MARKER) {
|
|
|
|
pr_err("No config found for PCI dev %04x/%04x, rev=0x%x, rfid=0x%x\n",
|
|
|
|
pdev->device, pdev->subsystem_device,
|
|
|
|
iwl_trans->hw_rev, iwl_trans->hw_rf_id);
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out_free_trans;
|
|
|
|
}
|
2019-10-10 15:57:35 +03:00
|
|
|
iwl_trans->cfg = cfg;
|
2021-03-30 16:24:58 +03:00
|
|
|
}
|
2014-11-18 15:39:51 +01:00
|
|
|
|
2019-10-10 18:29:26 +03:00
|
|
|
/* if we don't have a name yet, copy name from the old cfg */
|
|
|
|
if (!iwl_trans->name)
|
|
|
|
iwl_trans->name = iwl_trans->cfg->name;
|
|
|
|
|
2019-10-10 15:57:35 +03:00
|
|
|
if (iwl_trans->trans_cfg->mq_rx_supported) {
|
|
|
|
if (WARN_ON(!iwl_trans->cfg->num_rbds)) {
|
iwlwifi: allocate more receive buffers for HE devices
For HE-capable devices, we need to allocate more receive buffers as
there could be 256 frames aggregated into a single A-MPDU, and then
they might contain A-MSDUs as well. Until 22000 family, the devices
are able to put multiple frames into a single RB and the default RB
size is 4k, but starting from AX210 family this is no longer true.
On the other hand, those newer devices only use 2k receive buffers
(by default).
Modify the code and configuration to allocate an appropriate number
of RBs depending on the device capabilities:
* 4096 for AX210 HE devices, which use 2k buffers by default,
* 2048 for 22000 family devices which use 4k buffers by default,
* 512 for existing 9000 family devices, which doesn't really
change anything since that's the default before this patch,
* 512 also for AX210/22000 family devices that don't do HE.
Theoretically, for devices lower than AX210, we wouldn't have to
allocate that many RBs if the RB size was manually increased, but
to support that the code got more complex, and it didn't really
seem necessary as that's a use case for monitor mode only, where
hopefully the wasted memory isn't really much of a concern.
Note that AX210 devices actually support bigger than 12-bit VID,
which is required here as we want to allocate 4096 buffers plus
some for quick recycling, so adjust the code for that as well.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2019-09-27 10:36:02 +02:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto out_free_trans;
|
|
|
|
}
|
2019-10-10 15:57:35 +03:00
|
|
|
trans_pcie->num_rx_bufs = iwl_trans->cfg->num_rbds;
|
iwlwifi: allocate more receive buffers for HE devices
For HE-capable devices, we need to allocate more receive buffers as
there could be 256 frames aggregated into a single A-MPDU, and then
they might contain A-MSDUs as well. Until 22000 family, the devices
are able to put multiple frames into a single RB and the default RB
size is 4k, but starting from AX210 family this is no longer true.
On the other hand, those newer devices only use 2k receive buffers
(by default).
Modify the code and configuration to allocate an appropriate number
of RBs depending on the device capabilities:
* 4096 for AX210 HE devices, which use 2k buffers by default,
* 2048 for 22000 family devices which use 4k buffers by default,
* 512 for existing 9000 family devices, which doesn't really
change anything since that's the default before this patch,
* 512 also for AX210/22000 family devices that don't do HE.
Theoretically, for devices lower than AX210, we wouldn't have to
allocate that many RBs if the RB size was manually increased, but
to support that the code got more complex, and it didn't really
seem necessary as that's a use case for monitor mode only, where
hopefully the wasted memory isn't really much of a concern.
Note that AX210 devices actually support bigger than 12-bit VID,
which is required here as we want to allocate 4096 buffers plus
some for quick recycling, so adjust the code for that as well.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2019-09-27 10:36:02 +02:00
|
|
|
} else {
|
|
|
|
trans_pcie->num_rx_bufs = RX_QUEUE_SIZE;
|
|
|
|
}
|
2014-11-18 15:39:51 +01:00
|
|
|
|
2023-06-20 13:03:56 +03:00
|
|
|
if (!iwl_trans->trans_cfg->integrated) {
|
|
|
|
u16 link_status;
|
|
|
|
|
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &link_status);
|
|
|
|
|
|
|
|
iwl_trans->pcie_link_speed =
|
|
|
|
u16_get_bits(link_status, PCI_EXP_LNKSTA_CLS);
|
|
|
|
}
|
|
|
|
|
2021-04-11 13:25:41 +03:00
|
|
|
ret = iwl_trans_init(iwl_trans);
|
|
|
|
if (ret)
|
|
|
|
goto out_free_trans;
|
|
|
|
|
2012-02-27 13:53:32 -08:00
|
|
|
pci_set_drvdata(pdev, iwl_trans);
|
2021-11-12 08:28:12 +02:00
|
|
|
|
|
|
|
/* try to get ownership so that we'll know if we don't own it */
|
|
|
|
iwl_pcie_prepare_card_hw(iwl_trans);
|
|
|
|
|
2016-12-13 09:48:57 +02:00
|
|
|
iwl_trans->drv = iwl_drv_start(iwl_trans);
|
2012-02-27 13:53:32 -08:00
|
|
|
|
2016-07-05 18:50:17 +03:00
|
|
|
if (IS_ERR(iwl_trans->drv)) {
|
|
|
|
ret = PTR_ERR(iwl_trans->drv);
|
2012-02-02 14:16:59 -08:00
|
|
|
goto out_free_trans;
|
2012-11-28 16:42:09 +02:00
|
|
|
}
|
2012-02-02 14:33:08 -08:00
|
|
|
|
2012-07-16 18:43:56 -07:00
|
|
|
/* register transport layer debugfs here */
|
2019-01-22 16:21:20 +01:00
|
|
|
iwl_trans_pcie_dbgfs_register(iwl_trans);
|
2012-07-16 18:43:56 -07:00
|
|
|
|
2011-05-31 08:22:30 +03:00
|
|
|
return 0;
|
|
|
|
|
2012-02-02 14:16:59 -08:00
|
|
|
out_free_trans:
|
2012-04-12 06:24:30 -07:00
|
|
|
iwl_trans_pcie_free(iwl_trans);
|
2012-11-28 16:42:09 +02:00
|
|
|
return ret;
|
2011-05-24 11:39:02 +03:00
|
|
|
}
|
|
|
|
|
2012-12-03 09:56:34 -05:00
|
|
|
static void iwl_pci_remove(struct pci_dev *pdev)
|
2011-05-31 09:07:00 +03:00
|
|
|
{
|
2012-03-26 08:51:09 -07:00
|
|
|
struct iwl_trans *trans = pci_get_drvdata(pdev);
|
2011-09-06 09:31:17 -07:00
|
|
|
|
2023-04-13 21:40:32 +03:00
|
|
|
if (!trans)
|
|
|
|
return;
|
|
|
|
|
2016-07-05 18:50:17 +03:00
|
|
|
iwl_drv_stop(trans->drv);
|
2016-02-08 11:18:46 +02:00
|
|
|
|
2012-04-12 06:24:30 -07:00
|
|
|
iwl_trans_pcie_free(trans);
|
2011-05-31 09:07:00 +03:00
|
|
|
}
|
|
|
|
|
2011-08-25 23:11:15 -07:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2011-05-24 11:39:02 +03:00
|
|
|
|
|
|
|
static int iwl_pci_suspend(struct device *device)
|
|
|
|
{
|
2011-07-11 13:14:37 +03:00
|
|
|
/* Before you put code here, think about WoWLAN. You cannot check here
|
|
|
|
* whether WoWLAN is enabled or not, and your code will run even if
|
|
|
|
* WoWLAN is enabled - don't kill the NIC, someone may need it in Sx.
|
|
|
|
*/
|
|
|
|
|
2013-08-02 10:51:22 +02:00
|
|
|
return 0;
|
2011-05-24 11:39:02 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static int iwl_pci_resume(struct device *device)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = to_pci_dev(device);
|
2013-08-02 10:51:22 +02:00
|
|
|
struct iwl_trans *trans = pci_get_drvdata(pdev);
|
2015-06-11 20:45:49 +03:00
|
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
2011-05-24 11:39:02 +03:00
|
|
|
|
2011-07-11 13:14:37 +03:00
|
|
|
/* Before you put code here, think about WoWLAN. You cannot check here
|
|
|
|
* whether WoWLAN is enabled or not, and your code will run even if
|
|
|
|
* WoWLAN is enabled - the NIC may be alive.
|
|
|
|
*/
|
|
|
|
|
2011-05-24 11:39:02 +03:00
|
|
|
/*
|
|
|
|
* We disable the RETRY_TIMEOUT register (0x41) to keep
|
|
|
|
* PCI Tx retries from interfering with C3 CPU state.
|
|
|
|
*/
|
|
|
|
pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
|
|
|
|
|
2013-08-02 10:51:22 +02:00
|
|
|
if (!trans->op_mode)
|
|
|
|
return 0;
|
|
|
|
|
2018-03-13 14:12:40 +02:00
|
|
|
/* In WOWLAN, let iwl_trans_pcie_d3_resume do the rest of the work */
|
|
|
|
if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
|
|
|
|
return 0;
|
|
|
|
|
2017-06-20 12:51:30 +02:00
|
|
|
/* reconfigure the MSI-X mapping to get the correct IRQ for rfkill */
|
|
|
|
iwl_pcie_conf_msix_hw(trans_pcie);
|
|
|
|
|
2015-05-28 16:50:12 +03:00
|
|
|
/*
|
2017-04-25 13:41:20 +02:00
|
|
|
* Enable rfkill interrupt (in order to keep track of the rfkill
|
|
|
|
* status). Must be locked to avoid processing a possible rfkill
|
2017-06-20 15:10:31 +02:00
|
|
|
* interrupt while in iwl_pcie_check_hw_rf_kill().
|
2015-05-28 16:50:12 +03:00
|
|
|
*/
|
2016-12-13 10:29:07 +01:00
|
|
|
mutex_lock(&trans_pcie->mutex);
|
2015-07-09 14:17:24 +03:00
|
|
|
iwl_enable_rfkill_int(trans);
|
2017-06-20 15:10:31 +02:00
|
|
|
iwl_pcie_check_hw_rf_kill(trans);
|
2015-06-11 20:45:49 +03:00
|
|
|
mutex_unlock(&trans_pcie->mutex);
|
2013-08-02 10:51:22 +02:00
|
|
|
|
|
|
|
return 0;
|
2011-05-24 11:39:02 +03:00
|
|
|
}
|
|
|
|
|
2016-01-06 18:40:38 -02:00
|
|
|
static const struct dev_pm_ops iwl_dev_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(iwl_pci_suspend,
|
|
|
|
iwl_pci_resume)
|
|
|
|
};
|
2011-05-24 11:39:02 +03:00
|
|
|
|
|
|
|
#define IWL_PM_OPS (&iwl_dev_pm_ops)
|
|
|
|
|
2016-01-06 18:40:38 -02:00
|
|
|
#else /* CONFIG_PM_SLEEP */
|
2011-05-24 11:39:02 +03:00
|
|
|
|
|
|
|
#define IWL_PM_OPS NULL
|
|
|
|
|
2016-01-06 18:40:38 -02:00
|
|
|
#endif /* CONFIG_PM_SLEEP */
|
2011-05-24 11:39:02 +03:00
|
|
|
|
|
|
|
static struct pci_driver iwl_pci_driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.id_table = iwl_hw_card_ids,
|
|
|
|
.probe = iwl_pci_probe,
|
2012-12-03 09:56:34 -05:00
|
|
|
.remove = iwl_pci_remove,
|
2011-05-24 11:39:02 +03:00
|
|
|
.driver.pm = IWL_PM_OPS,
|
|
|
|
};
|
|
|
|
|
|
|
|
int __must_check iwl_pci_register_driver(void)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
ret = pci_register_driver(&iwl_pci_driver);
|
|
|
|
if (ret)
|
|
|
|
pr_err("Unable to initialize PCI module\n");
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void iwl_pci_unregister_driver(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&iwl_pci_driver);
|
|
|
|
}
|