2005-04-16 15:20:36 -07:00
|
|
|
/*
|
|
|
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
|
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
|
|
|
* for more details.
|
|
|
|
|
*
|
|
|
|
|
* Copyright (C) 1994 Waldorf GMBH
|
|
|
|
|
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
|
|
|
|
|
* Copyright (C) 1996 Paul M. Antoine
|
|
|
|
|
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
|
2005-05-05 16:45:59 +00:00
|
|
|
* Copyright (C) 2004 Maciej W. Rozycki
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
|
|
|
|
#ifndef __ASM_CPU_INFO_H
|
|
|
|
|
#define __ASM_CPU_INFO_H
|
|
|
|
|
|
2017-03-21 22:40:43 +01:00
|
|
|
#include <linux/cache.h>
|
2008-09-23 00:05:54 -07:00
|
|
|
#include <linux/types.h>
|
|
|
|
|
|
2017-08-12 19:49:36 -07:00
|
|
|
#include <asm/mipsregs.h>
|
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/*
|
|
|
|
|
* Descriptor for a cache
|
|
|
|
|
*/
|
|
|
|
|
struct cache_desc {
|
|
|
|
|
unsigned int waysize; /* Bytes per way */
|
2006-11-30 01:14:45 +00:00
|
|
|
unsigned short sets; /* Number of lines per set */
|
|
|
|
|
unsigned char ways; /* Number of ways */
|
|
|
|
|
unsigned char linesz; /* Size of line in bytes */
|
|
|
|
|
unsigned char waybit; /* Bits to select in a cache set */
|
|
|
|
|
unsigned char flags; /* Flags describing cache properties */
|
2005-04-16 15:20:36 -07:00
|
|
|
};
|
|
|
|
|
|
MIPS: Add probing & defs for VZ & guest features
Add a few new cpu-features.h definitions for VZ sub-features, namely the
existence of the CP0_GuestCtl0Ext, CP0_GuestCtl1, and CP0_GuestCtl2
registers, and support for GuestID to dialias TLB entries belonging to
different guests.
Also add certain features present in the guest, with the naming scheme
cpu_guest_has_*. These are added separately to the main options bitfield
since they generally parallel similar features in the root context. A
few of these (FPU, MSA, watchpoints, perf counters, CP0_[X]ContextConfig
registers, MAAR registers, and probably others in future) can be
dynamically configured in the guest context, for which the
cpu_guest_has_dyn_* macros are added.
[ralf@linux-mips.org: Resolve merge conflict.]
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13231/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-11 15:50:30 +01:00
|
|
|
struct guest_info {
|
|
|
|
|
unsigned long ases;
|
|
|
|
|
unsigned long ases_dyn;
|
|
|
|
|
unsigned long long options;
|
|
|
|
|
unsigned long long options_dyn;
|
2017-03-14 10:15:27 +00:00
|
|
|
int tlbsize;
|
MIPS: Add probing & defs for VZ & guest features
Add a few new cpu-features.h definitions for VZ sub-features, namely the
existence of the CP0_GuestCtl0Ext, CP0_GuestCtl1, and CP0_GuestCtl2
registers, and support for GuestID to dialias TLB entries belonging to
different guests.
Also add certain features present in the guest, with the naming scheme
cpu_guest_has_*. These are added separately to the main options bitfield
since they generally parallel similar features in the root context. A
few of these (FPU, MSA, watchpoints, perf counters, CP0_[X]ContextConfig
registers, MAAR registers, and probably others in future) can be
dynamically configured in the guest context, for which the
cpu_guest_has_dyn_* macros are added.
[ralf@linux-mips.org: Resolve merge conflict.]
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13231/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-11 15:50:30 +01:00
|
|
|
u8 conf;
|
|
|
|
|
u8 kscratch_mask;
|
|
|
|
|
};
|
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/*
|
|
|
|
|
* Flag definitions
|
|
|
|
|
*/
|
|
|
|
|
#define MIPS_CACHE_NOT_PRESENT 0x00000001
|
|
|
|
|
#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
|
|
|
|
|
#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
|
|
|
|
|
#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
|
|
|
|
|
#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
|
2006-03-13 18:23:03 +09:00
|
|
|
#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
|
struct cpuinfo_mips {
|
MIPS: Expand MIPS32 ASIDs to 64 bits
ASIDs have always been stored as unsigned longs, ie. 32 bits on MIPS32
kernels. This is problematic because it is feasible for the ASID version
to overflow & wrap around to zero.
We currently attempt to handle this overflow by simply setting the ASID
version to 1, using asid_first_version(), but we make no attempt to
account for the fact that there may be mm_structs with stale ASIDs that
have versions which we now reuse due to the overflow & wrap around.
Encountering this requires that:
1) A struct mm_struct X is active on CPU A using ASID (V,n).
2) That mm is not used on CPU A for the length of time that it takes
for CPU A's asid_cache to overflow & wrap around to the same
version V that the mm had in step 1. During this time tasks using
the mm could either be sleeping or only scheduled on other CPUs.
3) Some other mm Y becomes active on CPU A and is allocated the same
ASID (V,n).
4) mm X now becomes active on CPU A again, and now incorrectly has the
same ASID as mm Y.
Where struct mm_struct ASIDs are represented above in the format
(version, EntryHi.ASID), and on a typical MIPS32 system version will be
24 bits wide & EntryHi.ASID will be 8 bits wide.
The length of time required in step 2 is highly dependent upon the CPU &
workload, but for a hypothetical 2GHz CPU running a workload which
generates a new ASID every 10000 cycles this period is around 248 days.
Due to this long period of time & the fact that tasks need to be
scheduled in just the right (or wrong, depending upon your inclination)
way, this is obviously a difficult bug to encounter but it's entirely
possible as evidenced by reports.
In order to fix this, simply extend ASIDs to 64 bits even on MIPS32
builds. This will extend the period of time required for the
hypothetical system above to encounter the problem from 28 days to
around 3 trillion years, which feels safely outside of the realms of
possibility.
The cost of this is slightly more generated code in some commonly
executed paths, but this is pretty minimal:
| Code Size Gain | Percentage
-----------------------|----------------|-------------
decstation_defconfig | +270 | +0.00%
32r2el_defconfig | +652 | +0.01%
32r6el_defconfig | +1000 | +0.01%
I have been unable to measure any change in performance of the LMbench
lat_ctx or lat_proc tests resulting from the 64b ASIDs on either
32r2el_defconfig+interAptiv or 32r6el_defconfig+I6500 systems.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Suggested-by: James Hogan <jhogan@kernel.org>
References: https://lore.kernel.org/linux-mips/80B78A8B8FEE6145A87579E8435D78C30205D5F3@fzex.ruijie.com.cn/
References: https://lore.kernel.org/linux-mips/1488684260-18867-1-git-send-email-jiwei.sun@windriver.com/
Cc: Jiwei Sun <jiwei.sun@windriver.com>
Cc: Yu Huabing <yhb@ruijie.com.cn>
Cc: stable@vger.kernel.org # 2.6.12+
Cc: linux-mips@vger.kernel.org
2018-12-04 23:44:12 +00:00
|
|
|
u64 asid_cache;
|
2016-05-06 14:36:24 +01:00
|
|
|
#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
|
|
|
|
|
unsigned long asid_mask;
|
|
|
|
|
#endif
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Capability and feature descriptor structure for MIPS CPU
|
|
|
|
|
*/
|
2005-05-05 16:45:59 +00:00
|
|
|
unsigned long ases;
|
2014-07-14 10:14:02 +01:00
|
|
|
unsigned long long options;
|
2014-05-21 11:42:10 +02:00
|
|
|
unsigned int udelay_val;
|
2005-04-16 15:20:36 -07:00
|
|
|
unsigned int processor_id;
|
|
|
|
|
unsigned int fpu_id;
|
2015-04-03 23:27:48 +01:00
|
|
|
unsigned int fpu_csr31;
|
|
|
|
|
unsigned int fpu_msk31;
|
2014-01-27 15:23:10 +00:00
|
|
|
unsigned int msa_id;
|
2005-04-16 15:20:36 -07:00
|
|
|
unsigned int cputype;
|
|
|
|
|
int isa_level;
|
|
|
|
|
int tlbsize;
|
2013-11-14 16:12:31 +00:00
|
|
|
int tlbsizevtlb;
|
|
|
|
|
int tlbsizeftlbsets;
|
|
|
|
|
int tlbsizeftlbways;
|
2013-01-22 12:59:30 +01:00
|
|
|
struct cache_desc icache; /* Primary I-cache */
|
|
|
|
|
struct cache_desc dcache; /* Primary D or combined I/D cache */
|
2016-03-03 09:45:09 +08:00
|
|
|
struct cache_desc vcache; /* Victim cache, between pcache and scache */
|
2013-01-22 12:59:30 +01:00
|
|
|
struct cache_desc scache; /* Secondary cache */
|
|
|
|
|
struct cache_desc tcache; /* Tertiary/split secondary cache */
|
|
|
|
|
int srsets; /* Shadow register sets */
|
2014-06-26 11:41:26 +08:00
|
|
|
int package;/* physical package number */
|
2017-08-12 19:49:36 -07:00
|
|
|
unsigned int globalnumber;
|
2010-02-02 08:52:20 -08:00
|
|
|
#ifdef CONFIG_64BIT
|
2013-01-22 12:59:30 +01:00
|
|
|
int vmbits; /* Virtual memory size in bits */
|
2007-03-02 20:42:04 +00:00
|
|
|
#endif
|
2013-01-22 12:59:30 +01:00
|
|
|
void *data; /* Additional data */
|
2008-09-23 00:05:54 -07:00
|
|
|
unsigned int watch_reg_count; /* Number that exist */
|
|
|
|
|
unsigned int watch_reg_use_cnt; /* Usable by ptrace */
|
|
|
|
|
#define NUM_WATCH_REGS 4
|
|
|
|
|
u16 watch_reg_masks[NUM_WATCH_REGS];
|
2010-12-21 14:19:09 -08:00
|
|
|
unsigned int kscratch_mask; /* Usable KScratch mask. */
|
2014-07-18 10:51:32 +01:00
|
|
|
/*
|
|
|
|
|
* Cache Coherency attribute for write-combine memory writes.
|
|
|
|
|
* (shifted by _CACHE_SHIFT)
|
|
|
|
|
*/
|
|
|
|
|
unsigned int writecombine;
|
2015-01-26 13:04:33 +00:00
|
|
|
/*
|
|
|
|
|
* Simple counter to prevent enabling HTW in nested
|
|
|
|
|
* htw_start/htw_stop calls
|
|
|
|
|
*/
|
|
|
|
|
unsigned int htw_seq;
|
MIPS: Add probing & defs for VZ & guest features
Add a few new cpu-features.h definitions for VZ sub-features, namely the
existence of the CP0_GuestCtl0Ext, CP0_GuestCtl1, and CP0_GuestCtl2
registers, and support for GuestID to dialias TLB entries belonging to
different guests.
Also add certain features present in the guest, with the naming scheme
cpu_guest_has_*. These are added separately to the main options bitfield
since they generally parallel similar features in the root context. A
few of these (FPU, MSA, watchpoints, perf counters, CP0_[X]ContextConfig
registers, MAAR registers, and probably others in future) can be
dynamically configured in the guest context, for which the
cpu_guest_has_dyn_* macros are added.
[ralf@linux-mips.org: Resolve merge conflict.]
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13231/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-11 15:50:30 +01:00
|
|
|
|
|
|
|
|
/* VZ & Guest features */
|
|
|
|
|
struct guest_info guest;
|
|
|
|
|
unsigned int gtoffset_mask;
|
|
|
|
|
unsigned int guestid_mask;
|
2017-03-14 10:15:31 +00:00
|
|
|
unsigned int guestid_cache;
|
MIPS: emulate CPUCFG instruction on older Loongson64 cores
CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.
The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.
This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 21:37:01 +08:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
|
|
|
|
|
/* CPUCFG data for this CPU, synthesized at probe time.
|
|
|
|
|
*
|
|
|
|
|
* CPUCFG select 0 is PRId, 4 and above are unimplemented for now.
|
|
|
|
|
* So the only stored values are for CPUCFG selects 1-3 inclusive.
|
|
|
|
|
*/
|
|
|
|
|
u32 loongson3_cpucfg_data[3];
|
|
|
|
|
#endif
|
2005-04-16 15:20:36 -07:00
|
|
|
} __attribute__((aligned(SMP_CACHE_BYTES)));
|
|
|
|
|
|
|
|
|
|
extern struct cpuinfo_mips cpu_data[];
|
|
|
|
|
#define current_cpu_data cpu_data[smp_processor_id()]
|
2007-03-10 01:07:45 +09:00
|
|
|
#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
|
2013-09-17 13:58:12 +02:00
|
|
|
#define boot_cpu_data cpu_data[0]
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
|
extern void cpu_probe(void);
|
|
|
|
|
extern void cpu_report(void);
|
|
|
|
|
|
2007-10-11 23:46:17 +01:00
|
|
|
extern const char *__cpu_name[];
|
2016-01-25 16:06:59 +00:00
|
|
|
#define cpu_name_string() __cpu_name[raw_smp_processor_id()]
|
2007-10-11 23:46:17 +01:00
|
|
|
|
2013-10-16 17:10:07 +02:00
|
|
|
struct seq_file;
|
|
|
|
|
struct notifier_block;
|
|
|
|
|
|
|
|
|
|
extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
|
|
|
|
|
extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
|
|
|
|
|
|
|
|
|
|
#define proc_cpuinfo_notifier(fn, pri) \
|
|
|
|
|
({ \
|
|
|
|
|
static struct notifier_block fn##_nb = { \
|
|
|
|
|
.notifier_call = fn, \
|
|
|
|
|
.priority = pri \
|
|
|
|
|
}; \
|
|
|
|
|
\
|
|
|
|
|
register_proc_cpuinfo_notifier(&fn##_nb); \
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
struct proc_cpuinfo_notifier_args {
|
|
|
|
|
struct seq_file *m;
|
|
|
|
|
unsigned long n;
|
|
|
|
|
};
|
|
|
|
|
|
2017-08-12 19:49:38 -07:00
|
|
|
static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo)
|
|
|
|
|
{
|
|
|
|
|
/* Optimisation for systems where multiple clusters aren't used */
|
mips: Add MIPS Release 5 support
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21 17:07:14 +03:00
|
|
|
if (!IS_ENABLED(CONFIG_CPU_MIPSR5) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
|
2017-08-12 19:49:38 -07:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >>
|
|
|
|
|
MIPS_GLOBALNUMBER_CLUSTER_SHF;
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-12 19:49:35 -07:00
|
|
|
static inline unsigned int cpu_core(struct cpuinfo_mips *cpuinfo)
|
|
|
|
|
{
|
2017-08-12 19:49:36 -07:00
|
|
|
return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CORE) >>
|
|
|
|
|
MIPS_GLOBALNUMBER_CORE_SHF;
|
2017-08-12 19:49:35 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned int cpu_vpe_id(struct cpuinfo_mips *cpuinfo)
|
|
|
|
|
{
|
2017-08-12 19:49:36 -07:00
|
|
|
/* Optimisation for systems where VP(E)s aren't used */
|
|
|
|
|
if (!IS_ENABLED(CONFIG_MIPS_MT_SMP) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
|
|
|
|
|
return 0;
|
2017-08-12 19:49:35 -07:00
|
|
|
|
2017-08-12 19:49:36 -07:00
|
|
|
return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_VP) >>
|
|
|
|
|
MIPS_GLOBALNUMBER_VP_SHF;
|
2017-08-12 19:49:35 -07:00
|
|
|
}
|
2014-03-24 10:19:24 +00:00
|
|
|
|
2017-08-12 19:49:38 -07:00
|
|
|
extern void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster);
|
2017-08-12 19:49:36 -07:00
|
|
|
extern void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core);
|
|
|
|
|
extern void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe);
|
|
|
|
|
|
2017-08-12 19:49:37 -07:00
|
|
|
static inline bool cpus_are_siblings(int cpua, int cpub)
|
|
|
|
|
{
|
|
|
|
|
struct cpuinfo_mips *infoa = &cpu_data[cpua];
|
|
|
|
|
struct cpuinfo_mips *infob = &cpu_data[cpub];
|
|
|
|
|
unsigned int gnuma, gnumb;
|
|
|
|
|
|
|
|
|
|
if (infoa->package != infob->package)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
gnuma = infoa->globalnumber & ~MIPS_GLOBALNUMBER_VP;
|
|
|
|
|
gnumb = infob->globalnumber & ~MIPS_GLOBALNUMBER_VP;
|
|
|
|
|
if (gnuma != gnumb)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-06 14:36:23 +01:00
|
|
|
static inline unsigned long cpu_asid_inc(void)
|
|
|
|
|
{
|
|
|
|
|
return 1 << CONFIG_MIPS_ASID_SHIFT;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned long cpu_asid_mask(struct cpuinfo_mips *cpuinfo)
|
|
|
|
|
{
|
2016-05-06 14:36:24 +01:00
|
|
|
#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
|
|
|
|
|
return cpuinfo->asid_mask;
|
|
|
|
|
#endif
|
2016-05-06 14:36:23 +01:00
|
|
|
return ((1 << CONFIG_MIPS_ASID_BITS) - 1) << CONFIG_MIPS_ASID_SHIFT;
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-06 14:36:24 +01:00
|
|
|
static inline void set_cpu_asid_mask(struct cpuinfo_mips *cpuinfo,
|
|
|
|
|
unsigned long asid_mask)
|
|
|
|
|
{
|
|
|
|
|
#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
|
|
|
|
|
cpuinfo->asid_mask = asid_mask;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
#endif /* __ASM_CPU_INFO_H */
|