linux/arch/arm/include/asm/hardware/cache-b15-rac.h

#ifndef __ASM_ARM_HARDWARE_CACHE_B15_RAC_H
#define __ASM_ARM_HARDWARE_CACHE_B15_RAC_H

#ifndef __ASSEMBLY__

void b15_flush_kern_cache_all(void);

#endif

#endif
ARM: 8725/1: Add Broadcom Brahma-B15 readahead cache support This patch adds support for the Broadcom Brahma-B15 CPU readahead cache controller. This cache controller sits between the L2 and the memory bus and its purpose is to provide a friendler burst size towards the DDR interface than the native cache line size. The readahead cache is mostly transparent, except for flush_kern_cache_all, which is precisely what we are overriding here. The readahead cache only intercepts reads, and does invalidate on writes (IOW), as such, some data can remain stale in any of its buffers, such that we need to flush it, which is an operation that needs to happen in a particular order: - disable the readahead cache - flush it - call the appropriate cache-v7.S function - re-enable This patch tries to minimize the impact to the cache-v7.S file by only providing a stub in case CONFIG_CACHE_B15_RAC is enabled (default for ARCH_BRCMSTB since it is the current user). Signed-off-by: Alamy Liu <alamyliu@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> 2017-12-01 01:10:09 +01:00			`#ifndef __ASM_ARM_HARDWARE_CACHE_B15_RAC_H`
			`#define __ASM_ARM_HARDWARE_CACHE_B15_RAC_H`

			`#ifndef __ASSEMBLY__`

			`void b15_flush_kern_cache_all(void);`

			`#endif`

			`#endif`