net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2019, Vladimir Oltean <olteanv@gmail.com>
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*/
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#include "sja1105.h"
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/* The adjfine API clamps ppb between [-32,768,000, 32,768,000], and
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* therefore scaled_ppm between [-2,147,483,648, 2,147,483,647].
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* Set the maximum supported ppb to a round value smaller than the maximum.
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*
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* Percentually speaking, this is a +/- 0.032x adjustment of the
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* free-running counter (0.968x to 1.032x).
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*/
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#define SJA1105_MAX_ADJ_PPB 32000000
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#define SJA1105_SIZE_PTP_CMD 4
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/* Timestamps are in units of 8 ns clock ticks (equivalent to a fixed
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* 125 MHz clock) so the scale factor (MULT / SHIFT) needs to be 8.
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* Furthermore, wisely pick SHIFT as 28 bits, which translates
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* MULT into 2^31 (0x80000000). This is the same value around which
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* the hardware PTPCLKRATE is centered, so the same ppb conversion
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* arithmetic can be reused.
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*/
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#define SJA1105_CC_SHIFT 28
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#define SJA1105_CC_MULT (8 << SJA1105_CC_SHIFT)
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/* Having 33 bits of cycle counter left until a 64-bit overflow during delta
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* conversion, we multiply this by the 8 ns counter resolution and arrive at
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* a comfortable 68.71 second refresh interval until the delta would cause
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* an integer overflow, in absence of any other readout.
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* Approximate to 1 minute.
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*/
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#define SJA1105_REFRESH_INTERVAL (HZ * 60)
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/* This range is actually +/- SJA1105_MAX_ADJ_PPB
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* divided by 1000 (ppb -> ppm) and with a 16-bit
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* "fractional" part (actually fixed point).
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* |
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* v
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* Convert scaled_ppm from the +/- ((10^6) << 16) range
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* into the +/- (1 << 31) range.
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*
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* This forgoes a "ppb" numeric representation (up to NSEC_PER_SEC)
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* and defines the scaling factor between scaled_ppm and the actual
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* frequency adjustments (both cycle counter and hardware).
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*
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* ptpclkrate = scaled_ppm * 2^31 / (10^6 * 2^16)
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* simplifies to
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* ptpclkrate = scaled_ppm * 2^9 / 5^6
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*/
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#define SJA1105_CC_MULT_NUM (1 << 9)
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#define SJA1105_CC_MULT_DEM 15625
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2019-10-12 02:18:15 +03:00
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#define ptp_caps_to_data(d) \
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container_of((d), struct sja1105_ptp_data, caps)
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#define cc_to_ptp_data(d) \
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container_of((d), struct sja1105_ptp_data, tstamp_cc)
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#define dw_to_ptp_data(d) \
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container_of((d), struct sja1105_ptp_data, refresh_work)
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#define ptp_data_to_sja1105(d) \
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container_of((d), struct sja1105_private, ptp_data)
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net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
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2019-10-12 02:18:15 +03:00
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static int sja1105_init_avb_params(struct sja1105_private *priv,
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bool on)
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{
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struct sja1105_avb_params_entry *avb;
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struct sja1105_table *table;
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table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];
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/* Discard previous AVB Parameters Table */
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if (table->entry_count) {
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kfree(table->entries);
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table->entry_count = 0;
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}
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/* Configure the reception of meta frames only if requested */
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if (!on)
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return 0;
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table->entries = kcalloc(SJA1105_MAX_AVB_PARAMS_COUNT,
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table->ops->unpacked_entry_size, GFP_KERNEL);
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if (!table->entries)
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return -ENOMEM;
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table->entry_count = SJA1105_MAX_AVB_PARAMS_COUNT;
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avb = table->entries;
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avb->destmeta = SJA1105_META_DMAC;
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avb->srcmeta = SJA1105_META_SMAC;
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return 0;
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}
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/* Must be called only with priv->tagger_data.state bit
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* SJA1105_HWTS_RX_EN cleared
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*/
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static int sja1105_change_rxtstamping(struct sja1105_private *priv,
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bool on)
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{
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struct sja1105_general_params_entry *general_params;
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struct sja1105_table *table;
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int rc;
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table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
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general_params = table->entries;
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general_params->send_meta1 = on;
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general_params->send_meta0 = on;
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rc = sja1105_init_avb_params(priv, on);
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if (rc < 0)
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return rc;
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/* Initialize the meta state machine to a known state */
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if (priv->tagger_data.stampable_skb) {
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kfree_skb(priv->tagger_data.stampable_skb);
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priv->tagger_data.stampable_skb = NULL;
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}
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return sja1105_static_config_reload(priv);
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}
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int sja1105_hwtstamp_set(struct dsa_switch *ds, int port, struct ifreq *ifr)
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{
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struct sja1105_private *priv = ds->priv;
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struct hwtstamp_config config;
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bool rx_on;
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int rc;
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if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
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return -EFAULT;
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switch (config.tx_type) {
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case HWTSTAMP_TX_OFF:
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priv->ports[port].hwts_tx_en = false;
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break;
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case HWTSTAMP_TX_ON:
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priv->ports[port].hwts_tx_en = true;
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break;
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default:
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return -ERANGE;
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}
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switch (config.rx_filter) {
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case HWTSTAMP_FILTER_NONE:
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rx_on = false;
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break;
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default:
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rx_on = true;
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break;
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}
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if (rx_on != test_bit(SJA1105_HWTS_RX_EN, &priv->tagger_data.state)) {
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clear_bit(SJA1105_HWTS_RX_EN, &priv->tagger_data.state);
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rc = sja1105_change_rxtstamping(priv, rx_on);
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if (rc < 0) {
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dev_err(ds->dev,
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"Failed to change RX timestamping: %d\n", rc);
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return rc;
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}
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if (rx_on)
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set_bit(SJA1105_HWTS_RX_EN, &priv->tagger_data.state);
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}
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if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
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return -EFAULT;
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return 0;
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}
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int sja1105_hwtstamp_get(struct dsa_switch *ds, int port, struct ifreq *ifr)
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{
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struct sja1105_private *priv = ds->priv;
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struct hwtstamp_config config;
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config.flags = 0;
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if (priv->ports[port].hwts_tx_en)
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config.tx_type = HWTSTAMP_TX_ON;
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else
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config.tx_type = HWTSTAMP_TX_OFF;
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if (test_bit(SJA1105_HWTS_RX_EN, &priv->tagger_data.state))
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config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
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else
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config.rx_filter = HWTSTAMP_FILTER_NONE;
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return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
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-EFAULT : 0;
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}
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net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
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int sja1105_get_ts_info(struct dsa_switch *ds, int port,
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struct ethtool_ts_info *info)
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{
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struct sja1105_private *priv = ds->priv;
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2019-10-12 02:18:15 +03:00
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struct sja1105_ptp_data *ptp_data = &priv->ptp_data;
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net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
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/* Called during cleanup */
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2019-10-12 02:18:15 +03:00
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if (!ptp_data->clock)
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net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
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return -ENODEV;
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info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
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SOF_TIMESTAMPING_RX_HARDWARE |
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SOF_TIMESTAMPING_RAW_HARDWARE;
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2019-06-08 15:04:43 +03:00
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info->tx_types = (1 << HWTSTAMP_TX_OFF) |
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(1 << HWTSTAMP_TX_ON);
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info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT);
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2019-10-12 02:18:15 +03:00
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info->phc_index = ptp_clock_index(ptp_data->clock);
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net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
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return 0;
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}
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2019-10-12 02:18:16 +03:00
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int sja1105et_ptp_cmd(const struct dsa_switch *ds,
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const struct sja1105_ptp_cmd *cmd)
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net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
{
|
2019-10-12 02:18:14 +03:00
|
|
|
const struct sja1105_private *priv = ds->priv;
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
const struct sja1105_regs *regs = priv->info->regs;
|
|
|
|
const int size = SJA1105_SIZE_PTP_CMD;
|
|
|
|
u8 buf[SJA1105_SIZE_PTP_CMD] = {0};
|
|
|
|
/* No need to keep this as part of the structure */
|
|
|
|
u64 valid = 1;
|
|
|
|
|
|
|
|
sja1105_pack(buf, &valid, 31, 31, size);
|
|
|
|
sja1105_pack(buf, &cmd->resptp, 2, 2, size);
|
|
|
|
|
2019-10-01 22:18:01 +03:00
|
|
|
return sja1105_xfer_buf(priv, SPI_WRITE, regs->ptp_control, buf,
|
|
|
|
SJA1105_SIZE_PTP_CMD);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
}
|
|
|
|
|
2019-10-12 02:18:16 +03:00
|
|
|
int sja1105pqrs_ptp_cmd(const struct dsa_switch *ds,
|
|
|
|
const struct sja1105_ptp_cmd *cmd)
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
{
|
2019-10-12 02:18:14 +03:00
|
|
|
const struct sja1105_private *priv = ds->priv;
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
const struct sja1105_regs *regs = priv->info->regs;
|
|
|
|
const int size = SJA1105_SIZE_PTP_CMD;
|
|
|
|
u8 buf[SJA1105_SIZE_PTP_CMD] = {0};
|
|
|
|
/* No need to keep this as part of the structure */
|
|
|
|
u64 valid = 1;
|
|
|
|
|
|
|
|
sja1105_pack(buf, &valid, 31, 31, size);
|
|
|
|
sja1105_pack(buf, &cmd->resptp, 3, 3, size);
|
|
|
|
|
2019-10-01 22:18:01 +03:00
|
|
|
return sja1105_xfer_buf(priv, SPI_WRITE, regs->ptp_control, buf,
|
|
|
|
SJA1105_SIZE_PTP_CMD);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
}
|
|
|
|
|
2019-06-08 15:04:35 +03:00
|
|
|
/* The switch returns partial timestamps (24 bits for SJA1105 E/T, which wrap
|
|
|
|
* around in 0.135 seconds, and 32 bits for P/Q/R/S, wrapping around in 34.35
|
|
|
|
* seconds).
|
|
|
|
*
|
|
|
|
* This receives the RX or TX MAC timestamps, provided by hardware as
|
|
|
|
* the lower bits of the cycle counter, sampled at the time the timestamp was
|
|
|
|
* collected.
|
|
|
|
*
|
|
|
|
* To reconstruct into a full 64-bit-wide timestamp, the cycle counter is
|
|
|
|
* read and the high-order bits are filled in.
|
|
|
|
*
|
|
|
|
* Must be called within one wraparound period of the partial timestamp since
|
|
|
|
* it was generated by the MAC.
|
|
|
|
*/
|
2019-10-12 02:18:15 +03:00
|
|
|
static u64 sja1105_tstamp_reconstruct(struct dsa_switch *ds, u64 now,
|
|
|
|
u64 ts_partial)
|
2019-06-08 15:04:35 +03:00
|
|
|
{
|
2019-10-12 02:18:14 +03:00
|
|
|
struct sja1105_private *priv = ds->priv;
|
2019-06-08 15:04:35 +03:00
|
|
|
u64 partial_tstamp_mask = CYCLECOUNTER_MASK(priv->info->ptp_ts_bits);
|
|
|
|
u64 ts_reconstructed;
|
|
|
|
|
|
|
|
ts_reconstructed = (now & ~partial_tstamp_mask) | ts_partial;
|
|
|
|
|
|
|
|
/* Check lower bits of current cycle counter against the timestamp.
|
|
|
|
* If the current cycle counter is lower than the partial timestamp,
|
|
|
|
* then wraparound surely occurred and must be accounted for.
|
|
|
|
*/
|
|
|
|
if ((now & partial_tstamp_mask) <= ts_partial)
|
|
|
|
ts_reconstructed -= (partial_tstamp_mask + 1);
|
|
|
|
|
|
|
|
return ts_reconstructed;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Reads the SPI interface for an egress timestamp generated by the switch
|
|
|
|
* for frames sent using management routes.
|
|
|
|
*
|
|
|
|
* SJA1105 E/T layout of the 4-byte SPI payload:
|
|
|
|
*
|
|
|
|
* 31 23 15 7 0
|
|
|
|
* | | | | |
|
|
|
|
* +-----+-----+-----+ ^
|
|
|
|
* ^ |
|
|
|
|
* | |
|
|
|
|
* 24-bit timestamp Update bit
|
|
|
|
*
|
|
|
|
*
|
|
|
|
* SJA1105 P/Q/R/S layout of the 8-byte SPI payload:
|
|
|
|
*
|
|
|
|
* 31 23 15 7 0 63 55 47 39 32
|
|
|
|
* | | | | | | | | | |
|
|
|
|
* ^ +-----+-----+-----+-----+
|
|
|
|
* | ^
|
|
|
|
* | |
|
|
|
|
* Update bit 32-bit timestamp
|
|
|
|
*
|
|
|
|
* Notice that the update bit is in the same place.
|
|
|
|
* To have common code for E/T and P/Q/R/S for reading the timestamp,
|
|
|
|
* we need to juggle with the offset and the bit indices.
|
|
|
|
*/
|
2019-10-12 02:18:15 +03:00
|
|
|
static int sja1105_ptpegr_ts_poll(struct dsa_switch *ds, int port, u64 *ts)
|
2019-06-08 15:04:35 +03:00
|
|
|
{
|
2019-10-12 02:18:14 +03:00
|
|
|
struct sja1105_private *priv = ds->priv;
|
2019-06-08 15:04:35 +03:00
|
|
|
const struct sja1105_regs *regs = priv->info->regs;
|
|
|
|
int tstamp_bit_start, tstamp_bit_end;
|
|
|
|
int timeout = 10;
|
|
|
|
u8 packed_buf[8];
|
|
|
|
u64 update;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
do {
|
2019-10-01 22:18:01 +03:00
|
|
|
rc = sja1105_xfer_buf(priv, SPI_READ, regs->ptpegr_ts[port],
|
|
|
|
packed_buf, priv->info->ptpegr_ts_bytes);
|
2019-06-08 15:04:35 +03:00
|
|
|
if (rc < 0)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
sja1105_unpack(packed_buf, &update, 0, 0,
|
|
|
|
priv->info->ptpegr_ts_bytes);
|
|
|
|
if (update)
|
|
|
|
break;
|
|
|
|
|
|
|
|
usleep_range(10, 50);
|
|
|
|
} while (--timeout);
|
|
|
|
|
|
|
|
if (!timeout)
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
|
|
|
/* Point the end bit to the second 32-bit word on P/Q/R/S,
|
|
|
|
* no-op on E/T.
|
|
|
|
*/
|
|
|
|
tstamp_bit_end = (priv->info->ptpegr_ts_bytes - 4) * 8;
|
|
|
|
/* Shift the 24-bit timestamp on E/T to be collected from 31:8.
|
|
|
|
* No-op on P/Q/R/S.
|
|
|
|
*/
|
|
|
|
tstamp_bit_end += 32 - priv->info->ptp_ts_bits;
|
|
|
|
tstamp_bit_start = tstamp_bit_end + priv->info->ptp_ts_bits - 1;
|
|
|
|
|
|
|
|
*ts = 0;
|
|
|
|
|
|
|
|
sja1105_unpack(packed_buf, ts, tstamp_bit_start, tstamp_bit_end,
|
|
|
|
priv->info->ptpegr_ts_bytes);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
#define rxtstamp_to_tagger(d) \
|
|
|
|
container_of((d), struct sja1105_tagger_data, rxtstamp_work)
|
|
|
|
#define tagger_to_sja1105(d) \
|
|
|
|
container_of((d), struct sja1105_private, tagger_data)
|
|
|
|
|
|
|
|
static void sja1105_rxtstamp_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct sja1105_tagger_data *tagger_data = rxtstamp_to_tagger(work);
|
|
|
|
struct sja1105_private *priv = tagger_to_sja1105(tagger_data);
|
|
|
|
struct sja1105_ptp_data *ptp_data = &priv->ptp_data;
|
|
|
|
struct dsa_switch *ds = priv->ds;
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
|
|
|
mutex_lock(&ptp_data->lock);
|
|
|
|
|
|
|
|
while ((skb = skb_dequeue(&tagger_data->skb_rxtstamp_queue)) != NULL) {
|
|
|
|
struct skb_shared_hwtstamps *shwt = skb_hwtstamps(skb);
|
|
|
|
u64 now, ts;
|
|
|
|
|
|
|
|
now = ptp_data->tstamp_cc.read(&ptp_data->tstamp_cc);
|
|
|
|
|
|
|
|
*shwt = (struct skb_shared_hwtstamps) {0};
|
|
|
|
|
|
|
|
ts = SJA1105_SKB_CB(skb)->meta_tstamp;
|
|
|
|
ts = sja1105_tstamp_reconstruct(ds, now, ts);
|
|
|
|
ts = timecounter_cyc2time(&ptp_data->tstamp_tc, ts);
|
|
|
|
|
|
|
|
shwt->hwtstamp = ns_to_ktime(ts);
|
|
|
|
netif_rx_ni(skb);
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_unlock(&ptp_data->lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Called from dsa_skb_defer_rx_timestamp */
|
|
|
|
bool sja1105_port_rxtstamp(struct dsa_switch *ds, int port,
|
|
|
|
struct sk_buff *skb, unsigned int type)
|
|
|
|
{
|
|
|
|
struct sja1105_private *priv = ds->priv;
|
|
|
|
struct sja1105_tagger_data *tagger_data = &priv->tagger_data;
|
|
|
|
|
|
|
|
if (!test_bit(SJA1105_HWTS_RX_EN, &tagger_data->state))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* We need to read the full PTP clock to reconstruct the Rx
|
|
|
|
* timestamp. For that we need a sleepable context.
|
|
|
|
*/
|
|
|
|
skb_queue_tail(&tagger_data->skb_rxtstamp_queue, skb);
|
|
|
|
schedule_work(&tagger_data->rxtstamp_work);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Called from dsa_skb_tx_timestamp. This callback is just to make DSA clone
|
|
|
|
* the skb and have it available in DSA_SKB_CB in the .port_deferred_xmit
|
|
|
|
* callback, where we will timestamp it synchronously.
|
|
|
|
*/
|
|
|
|
bool sja1105_port_txtstamp(struct dsa_switch *ds, int port,
|
|
|
|
struct sk_buff *skb, unsigned int type)
|
|
|
|
{
|
|
|
|
struct sja1105_private *priv = ds->priv;
|
|
|
|
struct sja1105_port *sp = &priv->ports[port];
|
|
|
|
|
|
|
|
if (!sp->hwts_tx_en)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-10-12 02:18:14 +03:00
|
|
|
int sja1105_ptp_reset(struct dsa_switch *ds)
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
{
|
2019-10-12 02:18:14 +03:00
|
|
|
struct sja1105_private *priv = ds->priv;
|
2019-10-12 02:18:15 +03:00
|
|
|
struct sja1105_ptp_data *ptp_data = &priv->ptp_data;
|
2019-10-12 02:18:16 +03:00
|
|
|
struct sja1105_ptp_cmd cmd = ptp_data->cmd;
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
int rc;
|
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
mutex_lock(&ptp_data->lock);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
|
|
|
cmd.resptp = 1;
|
|
|
|
dev_dbg(ds->dev, "Resetting PTP clock\n");
|
2019-10-12 02:18:14 +03:00
|
|
|
rc = priv->info->ptp_cmd(ds, &cmd);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
timecounter_init(&ptp_data->tstamp_tc, &ptp_data->tstamp_cc,
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
ktime_to_ns(ktime_get_real()));
|
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
mutex_unlock(&ptp_data->lock);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sja1105_ptp_gettime(struct ptp_clock_info *ptp,
|
|
|
|
struct timespec64 *ts)
|
|
|
|
{
|
2019-10-12 02:18:15 +03:00
|
|
|
struct sja1105_ptp_data *ptp_data = ptp_caps_to_data(ptp);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
u64 ns;
|
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
mutex_lock(&ptp_data->lock);
|
|
|
|
ns = timecounter_read(&ptp_data->tstamp_tc);
|
|
|
|
mutex_unlock(&ptp_data->lock);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
|
|
|
*ts = ns_to_timespec64(ns);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sja1105_ptp_settime(struct ptp_clock_info *ptp,
|
|
|
|
const struct timespec64 *ts)
|
|
|
|
{
|
2019-10-12 02:18:15 +03:00
|
|
|
struct sja1105_ptp_data *ptp_data = ptp_caps_to_data(ptp);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
u64 ns = timespec64_to_ns(ts);
|
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
mutex_lock(&ptp_data->lock);
|
|
|
|
timecounter_init(&ptp_data->tstamp_tc, &ptp_data->tstamp_cc, ns);
|
|
|
|
mutex_unlock(&ptp_data->lock);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sja1105_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
|
|
|
|
{
|
2019-10-12 02:18:15 +03:00
|
|
|
struct sja1105_ptp_data *ptp_data = ptp_caps_to_data(ptp);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
s64 clkrate;
|
|
|
|
|
|
|
|
clkrate = (s64)scaled_ppm * SJA1105_CC_MULT_NUM;
|
|
|
|
clkrate = div_s64(clkrate, SJA1105_CC_MULT_DEM);
|
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
mutex_lock(&ptp_data->lock);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
|
|
|
/* Force a readout to update the timer *before* changing its frequency.
|
|
|
|
*
|
|
|
|
* This way, its corrected time curve can at all times be modeled
|
|
|
|
* as a linear "A * x + B" function, where:
|
|
|
|
*
|
|
|
|
* - B are past frequency adjustments and offset shifts, all
|
|
|
|
* accumulated into the cycle_last variable.
|
|
|
|
*
|
|
|
|
* - A is the new frequency adjustments we're just about to set.
|
|
|
|
*
|
|
|
|
* Reading now makes B accumulate the correct amount of time,
|
|
|
|
* corrected at the old rate, before changing it.
|
|
|
|
*
|
|
|
|
* Hardware timestamps then become simple points on the curve and
|
|
|
|
* are approximated using the above function. This is still better
|
|
|
|
* than letting the switch take the timestamps using the hardware
|
|
|
|
* rate-corrected clock (PTPCLKVAL) - the comparison in this case would
|
|
|
|
* be that we're shifting the ruler at the same time as we're taking
|
|
|
|
* measurements with it.
|
|
|
|
*
|
|
|
|
* The disadvantage is that it's possible to receive timestamps when
|
|
|
|
* a frequency adjustment took place in the near past.
|
|
|
|
* In this case they will be approximated using the new ppb value
|
|
|
|
* instead of a compound function made of two segments (one at the old
|
|
|
|
* and the other at the new rate) - introducing some inaccuracy.
|
|
|
|
*/
|
2019-10-12 02:18:15 +03:00
|
|
|
timecounter_read(&ptp_data->tstamp_tc);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
ptp_data->tstamp_cc.mult = SJA1105_CC_MULT + clkrate;
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
mutex_unlock(&ptp_data->lock);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sja1105_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
|
|
|
|
{
|
2019-10-12 02:18:15 +03:00
|
|
|
struct sja1105_ptp_data *ptp_data = ptp_caps_to_data(ptp);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
mutex_lock(&ptp_data->lock);
|
|
|
|
timecounter_adjtime(&ptp_data->tstamp_tc, delta);
|
|
|
|
mutex_unlock(&ptp_data->lock);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u64 sja1105_ptptsclk_read(const struct cyclecounter *cc)
|
|
|
|
{
|
2019-10-12 02:18:15 +03:00
|
|
|
struct sja1105_ptp_data *ptp_data = cc_to_ptp_data(cc);
|
|
|
|
struct sja1105_private *priv = ptp_data_to_sja1105(ptp_data);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
const struct sja1105_regs *regs = priv->info->regs;
|
|
|
|
u64 ptptsclk = 0;
|
|
|
|
int rc;
|
|
|
|
|
2019-10-01 22:18:00 +03:00
|
|
|
rc = sja1105_xfer_u64(priv, SPI_READ, regs->ptptsclk, &ptptsclk);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
if (rc < 0)
|
|
|
|
dev_err_ratelimited(priv->ds->dev,
|
|
|
|
"failed to read ptp cycle counter: %d\n",
|
|
|
|
rc);
|
|
|
|
return ptptsclk;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sja1105_ptp_overflow_check(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct delayed_work *dw = to_delayed_work(work);
|
2019-10-12 02:18:15 +03:00
|
|
|
struct sja1105_ptp_data *ptp_data = dw_to_ptp_data(dw);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
struct timespec64 ts;
|
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
sja1105_ptp_gettime(&ptp_data->caps, &ts);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
schedule_delayed_work(&ptp_data->refresh_work,
|
|
|
|
SJA1105_REFRESH_INTERVAL);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
}
|
|
|
|
|
2019-10-12 02:18:14 +03:00
|
|
|
int sja1105_ptp_clock_register(struct dsa_switch *ds)
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
{
|
2019-10-12 02:18:14 +03:00
|
|
|
struct sja1105_private *priv = ds->priv;
|
2019-10-12 02:18:15 +03:00
|
|
|
struct sja1105_tagger_data *tagger_data = &priv->tagger_data;
|
|
|
|
struct sja1105_ptp_data *ptp_data = &priv->ptp_data;
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
|
|
|
/* Set up the cycle counter */
|
2019-10-12 02:18:15 +03:00
|
|
|
ptp_data->tstamp_cc = (struct cyclecounter) {
|
2019-10-12 02:18:13 +03:00
|
|
|
.read = sja1105_ptptsclk_read,
|
|
|
|
.mask = CYCLECOUNTER_MASK(64),
|
|
|
|
.shift = SJA1105_CC_SHIFT,
|
|
|
|
.mult = SJA1105_CC_MULT,
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
};
|
2019-10-12 02:18:15 +03:00
|
|
|
ptp_data->caps = (struct ptp_clock_info) {
|
2019-10-12 02:18:13 +03:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.name = "SJA1105 PHC",
|
|
|
|
.adjfine = sja1105_ptp_adjfine,
|
|
|
|
.adjtime = sja1105_ptp_adjtime,
|
|
|
|
.gettime64 = sja1105_ptp_gettime,
|
|
|
|
.settime64 = sja1105_ptp_settime,
|
|
|
|
.max_adj = SJA1105_MAX_ADJ_PPB,
|
|
|
|
};
|
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
skb_queue_head_init(&tagger_data->skb_rxtstamp_queue);
|
|
|
|
INIT_WORK(&tagger_data->rxtstamp_work, sja1105_rxtstamp_work);
|
|
|
|
spin_lock_init(&tagger_data->meta_lock);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
ptp_data->clock = ptp_clock_register(&ptp_data->caps, ds->dev);
|
|
|
|
if (IS_ERR_OR_NULL(ptp_data->clock))
|
|
|
|
return PTR_ERR(ptp_data->clock);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
INIT_DELAYED_WORK(&ptp_data->refresh_work, sja1105_ptp_overflow_check);
|
|
|
|
schedule_delayed_work(&ptp_data->refresh_work, SJA1105_REFRESH_INTERVAL);
|
2019-08-05 01:38:46 +03:00
|
|
|
|
2019-10-12 02:18:14 +03:00
|
|
|
return sja1105_ptp_reset(ds);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
}
|
|
|
|
|
2019-10-12 02:18:14 +03:00
|
|
|
void sja1105_ptp_clock_unregister(struct dsa_switch *ds)
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
{
|
2019-10-12 02:18:14 +03:00
|
|
|
struct sja1105_private *priv = ds->priv;
|
2019-10-12 02:18:15 +03:00
|
|
|
struct sja1105_ptp_data *ptp_data = &priv->ptp_data;
|
2019-10-12 02:18:14 +03:00
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
if (IS_ERR_OR_NULL(ptp_data->clock))
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
return;
|
|
|
|
|
2019-10-12 02:18:15 +03:00
|
|
|
cancel_work_sync(&priv->tagger_data.rxtstamp_work);
|
|
|
|
skb_queue_purge(&priv->tagger_data.skb_rxtstamp_queue);
|
|
|
|
cancel_delayed_work_sync(&ptp_data->refresh_work);
|
|
|
|
ptp_clock_unregister(ptp_data->clock);
|
|
|
|
ptp_data->clock = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
void sja1105_ptp_txtstamp_skb(struct dsa_switch *ds, int slot,
|
|
|
|
struct sk_buff *skb)
|
|
|
|
{
|
|
|
|
struct sja1105_private *priv = ds->priv;
|
|
|
|
struct sja1105_ptp_data *ptp_data = &priv->ptp_data;
|
|
|
|
struct skb_shared_hwtstamps shwt = {0};
|
|
|
|
u64 now, ts;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
|
|
|
|
|
|
|
|
mutex_lock(&ptp_data->lock);
|
|
|
|
|
|
|
|
now = ptp_data->tstamp_cc.read(&ptp_data->tstamp_cc);
|
|
|
|
|
|
|
|
rc = sja1105_ptpegr_ts_poll(ds, slot, &ts);
|
|
|
|
if (rc < 0) {
|
|
|
|
dev_err(ds->dev, "timed out polling for tstamp\n");
|
|
|
|
kfree_skb(skb);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
ts = sja1105_tstamp_reconstruct(ds, now, ts);
|
|
|
|
ts = timecounter_cyc2time(&ptp_data->tstamp_tc, ts);
|
|
|
|
|
|
|
|
shwt.hwtstamp = ns_to_ktime(ts);
|
|
|
|
skb_complete_tx_timestamp(skb, &shwt);
|
|
|
|
|
|
|
|
out:
|
|
|
|
mutex_unlock(&ptp_data->lock);
|
net: dsa: sja1105: Add support for the PTP clock
The design of this PHC driver is influenced by the switch's behavior
w.r.t. timestamping. It exposes two PTP counters, one free-running
(PTPTSCLK) and the other offset- and frequency-corrected in hardware
through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either
of these for frame timestamps.
However, the user manual warns that taking timestamps based on the
corrected clock is less than useful, as the switch can deliver corrupted
timestamps in a variety of circumstances.
Therefore, this PHC uses the free-running PTPTSCLK together with a
timecounter/cyclecounter structure that translates it into a software
time domain. Thus, the settime/adjtime and adjfine callbacks are
hardware no-ops.
The timestamps (introduced in a further patch) will also be translated
to the correct time domain before being handed over to the userspace PTP
stack.
The introduction of a second set of PHC operations that operate on the
hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
unavoidable, as the TTEthernet core uses the corrected PTP time domain.
However, the free-running counter + timecounter structure combination
will suffice for now, as the resulting timestamps yield a sub-50 ns
synchronization offset in steady state using linuxptp.
For this patch, in absence of frame timestamping, the operations of the
switch PHC were tested by syncing it to the system time as a local slave
clock with:
phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-08 15:04:34 +03:00
|
|
|
}
|