2017-11-24 15:00:32 +01:00
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// SPDX-License-Identifier: GPL-2.0
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2005-04-16 15:20:36 -07:00
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/*
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2009-03-26 15:24:01 +01:00
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* Machine check handler
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2005-04-16 15:20:36 -07:00
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*
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2012-07-20 11:15:04 +02:00
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* Copyright IBM Corp. 2000, 2009
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2009-03-26 15:24:01 +01:00
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* Author(s): Ingo Adlung <adlung@de.ibm.com>,
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* Martin Schwidefsky <schwidefsky@de.ibm.com>,
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* Cornelia Huck <cornelia.huck@de.ibm.com>,
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2005-04-16 15:20:36 -07:00
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*/
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2011-01-05 12:47:28 +01:00
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#include <linux/kernel_stat.h>
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2005-04-16 15:20:36 -07:00
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#include <linux/init.h>
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#include <linux/errno.h>
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2022-07-26 09:43:53 +02:00
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#include <linux/entry-common.h>
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2009-04-14 15:36:18 +02:00
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#include <linux/hardirq.h>
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2017-10-12 13:24:47 +02:00
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#include <linux/log2.h>
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2017-09-15 16:24:31 +02:00
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#include <linux/kprobes.h>
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2018-04-05 16:25:34 -07:00
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#include <linux/kmemleak.h>
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2006-05-01 12:16:14 -07:00
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#include <linux/time.h>
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2017-02-08 18:51:30 +01:00
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#include <linux/module.h>
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#include <linux/sched/signal.h>
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s390/nmi: use vector instruction macros instead of byte patterns
Use vector instruction macros instead of byte patterns to increase
readability. The generated code is nearly identical:
- 1e8: e7 0f 10 00 00 36 vlm %v0,%v15,0(%r1)
- 1ee: e7 0f 11 00 0c 36 vlm %v16,%v31,256(%r1)
+ 1e8: e7 0f 10 00 30 36 vlm %v0,%v15,0(%r1),3
+ 1ee: e7 0f 11 00 3c 36 vlm %v16,%v31,256(%r1),3
By using the VLM macro the alignment hint is automatically specified
too. Even though from a performance perspective it doesn't matter at
all for the machine check code, this shows yet another benefit when
using the macros.
Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2022-12-01 18:01:36 +01:00
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#include <linux/kvm_host.h>
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2017-02-09 15:20:23 -05:00
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#include <linux/export.h>
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2005-04-16 15:20:36 -07:00
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#include <asm/lowcore.h>
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2009-03-26 15:24:01 +01:00
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#include <asm/smp.h>
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2016-05-31 15:06:51 +02:00
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#include <asm/stp.h>
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2009-06-12 10:26:21 +02:00
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#include <asm/cputime.h>
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2009-03-26 15:24:01 +01:00
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#include <asm/nmi.h>
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#include <asm/crw.h>
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2014-10-06 17:53:53 +02:00
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#include <asm/switch_to.h>
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s390/nmi: fix vector register corruption
If a machine check happens, the machine has the vector facility installed
and the extended save area exists, the cpu will save vector register
contents into the extended save area. This is regardless of control
register 0 contents, which enables and disables the vector facility during
runtime.
On each machine check we should validate the vector registers. The current
code however tries to validate the registers only if the running task is
using vector registers in user space.
However even the current code is broken and causes vector register
corruption on machine checks, if user space uses them:
the prefix area contains a pointer (absolute address) to the machine check
extended save area. In order to save some space the save area was put into
an unused area of the second prefix page.
When validating vector register contents the code uses the absolute address
of the extended save area, which is wrong. Due to prefixing the vector
instructions will then access contents using absolute addresses instead
of real addresses, where the machine stored the contents.
If the above would work there is still the problem that register validition
would only happen if user space uses vector registers. If kernel space uses
them also, this may also lead to vector register content corruption:
if the kernel makes use of vector instructions, but the current running
user space context does not, the machine check handler will validate
floating point registers instead of vector registers.
Given the fact that writing to a floating point register may change the
upper halve of the corresponding vector register, we also experience vector
register corruption in this case.
Fix all of these issues, and always validate vector registers on each
machine check, if the machine has the vector facility installed and the
extended save area is defined.
Cc: <stable@vger.kernel.org> # 4.1+
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-07-07 08:40:49 +02:00
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#include <asm/ctl_reg.h>
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2017-06-07 11:30:42 +02:00
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#include <asm/asm-offsets.h>
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2022-05-04 08:23:51 +02:00
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#include <asm/pai.h>
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s390/nmi: use vector instruction macros instead of byte patterns
Use vector instruction macros instead of byte patterns to increase
readability. The generated code is nearly identical:
- 1e8: e7 0f 10 00 00 36 vlm %v0,%v15,0(%r1)
- 1ee: e7 0f 11 00 0c 36 vlm %v16,%v31,256(%r1)
+ 1e8: e7 0f 10 00 30 36 vlm %v0,%v15,0(%r1),3
+ 1ee: e7 0f 11 00 3c 36 vlm %v16,%v31,256(%r1),3
By using the VLM macro the alignment hint is automatically specified
too. Even though from a performance perspective it doesn't matter at
all for the machine check code, this shows yet another benefit when
using the macros.
Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2022-12-01 18:01:36 +01:00
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#include <asm/vx-insn.h>
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2005-04-16 15:20:36 -07:00
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2005-06-25 14:55:30 -07:00
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struct mcck_struct {
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2015-10-12 13:04:12 +02:00
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unsigned int kill_task : 1;
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unsigned int channel_report : 1;
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unsigned int warning : 1;
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2015-10-09 13:48:03 +02:00
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unsigned int stp_queue : 1;
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2015-10-12 13:00:39 +02:00
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unsigned long mcck_code;
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2005-06-25 14:55:30 -07:00
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};
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static DEFINE_PER_CPU(struct mcck_struct, cpu_mcck);
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2017-10-12 13:24:47 +02:00
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static struct kmem_cache *mcesa_cache;
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static unsigned long mcesa_origin_lc;
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static inline int nmi_needs_mcesa(void)
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{
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return MACHINE_HAS_VX || MACHINE_HAS_GS;
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}
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static inline unsigned long nmi_get_mcesa_size(void)
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{
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if (MACHINE_HAS_GS)
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return MCESA_MAX_SIZE;
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return MCESA_MIN_SIZE;
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}
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/*
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* The initial machine check extended save area for the boot CPU.
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2021-12-10 16:32:11 +01:00
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* It will be replaced on the boot CPU reinit with an allocated
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* structure. The structure is required for machine check happening
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* early in the boot process.
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2017-10-12 13:24:47 +02:00
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*/
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2022-08-13 19:45:21 +02:00
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static struct mcesa boot_mcesa __aligned(MCESA_MAX_SIZE);
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2017-10-12 13:24:47 +02:00
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2021-12-10 16:32:11 +01:00
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void __init nmi_alloc_mcesa_early(u64 *mcesad)
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2017-10-12 13:24:47 +02:00
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{
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if (!nmi_needs_mcesa())
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return;
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2021-12-10 16:32:11 +01:00
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*mcesad = __pa(&boot_mcesa);
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2017-10-12 13:24:47 +02:00
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if (MACHINE_HAS_GS)
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2021-12-10 16:32:11 +01:00
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*mcesad |= ilog2(MCESA_MAX_SIZE);
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2017-10-12 13:24:47 +02:00
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}
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2021-12-10 16:32:11 +01:00
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static void __init nmi_alloc_cache(void)
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2017-10-12 13:24:47 +02:00
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{
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2021-12-10 16:32:11 +01:00
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unsigned long size;
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2017-10-12 13:24:47 +02:00
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if (!nmi_needs_mcesa())
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2021-12-10 16:32:11 +01:00
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return;
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2017-10-12 13:24:47 +02:00
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size = nmi_get_mcesa_size();
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if (size > MCESA_MIN_SIZE)
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mcesa_origin_lc = ilog2(size);
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/* create slab cache for the machine-check-extended-save-areas */
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mcesa_cache = kmem_cache_create("nmi_save_areas", size, size, 0, NULL);
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if (!mcesa_cache)
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panic("Couldn't create nmi save area cache");
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}
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2021-12-10 16:32:11 +01:00
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int __ref nmi_alloc_mcesa(u64 *mcesad)
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2017-10-12 13:24:47 +02:00
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{
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unsigned long origin;
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2021-12-10 16:32:11 +01:00
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*mcesad = 0;
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2017-10-12 13:24:47 +02:00
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if (!nmi_needs_mcesa())
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return 0;
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2021-12-10 16:32:11 +01:00
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if (!mcesa_cache)
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nmi_alloc_cache();
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2017-10-12 13:24:47 +02:00
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origin = (unsigned long) kmem_cache_alloc(mcesa_cache, GFP_KERNEL);
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if (!origin)
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return -ENOMEM;
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/* The pointer is stored with mcesa_bits ORed in */
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kmemleak_not_leak((void *) origin);
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2021-12-10 16:32:11 +01:00
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*mcesad = __pa(origin) | mcesa_origin_lc;
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2017-10-12 13:24:47 +02:00
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return 0;
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}
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2021-12-10 16:32:11 +01:00
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void nmi_free_mcesa(u64 *mcesad)
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2017-10-12 13:24:47 +02:00
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{
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if (!nmi_needs_mcesa())
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return;
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2021-12-10 16:32:11 +01:00
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kmem_cache_free(mcesa_cache, __va(*mcesad & MCESA_ORIGIN_MASK));
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2017-10-12 13:24:47 +02:00
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}
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2005-06-25 14:55:30 -07:00
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2017-09-15 16:24:31 +02:00
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static notrace void s390_handle_damage(void)
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2009-03-26 15:24:01 +01:00
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{
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2017-09-15 16:24:31 +02:00
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smp_emergency_stop();
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2019-04-30 12:33:45 +02:00
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disabled_wait();
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2009-03-26 15:24:01 +01:00
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while (1);
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}
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2017-09-15 16:24:31 +02:00
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NOKPROBE_SYMBOL(s390_handle_damage);
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2009-03-26 15:24:01 +01:00
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2005-04-16 15:20:36 -07:00
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/*
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2020-11-21 11:14:56 +01:00
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* Main machine check handler function. Will be called with interrupts disabled
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* and machine checks enabled.
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2005-04-16 15:20:36 -07:00
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*/
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2020-11-21 11:14:56 +01:00
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void __s390_handle_mcck(void)
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2005-04-16 15:20:36 -07:00
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{
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2005-06-25 14:55:30 -07:00
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struct mcck_struct mcck;
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2005-04-16 15:20:36 -07:00
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2005-06-25 14:55:30 -07:00
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/*
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* Disable machine checks and get the current state of accumulated
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* machine checks. Afterwards delete the old state and enable machine
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* checks again.
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*/
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local_mcck_disable();
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2014-11-28 15:40:57 +01:00
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mcck = *this_cpu_ptr(&cpu_mcck);
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memset(this_cpu_ptr(&cpu_mcck), 0, sizeof(mcck));
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2005-06-25 14:55:30 -07:00
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local_mcck_enable();
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2005-04-16 15:20:36 -07:00
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2005-06-25 14:55:30 -07:00
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if (mcck.channel_report)
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2009-03-26 15:24:01 +01:00
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crw_handle_channel_report();
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2009-03-26 15:24:02 +01:00
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/*
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* A warning may remain for a prolonged period on the bare iron.
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* (actually until the machine is powered off, or the problem is gone)
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* So we just stop listening for the WARNING MCH and avoid continuously
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* being interrupted. One caveat is however, that we must do this per
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* processor and cannot use the smp version of ctl_clear_bit().
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* On VM we only get one interrupt per virtally presented machinecheck.
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* Though one suffices, we may get one interrupt per (virtual) cpu.
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*/
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2005-06-25 14:55:30 -07:00
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if (mcck.warning) { /* WARNING pending ? */
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2005-04-16 15:20:36 -07:00
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static int mchchk_wng_posted = 0;
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2009-03-26 15:24:02 +01:00
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/* Use single cpu clear, as we cannot handle smp here. */
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2005-04-16 15:20:36 -07:00
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__ctl_clear_bit(14, 24); /* Disable WARNING MCH */
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if (xchg(&mchchk_wng_posted, 1) == 0)
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2006-10-02 02:19:00 -07:00
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kill_cad_pid(SIGPWR, 1);
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2005-04-16 15:20:36 -07:00
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}
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2015-10-09 13:48:03 +02:00
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if (mcck.stp_queue)
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stp_queue_work();
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2005-06-25 14:55:30 -07:00
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if (mcck.kill_task) {
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local_irq_enable();
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printk(KERN_EMERG "mcck: Terminating task because of machine "
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2015-10-12 13:00:39 +02:00
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"malfunction (code 0x%016lx).\n", mcck.mcck_code);
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2005-06-25 14:55:30 -07:00
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printk(KERN_EMERG "mcck: task: %s, pid: %d.\n",
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current->comm, current->pid);
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2021-06-28 14:52:01 -05:00
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make_task_dead(SIGSEGV);
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2005-06-25 14:55:30 -07:00
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}
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}
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2022-05-04 08:23:51 +02:00
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void noinstr s390_handle_mcck(struct pt_regs *regs)
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2020-11-21 11:14:56 +01:00
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{
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trace_hardirqs_off();
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2022-05-04 08:23:51 +02:00
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pai_kernel_enter(regs);
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2020-11-21 11:14:56 +01:00
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__s390_handle_mcck();
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2022-05-04 08:23:51 +02:00
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pai_kernel_exit(regs);
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2020-11-21 11:14:56 +01:00
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trace_hardirqs_on();
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}
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2005-06-25 14:55:30 -07:00
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/*
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2022-11-27 09:45:26 +01:00
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* returns 0 if register contents could be validated
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2005-06-25 14:55:30 -07:00
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* returns 1 otherwise
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*/
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2022-11-27 09:45:26 +01:00
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static int notrace s390_validate_registers(union mci mci)
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2005-06-25 14:55:30 -07:00
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{
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2021-06-18 08:17:18 +02:00
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struct mcesa *mcesa;
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void *fpt_save_area;
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2017-10-12 13:24:45 +02:00
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union ctlreg2 cr2;
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2005-06-25 14:55:30 -07:00
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int kill_task;
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2021-06-18 08:17:18 +02:00
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u64 zero;
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2005-06-25 14:55:30 -07:00
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kill_task = 0;
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2021-06-18 08:17:18 +02:00
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zero = 0;
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2009-03-26 15:24:01 +01:00
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2022-11-27 09:45:26 +01:00
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if (!mci.gr || !mci.fp)
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2005-06-25 14:55:30 -07:00
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kill_task = 1;
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2021-06-18 08:17:18 +02:00
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fpt_save_area = &S390_lowcore.floating_pt_save_area;
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2015-10-12 13:00:39 +02:00
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if (!mci.fc) {
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2022-11-27 09:45:26 +01:00
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kill_task = 1;
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2021-06-18 08:17:18 +02:00
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asm volatile(
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" lfpc %0\n"
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:
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: "Q" (zero));
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} else {
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asm volatile(
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" lfpc %0\n"
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:
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: "Q" (S390_lowcore.fpt_creg_save_area));
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2016-12-13 12:42:07 +01:00
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}
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2015-02-12 13:08:27 +01:00
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2021-11-25 19:59:16 +01:00
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mcesa = __va(S390_lowcore.mcesad & MCESA_ORIGIN_MASK);
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2021-06-18 08:17:18 +02:00
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if (!MACHINE_HAS_VX) {
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/* Validate floating point registers */
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asm volatile(
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" ld 0,0(%0)\n"
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" ld 1,8(%0)\n"
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" ld 2,16(%0)\n"
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" ld 3,24(%0)\n"
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" ld 4,32(%0)\n"
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" ld 5,40(%0)\n"
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" ld 6,48(%0)\n"
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" ld 7,56(%0)\n"
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" ld 8,64(%0)\n"
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" ld 9,72(%0)\n"
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" ld 10,80(%0)\n"
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" ld 11,88(%0)\n"
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" ld 12,96(%0)\n"
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" ld 13,104(%0)\n"
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|
|
|
" ld 14,112(%0)\n"
|
|
|
|
" ld 15,120(%0)\n"
|
|
|
|
:
|
|
|
|
: "a" (fpt_save_area)
|
|
|
|
: "memory");
|
|
|
|
} else {
|
|
|
|
/* Validate vector registers */
|
|
|
|
union ctlreg0 cr0;
|
|
|
|
|
2022-01-17 18:40:32 +01:00
|
|
|
/*
|
|
|
|
* The vector validity must only be checked if not running a
|
|
|
|
* KVM guest. For KVM guests the machine check is forwarded by
|
|
|
|
* KVM and it is the responsibility of the guest to take
|
|
|
|
* appropriate actions. The host vector or FPU values have been
|
|
|
|
* saved by KVM and will be restored by KVM.
|
|
|
|
*/
|
2022-11-27 09:45:26 +01:00
|
|
|
if (!mci.vr && !test_cpu_flag(CIF_MCCK_GUEST))
|
|
|
|
kill_task = 1;
|
2021-06-18 08:17:18 +02:00
|
|
|
cr0.val = S390_lowcore.cregs_save_area[0];
|
|
|
|
cr0.afp = cr0.vx = 1;
|
|
|
|
__ctl_load(cr0.val, 0, 0);
|
|
|
|
asm volatile(
|
|
|
|
" la 1,%0\n"
|
s390/nmi: use vector instruction macros instead of byte patterns
Use vector instruction macros instead of byte patterns to increase
readability. The generated code is nearly identical:
- 1e8: e7 0f 10 00 00 36 vlm %v0,%v15,0(%r1)
- 1ee: e7 0f 11 00 0c 36 vlm %v16,%v31,256(%r1)
+ 1e8: e7 0f 10 00 30 36 vlm %v0,%v15,0(%r1),3
+ 1ee: e7 0f 11 00 3c 36 vlm %v16,%v31,256(%r1),3
By using the VLM macro the alignment hint is automatically specified
too. Even though from a performance perspective it doesn't matter at
all for the machine check code, this shows yet another benefit when
using the macros.
Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2022-12-01 18:01:36 +01:00
|
|
|
" VLM 0,15,0,1\n"
|
|
|
|
" VLM 16,31,256,1\n"
|
2021-06-18 08:17:18 +02:00
|
|
|
:
|
|
|
|
: "Q" (*(struct vx_array *)mcesa->vector_save_area)
|
|
|
|
: "1");
|
|
|
|
__ctl_load(S390_lowcore.cregs_save_area[0], 0, 0);
|
2014-10-06 17:53:53 +02:00
|
|
|
}
|
2021-06-18 08:17:18 +02:00
|
|
|
/* Validate access registers */
|
|
|
|
asm volatile(
|
|
|
|
" lam 0,15,0(%0)\n"
|
|
|
|
:
|
|
|
|
: "a" (&S390_lowcore.access_regs_save_area)
|
|
|
|
: "memory");
|
2022-11-27 09:45:26 +01:00
|
|
|
if (!mci.ar)
|
2005-06-25 14:55:30 -07:00
|
|
|
kill_task = 1;
|
2021-06-18 08:17:18 +02:00
|
|
|
/* Validate guarded storage registers */
|
2017-10-12 13:24:45 +02:00
|
|
|
cr2.val = S390_lowcore.cregs_save_area[2];
|
|
|
|
if (cr2.gse) {
|
2017-10-12 13:24:48 +02:00
|
|
|
if (!mci.gs) {
|
2016-01-26 14:10:34 +01:00
|
|
|
/*
|
2022-01-13 11:44:19 +01:00
|
|
|
* 2 cases:
|
|
|
|
* - machine check in kernel or userspace
|
|
|
|
* - machine check while running SIE (KVM guest)
|
|
|
|
* For kernel or userspace the userspace values of
|
|
|
|
* guarded storage control can not be recreated, the
|
|
|
|
* process must be terminated.
|
|
|
|
* For SIE the guest values of guarded storage can not
|
|
|
|
* be recreated. This is either due to a bug or due to
|
|
|
|
* GS being disabled in the guest. The guest will be
|
|
|
|
* notified by KVM code and the guests machine check
|
|
|
|
* handling must take care of this. The host values
|
|
|
|
* are saved by KVM and are not affected.
|
2016-01-26 14:10:34 +01:00
|
|
|
*/
|
2022-01-13 11:44:19 +01:00
|
|
|
if (!test_cpu_flag(CIF_MCCK_GUEST))
|
|
|
|
kill_task = 1;
|
2021-06-18 08:17:18 +02:00
|
|
|
} else {
|
|
|
|
load_gs_cb((struct gs_cb *)mcesa->guarded_storage_save_area);
|
2017-10-12 13:24:48 +02:00
|
|
|
}
|
2016-01-26 14:10:34 +01:00
|
|
|
}
|
2021-06-18 08:17:18 +02:00
|
|
|
/*
|
|
|
|
* The getcpu vdso syscall reads CPU number from the programmable
|
|
|
|
* field of the TOD clock. Disregard the TOD programmable register
|
|
|
|
* validity bit and load the CPU number into the TOD programmable
|
|
|
|
* field unconditionally.
|
|
|
|
*/
|
|
|
|
set_tod_programmable_field(raw_smp_processor_id());
|
|
|
|
/* Validate clock comparator register */
|
|
|
|
set_clock_comparator(S390_lowcore.clock_comparator);
|
2005-06-25 14:55:30 -07:00
|
|
|
|
2015-10-12 13:00:39 +02:00
|
|
|
if (!mci.ms || !mci.pm || !mci.ia)
|
2005-06-25 14:55:30 -07:00
|
|
|
kill_task = 1;
|
|
|
|
|
|
|
|
return kill_task;
|
|
|
|
}
|
2021-06-18 08:17:18 +02:00
|
|
|
NOKPROBE_SYMBOL(s390_validate_registers);
|
2005-06-25 14:55:30 -07:00
|
|
|
|
KVM: s390: Backup the guest's machine check info
When a machine check happens in the guest, related mcck info (mcic,
external damage code, ...) is stored in the vcpu's lowcore on the host.
Then the machine check handler's low-level part is executed, followed
by the high-level part.
If the high-level part's execution is interrupted by a new machine check
happening on the same vcpu on the host, the mcck info in the lowcore is
overwritten with the new machine check's data.
If the high-level part's execution is scheduled to a different cpu,
the mcck info in the lowcore is uncertain.
Therefore, for both cases, the further reinjection to the guest will use
the wrong data.
Let's backup the mcck info in the lowcore to the sie page
for further reinjection, so that the right data will be used.
Add new member into struct sie_page to store related machine check's
info of mcic, failing storage address and external damage code.
Signed-off-by: QingFeng Hao <haoqf@linux.vnet.ibm.com>
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-06-07 11:41:19 +02:00
|
|
|
/*
|
|
|
|
* Backup the guest's machine check info to its description block
|
|
|
|
*/
|
|
|
|
static void notrace s390_backup_mcck_info(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
struct mcck_volatile_info *mcck_backup;
|
|
|
|
struct sie_page *sie_page;
|
|
|
|
|
|
|
|
/* r14 contains the sie block, which was set in sie64a */
|
|
|
|
struct kvm_s390_sie_block *sie_block =
|
|
|
|
(struct kvm_s390_sie_block *) regs->gprs[14];
|
|
|
|
|
|
|
|
if (sie_block == NULL)
|
|
|
|
/* Something's seriously wrong, stop system. */
|
|
|
|
s390_handle_damage();
|
|
|
|
|
|
|
|
sie_page = container_of(sie_block, struct sie_page, sie_block);
|
|
|
|
mcck_backup = &sie_page->mcck_info;
|
|
|
|
mcck_backup->mcic = S390_lowcore.mcck_interruption_code &
|
|
|
|
~(MCCK_CODE_CP | MCCK_CODE_EXT_DAMAGE);
|
|
|
|
mcck_backup->ext_damage_code = S390_lowcore.external_damage_code;
|
|
|
|
mcck_backup->failing_storage_address
|
|
|
|
= S390_lowcore.failing_storage_address;
|
|
|
|
}
|
2017-09-15 16:24:31 +02:00
|
|
|
NOKPROBE_SYMBOL(s390_backup_mcck_info);
|
KVM: s390: Backup the guest's machine check info
When a machine check happens in the guest, related mcck info (mcic,
external damage code, ...) is stored in the vcpu's lowcore on the host.
Then the machine check handler's low-level part is executed, followed
by the high-level part.
If the high-level part's execution is interrupted by a new machine check
happening on the same vcpu on the host, the mcck info in the lowcore is
overwritten with the new machine check's data.
If the high-level part's execution is scheduled to a different cpu,
the mcck info in the lowcore is uncertain.
Therefore, for both cases, the further reinjection to the guest will use
the wrong data.
Let's backup the mcck info in the lowcore to the sie page
for further reinjection, so that the right data will be used.
Add new member into struct sie_page to store related machine check's
info of mcic, failing storage address and external damage code.
Signed-off-by: QingFeng Hao <haoqf@linux.vnet.ibm.com>
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-06-07 11:41:19 +02:00
|
|
|
|
2006-04-27 18:40:23 -07:00
|
|
|
#define MAX_IPD_COUNT 29
|
2006-05-01 12:16:14 -07:00
|
|
|
#define MAX_IPD_TIME (5 * 60 * USEC_PER_SEC) /* 5 minutes */
|
2006-04-27 18:40:23 -07:00
|
|
|
|
2009-03-26 15:24:01 +01:00
|
|
|
#define ED_STP_ISLAND 6 /* External damage STP island check */
|
|
|
|
#define ED_STP_SYNC 7 /* External damage STP sync check */
|
|
|
|
|
2017-06-07 11:30:42 +02:00
|
|
|
#define MCCK_CODE_NO_GUEST (MCCK_CODE_CP | MCCK_CODE_EXT_DAMAGE)
|
|
|
|
|
2005-06-25 14:55:30 -07:00
|
|
|
/*
|
|
|
|
* machine check handler.
|
|
|
|
*/
|
2020-02-20 12:09:36 +01:00
|
|
|
int notrace s390_do_machine_check(struct pt_regs *regs)
|
2005-06-25 14:55:30 -07:00
|
|
|
{
|
2009-03-26 15:24:01 +01:00
|
|
|
static int ipd_count;
|
2006-04-27 18:40:23 -07:00
|
|
|
static DEFINE_SPINLOCK(ipd_lock);
|
|
|
|
static unsigned long long last_ipd;
|
2009-03-26 15:24:01 +01:00
|
|
|
struct mcck_struct *mcck;
|
2006-04-27 18:40:23 -07:00
|
|
|
unsigned long long tmp;
|
2022-07-26 09:43:53 +02:00
|
|
|
irqentry_state_t irq_state;
|
2015-10-12 13:00:39 +02:00
|
|
|
union mci mci;
|
2017-06-07 11:30:42 +02:00
|
|
|
unsigned long mcck_dam_code;
|
2020-02-20 12:09:36 +01:00
|
|
|
int mcck_pending = 0;
|
2005-06-25 14:55:30 -07:00
|
|
|
|
2022-07-26 09:43:53 +02:00
|
|
|
irq_state = irqentry_nmi_enter(regs);
|
2020-11-21 11:14:56 +01:00
|
|
|
|
|
|
|
if (user_mode(regs))
|
|
|
|
update_timer_mcck();
|
2013-01-02 15:18:18 +01:00
|
|
|
inc_irq_stat(NMI_NMI);
|
2015-10-12 13:00:39 +02:00
|
|
|
mci.val = S390_lowcore.mcck_interruption_code;
|
s390: Replace __get_cpu_var uses
__get_cpu_var() is used for multiple purposes in the kernel source. One of
them is address calculation via the form &__get_cpu_var(x). This calculates
the address for the instance of the percpu variable of the current processor
based on an offset.
Other use cases are for storing and retrieving data from the current
processors percpu area. __get_cpu_var() can be used as an lvalue when
writing data or on the right side of an assignment.
__get_cpu_var() is defined as :
#define __get_cpu_var(var) (*this_cpu_ptr(&(var)))
__get_cpu_var() always only does an address determination. However, store
and retrieve operations could use a segment prefix (or global register on
other platforms) to avoid the address calculation.
this_cpu_write() and this_cpu_read() can directly take an offset into a
percpu area and use optimized assembly code to read and write per cpu
variables.
This patch converts __get_cpu_var into either an explicit address
calculation using this_cpu_ptr() or into a use of this_cpu operations that
use the offset. Thereby address calculations are avoided and less registers
are used when code is generated.
At the end of the patch set all uses of __get_cpu_var have been removed so
the macro is removed too.
The patch set includes passes over all arches as well. Once these operations
are used throughout then specialized macros can be defined in non -x86
arches as well in order to optimize per cpu access by f.e. using a global
register that may be set to the per cpu base.
Transformations done to __get_cpu_var()
1. Determine the address of the percpu instance of the current processor.
DEFINE_PER_CPU(int, y);
int *x = &__get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(&y);
2. Same as #1 but this time an array structure is involved.
DEFINE_PER_CPU(int, y[20]);
int *x = __get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(y);
3. Retrieve the content of the current processors instance of a per cpu
variable.
DEFINE_PER_CPU(int, y);
int x = __get_cpu_var(y)
Converts to
int x = __this_cpu_read(y);
4. Retrieve the content of a percpu struct
DEFINE_PER_CPU(struct mystruct, y);
struct mystruct x = __get_cpu_var(y);
Converts to
memcpy(&x, this_cpu_ptr(&y), sizeof(x));
5. Assignment to a per cpu variable
DEFINE_PER_CPU(int, y)
__get_cpu_var(y) = x;
Converts to
this_cpu_write(y, x);
6. Increment/Decrement etc of a per cpu variable
DEFINE_PER_CPU(int, y);
__get_cpu_var(y)++
Converts to
this_cpu_inc(y)
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
CC: linux390@de.ibm.com
Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2014-08-17 12:30:45 -05:00
|
|
|
mcck = this_cpu_ptr(&cpu_mcck);
|
2005-06-25 14:55:30 -07:00
|
|
|
|
2017-06-07 11:30:42 +02:00
|
|
|
/*
|
|
|
|
* Reinject the instruction processing damages' machine checks
|
|
|
|
* including Delayed Access Exception into the guest
|
|
|
|
* instead of damaging the host if they happen in the guest.
|
|
|
|
*/
|
|
|
|
if (mci.pd && !test_cpu_flag(CIF_MCCK_GUEST)) {
|
2015-10-12 13:00:39 +02:00
|
|
|
if (mci.b) {
|
2005-06-25 14:55:30 -07:00
|
|
|
/* Processing backup -> verify if we can survive this */
|
|
|
|
u64 z_mcic, o_mcic, t_mcic;
|
|
|
|
z_mcic = (1ULL<<63 | 1ULL<<59 | 1ULL<<29);
|
|
|
|
o_mcic = (1ULL<<43 | 1ULL<<42 | 1ULL<<41 | 1ULL<<40 |
|
|
|
|
1ULL<<36 | 1ULL<<35 | 1ULL<<34 | 1ULL<<32 |
|
|
|
|
1ULL<<30 | 1ULL<<21 | 1ULL<<20 | 1ULL<<17 |
|
|
|
|
1ULL<<16);
|
2015-10-12 13:00:39 +02:00
|
|
|
t_mcic = mci.val;
|
2005-06-25 14:55:30 -07:00
|
|
|
|
|
|
|
if (((t_mcic & z_mcic) != 0) ||
|
|
|
|
((t_mcic & o_mcic) != o_mcic)) {
|
2015-10-12 12:39:09 +02:00
|
|
|
s390_handle_damage();
|
2005-06-25 14:55:30 -07:00
|
|
|
}
|
2006-04-27 18:40:23 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Nullifying exigent condition, therefore we might
|
|
|
|
* retry this instruction.
|
|
|
|
*/
|
|
|
|
spin_lock(&ipd_lock);
|
2013-01-30 09:49:40 +01:00
|
|
|
tmp = get_tod_clock();
|
2006-04-27 18:40:23 -07:00
|
|
|
if (((tmp - last_ipd) >> 12) < MAX_IPD_TIME)
|
|
|
|
ipd_count++;
|
|
|
|
else
|
|
|
|
ipd_count = 1;
|
|
|
|
last_ipd = tmp;
|
|
|
|
if (ipd_count == MAX_IPD_COUNT)
|
2015-10-12 12:39:09 +02:00
|
|
|
s390_handle_damage();
|
2006-04-27 18:40:23 -07:00
|
|
|
spin_unlock(&ipd_lock);
|
2009-03-26 15:24:01 +01:00
|
|
|
} else {
|
2005-06-25 14:55:30 -07:00
|
|
|
/* Processing damage -> stopping machine */
|
2015-10-12 12:39:09 +02:00
|
|
|
s390_handle_damage();
|
2005-06-25 14:55:30 -07:00
|
|
|
}
|
|
|
|
}
|
2022-11-27 09:45:26 +01:00
|
|
|
if (s390_validate_registers(mci)) {
|
|
|
|
if (!user_mode(regs))
|
|
|
|
s390_handle_damage();
|
2016-08-22 14:40:06 +02:00
|
|
|
/*
|
|
|
|
* Couldn't restore all register contents for the
|
|
|
|
* user space process -> mark task for termination.
|
|
|
|
*/
|
|
|
|
mcck->kill_task = 1;
|
|
|
|
mcck->mcck_code = mci.val;
|
2020-02-20 12:09:36 +01:00
|
|
|
mcck_pending = 1;
|
2005-06-25 14:55:30 -07:00
|
|
|
}
|
KVM: s390: Backup the guest's machine check info
When a machine check happens in the guest, related mcck info (mcic,
external damage code, ...) is stored in the vcpu's lowcore on the host.
Then the machine check handler's low-level part is executed, followed
by the high-level part.
If the high-level part's execution is interrupted by a new machine check
happening on the same vcpu on the host, the mcck info in the lowcore is
overwritten with the new machine check's data.
If the high-level part's execution is scheduled to a different cpu,
the mcck info in the lowcore is uncertain.
Therefore, for both cases, the further reinjection to the guest will use
the wrong data.
Let's backup the mcck info in the lowcore to the sie page
for further reinjection, so that the right data will be used.
Add new member into struct sie_page to store related machine check's
info of mcic, failing storage address and external damage code.
Signed-off-by: QingFeng Hao <haoqf@linux.vnet.ibm.com>
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-06-07 11:41:19 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Backup the machine check's info if it happens when the guest
|
|
|
|
* is running.
|
|
|
|
*/
|
|
|
|
if (test_cpu_flag(CIF_MCCK_GUEST))
|
|
|
|
s390_backup_mcck_info(regs);
|
|
|
|
|
2015-10-12 13:00:39 +02:00
|
|
|
if (mci.cd) {
|
2007-02-05 21:18:19 +01:00
|
|
|
/* Timing facility damage */
|
2015-10-12 12:39:09 +02:00
|
|
|
s390_handle_damage();
|
2007-02-05 21:18:19 +01:00
|
|
|
}
|
2015-10-12 13:00:39 +02:00
|
|
|
if (mci.ed && mci.ec) {
|
2007-02-05 21:18:19 +01:00
|
|
|
/* External damage */
|
2008-07-14 09:58:56 +02:00
|
|
|
if (S390_lowcore.external_damage_code & (1U << ED_STP_SYNC))
|
2015-10-09 13:48:03 +02:00
|
|
|
mcck->stp_queue |= stp_sync_check();
|
2008-07-14 09:58:56 +02:00
|
|
|
if (S390_lowcore.external_damage_code & (1U << ED_STP_ISLAND))
|
2015-10-09 13:48:03 +02:00
|
|
|
mcck->stp_queue |= stp_island_check();
|
2020-02-20 12:09:36 +01:00
|
|
|
mcck_pending = 1;
|
2007-02-05 21:18:19 +01:00
|
|
|
}
|
2017-06-07 11:30:42 +02:00
|
|
|
|
2015-10-12 13:00:39 +02:00
|
|
|
if (mci.cp) {
|
2005-06-25 14:55:30 -07:00
|
|
|
/* Channel report word pending */
|
|
|
|
mcck->channel_report = 1;
|
2020-02-20 12:09:36 +01:00
|
|
|
mcck_pending = 1;
|
2005-06-25 14:55:30 -07:00
|
|
|
}
|
2015-10-12 13:00:39 +02:00
|
|
|
if (mci.w) {
|
2005-06-25 14:55:30 -07:00
|
|
|
/* Warning pending */
|
|
|
|
mcck->warning = 1;
|
2020-02-20 12:09:36 +01:00
|
|
|
mcck_pending = 1;
|
2005-06-25 14:55:30 -07:00
|
|
|
}
|
2017-06-07 11:30:42 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If there are only Channel Report Pending and External Damage
|
|
|
|
* machine checks, they will not be reinjected into the guest
|
|
|
|
* because they refer to host conditions only.
|
|
|
|
*/
|
|
|
|
mcck_dam_code = (mci.val & MCIC_SUBCLASS_MASK);
|
|
|
|
if (test_cpu_flag(CIF_MCCK_GUEST) &&
|
|
|
|
(mcck_dam_code & MCCK_CODE_NO_GUEST) != mcck_dam_code) {
|
|
|
|
/* Set exit reason code for host's later handling */
|
|
|
|
*((long *)(regs->gprs[15] + __SF_SIE_REASON)) = -EINTR;
|
|
|
|
}
|
|
|
|
clear_cpu_flag(CIF_MCCK_GUEST);
|
2020-02-20 12:09:36 +01:00
|
|
|
|
|
|
|
if (user_mode(regs) && mcck_pending) {
|
2022-07-26 09:43:53 +02:00
|
|
|
irqentry_nmi_exit(regs, irq_state);
|
2020-02-20 12:09:36 +01:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mcck_pending)
|
|
|
|
schedule_mcck_handler();
|
|
|
|
|
2022-07-26 09:43:53 +02:00
|
|
|
irqentry_nmi_exit(regs, irq_state);
|
2020-02-20 12:09:36 +01:00
|
|
|
return 0;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
2017-09-15 16:24:31 +02:00
|
|
|
NOKPROBE_SYMBOL(s390_do_machine_check);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2009-03-26 15:24:01 +01:00
|
|
|
static int __init machine_check_init(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-02-05 21:18:19 +01:00
|
|
|
ctl_set_bit(14, 25); /* enable external damage MCH */
|
2009-03-26 15:24:01 +01:00
|
|
|
ctl_set_bit(14, 27); /* enable system recovery MCH */
|
2005-04-16 15:20:36 -07:00
|
|
|
ctl_set_bit(14, 24); /* enable warning MCH */
|
|
|
|
return 0;
|
|
|
|
}
|
2015-08-17 08:09:17 +02:00
|
|
|
early_initcall(machine_check_init);
|