linux/arch/riscv/kernel/tests/module_test/test_set32.S

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2023 Rivos Inc.
 */

.text
.global test_set32
test_set32:
	lw	a0, set32
	la	t0, set32
#ifndef CONFIG_32BIT
	slli	t0, t0, 32
	srli	t0, t0, 32
#endif
	sub	a0, a0, t0
	ret
.data
set32:
	.reloc set32, R_RISCV_SET32, set32
	.word 0
riscv: Add tests for riscv module loading Add test cases for the two main groups of relocations added: SUB and SET, along with uleb128. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20231101-module_relocations-v9-3-8dfa3483c400@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> 2023-11-01 11:33:01 -07:00			`/* SPDX-License-Identifier: GPL-2.0 */`
			`/*`
			`* Copyright (C) 2023 Rivos Inc.`
			`*/`

			`.text`
			`.global test_set32`
			`test_set32:`
			`lw a0, set32`
			`la t0, set32`
			`#ifndef CONFIG_32BIT`
			`slli t0, t0, 32`
			`srli t0, t0, 32`
			`#endif`
			`sub a0, a0, t0`
			`ret`
			`.data`
			`set32:`
			`.reloc set32, R_RISCV_SET32, set32`
			`.word 0`