public-mirrors/linux
1
0
Fork 0
mirror of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2025-05-24 10:39:52 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions
linux/arch/mips/include/asm/octeon/cvmx-ciu-defs.h

249 lines
9.4 KiB
C
Raw Normal View History

MIPS: Octeon: Convert CIU types to use bitfields. Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:22 -05:00
/* SPDX-License-Identifier: GPL-2.0 */
/* Octeon CIU definitions
MIPS: Add Cavium OCTEON processor CSR definitions Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-12-11 15:33:19 -08:00
*
MIPS: Octeon: Convert CIU types to use bitfields. Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:22 -05:00
* Copyright (C) 2003-2018 Cavium, Inc.
*/
MIPS: Add Cavium OCTEON processor CSR definitions Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-12-11 15:33:19 -08:00
#ifndef __CVMX_CIU_DEFS_H__
#define __CVMX_CIU_DEFS_H__
MIPS: Octeon: Convert CIU types to use bitfields. Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:22 -05:00
#include <asm/bitfield.h>
MIPS: Octeon: Create simple macro for CIU registers. Create new CVMX_CIU_ADDR macro to improve readability. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19712/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:24 -05:00
#define CVMX_CIU_ADDR(addr, coreid, coremask, offset) \
(CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) + \
(((coreid) & (coremask)) * offset))
#define CVMX_CIU_EN2_PPX_IP4(c) CVMX_CIU_ADDR(0xA400, c, 0x0F, 8)
#define CVMX_CIU_EN2_PPX_IP4_W1C(c) CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8)
#define CVMX_CIU_EN2_PPX_IP4_W1S(c) CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8)
#define CVMX_CIU_FUSE CVMX_CIU_ADDR(0x0728, 0, 0x00, 0)
#define CVMX_CIU_INT_SUM1 CVMX_CIU_ADDR(0x0108, 0, 0x00, 0)
#define CVMX_CIU_INTX_EN0(c) CVMX_CIU_ADDR(0x0200, c, 0x3F, 16)
#define CVMX_CIU_INTX_EN0_W1C(c) CVMX_CIU_ADDR(0x2200, c, 0x3F, 16)
#define CVMX_CIU_INTX_EN0_W1S(c) CVMX_CIU_ADDR(0x6200, c, 0x3F, 16)
#define CVMX_CIU_INTX_EN1(c) CVMX_CIU_ADDR(0x0208, c, 0x3F, 16)
#define CVMX_CIU_INTX_EN1_W1C(c) CVMX_CIU_ADDR(0x2208, c, 0x3F, 16)
#define CVMX_CIU_INTX_EN1_W1S(c) CVMX_CIU_ADDR(0x6208, c, 0x3F, 16)
#define CVMX_CIU_INTX_SUM0(c) CVMX_CIU_ADDR(0x0000, c, 0x3F, 8)
#define CVMX_CIU_NMI CVMX_CIU_ADDR(0x0718, 0, 0x00, 0)
#define CVMX_CIU_PCI_INTA CVMX_CIU_ADDR(0x0750, 0, 0x00, 0)
#define CVMX_CIU_PP_BIST_STAT CVMX_CIU_ADDR(0x07E0, 0, 0x00, 0)
#define CVMX_CIU_PP_DBG CVMX_CIU_ADDR(0x0708, 0, 0x00, 0)
#define CVMX_CIU_PP_RST CVMX_CIU_ADDR(0x0700, 0, 0x00, 0)
#define CVMX_CIU_QLM0 CVMX_CIU_ADDR(0x0780, 0, 0x00, 0)
#define CVMX_CIU_QLM1 CVMX_CIU_ADDR(0x0788, 0, 0x00, 0)
#define CVMX_CIU_QLM_JTGC CVMX_CIU_ADDR(0x0768, 0, 0x00, 0)
#define CVMX_CIU_QLM_JTGD CVMX_CIU_ADDR(0x0770, 0, 0x00, 0)
#define CVMX_CIU_SOFT_BIST CVMX_CIU_ADDR(0x0738, 0, 0x00, 0)
#define CVMX_CIU_SOFT_PRST1 CVMX_CIU_ADDR(0x0758, 0, 0x00, 0)
#define CVMX_CIU_SOFT_PRST CVMX_CIU_ADDR(0x0748, 0, 0x00, 0)
#define CVMX_CIU_SOFT_RST CVMX_CIU_ADDR(0x0740, 0, 0x00, 0)
#define CVMX_CIU_SUM2_PPX_IP4(c) CVMX_CIU_ADDR(0x8C00, c, 0x0F, 8)
#define CVMX_CIU_TIM_MULTI_CAST CVMX_CIU_ADDR(0xC200, 0, 0x00, 0)
#define CVMX_CIU_TIMX(c) CVMX_CIU_ADDR(0x0480, c, 0x0F, 8)
MIPS: Octeon: Remove all unused CIU macros. Get rid of all unused CIU macros and sort them. Verified with 'make allyesconfig' build test. [paul.burton@mips.com: - Also checked via convoluted grep invocation for use of all removed macros within arch/mips/ & drivers/.] Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19710/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:23 -05:00
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2012-04-03 13:44:18 -07:00
static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070100100600ull) + (offset) * 8;
}
return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
}
static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070100100400ull) + (offset) * 8;
}
return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
}
static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
MIPS: Octeon: Watchdog registers for 70xx, 73xx, 78xx, F75xx. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17208/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-29 10:40:33 -05:00
case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2012-04-03 13:44:18 -07:00
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8;
MIPS: Octeon: Watchdog registers for 70xx, 73xx, 78xx, F75xx. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17208/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-29 10:40:33 -05:00
case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001010000030000ull) + (offset) * 8;
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2012-04-03 13:44:18 -07:00
}
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
}
static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
{
switch (cvmx_get_octeon_family()) {
case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
MIPS: Octeon: Watchdog registers for 70xx, 73xx, 78xx, F75xx. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17208/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-29 10:40:33 -05:00
case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2012-04-03 13:44:18 -07:00
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8;
MIPS: Octeon: Watchdog registers for 70xx, 73xx, 78xx, F75xx. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17208/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-29 10:40:33 -05:00
case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001010000020000ull) + (offset) * 8;
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2012-04-03 13:44:18 -07:00
}
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
}
MIPS: Add Cavium OCTEON processor CSR definitions Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-12-11 15:33:19 -08:00
MIPS: Octeon: Convert CIU types to use bitfields. Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:22 -05:00
MIPS: Octeon: Unify QLM data types in CIU header. Data types 'cvmx_ciu_qlm0' and 'cvmx_ciu_qlm1' are identical in their usage and structure. Combine them and update the PCIe code. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19708/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:21 -05:00
union cvmx_ciu_qlm {
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2012-04-03 13:44:18 -07:00
uint64_t u64;
MIPS: Octeon: Unify QLM data types in CIU header. Data types 'cvmx_ciu_qlm0' and 'cvmx_ciu_qlm1' are identical in their usage and structure. Combine them and update the PCIe code. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19708/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:21 -05:00
struct cvmx_ciu_qlm_s {
MIPS: Octeon: Convert CIU types to use bitfields. Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:22 -05:00
__BITFIELD_FIELD(uint64_t g2bypass:1,
__BITFIELD_FIELD(uint64_t reserved_53_62:10,
__BITFIELD_FIELD(uint64_t g2deemph:5,
__BITFIELD_FIELD(uint64_t reserved_45_47:3,
__BITFIELD_FIELD(uint64_t g2margin:5,
__BITFIELD_FIELD(uint64_t reserved_32_39:8,
__BITFIELD_FIELD(uint64_t txbypass:1,
__BITFIELD_FIELD(uint64_t reserved_21_30:10,
__BITFIELD_FIELD(uint64_t txdeemph:5,
__BITFIELD_FIELD(uint64_t reserved_13_15:3,
__BITFIELD_FIELD(uint64_t txmargin:5,
__BITFIELD_FIELD(uint64_t reserved_4_7:4,
__BITFIELD_FIELD(uint64_t lane_en:4,
;)))))))))))))
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2012-04-03 13:44:18 -07:00
} s;
};
union cvmx_ciu_qlm_jtgc {
uint64_t u64;
struct cvmx_ciu_qlm_jtgc_s {
MIPS: Octeon: Convert CIU types to use bitfields. Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:22 -05:00
__BITFIELD_FIELD(uint64_t reserved_17_63:47,
__BITFIELD_FIELD(uint64_t bypass_ext:1,
__BITFIELD_FIELD(uint64_t reserved_11_15:5,
__BITFIELD_FIELD(uint64_t clk_div:3,
__BITFIELD_FIELD(uint64_t reserved_7_7:1,
__BITFIELD_FIELD(uint64_t mux_sel:3,
__BITFIELD_FIELD(uint64_t bypass:4,
;)))))))
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2012-04-03 13:44:18 -07:00
} s;
MIPS: Add Cavium OCTEON processor CSR definitions Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-12-11 15:33:19 -08:00
};
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2012-04-03 13:44:18 -07:00
union cvmx_ciu_qlm_jtgd {
MIPS: Add Cavium OCTEON processor CSR definitions Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-12-11 15:33:19 -08:00
uint64_t u64;
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2012-04-03 13:44:18 -07:00
struct cvmx_ciu_qlm_jtgd_s {
MIPS: Octeon: Convert CIU types to use bitfields. Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:22 -05:00
__BITFIELD_FIELD(uint64_t capture:1,
__BITFIELD_FIELD(uint64_t shift:1,
__BITFIELD_FIELD(uint64_t update:1,
__BITFIELD_FIELD(uint64_t reserved_45_60:16,
__BITFIELD_FIELD(uint64_t select:5,
__BITFIELD_FIELD(uint64_t reserved_37_39:3,
__BITFIELD_FIELD(uint64_t shft_cnt:5,
__BITFIELD_FIELD(uint64_t shft_reg:32,
;))))))))
MIPS: Add Cavium OCTEON processor CSR definitions Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-12-11 15:33:19 -08:00
} s;
};
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2012-04-03 13:44:18 -07:00
union cvmx_ciu_soft_prst {
MIPS: Add Cavium OCTEON processor CSR definitions Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-12-11 15:33:19 -08:00
uint64_t u64;
MIPS: OCTEON: Update register definitions. Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2012-04-03 13:44:18 -07:00
struct cvmx_ciu_soft_prst_s {
MIPS: Octeon: Convert CIU types to use bitfields. Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:22 -05:00
__BITFIELD_FIELD(uint64_t reserved_3_63:61,
__BITFIELD_FIELD(uint64_t host64:1,
__BITFIELD_FIELD(uint64_t npi:1,
__BITFIELD_FIELD(uint64_t soft_prst:1,
;))))
MIPS: Add Cavium OCTEON processor CSR definitions Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-12-11 15:33:19 -08:00
} s;
};
union cvmx_ciu_timx {
uint64_t u64;
struct cvmx_ciu_timx_s {
MIPS: Octeon: Convert CIU types to use bitfields. Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:22 -05:00
__BITFIELD_FIELD(uint64_t reserved_37_63:27,
__BITFIELD_FIELD(uint64_t one_shot:1,
__BITFIELD_FIELD(uint64_t len:36,
;)))
MIPS: Add Cavium OCTEON processor CSR definitions Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-12-11 15:33:19 -08:00
} s;
};
union cvmx_ciu_wdogx {
uint64_t u64;
struct cvmx_ciu_wdogx_s {
MIPS: Octeon: Convert CIU types to use bitfields. Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:22 -05:00
__BITFIELD_FIELD(uint64_t reserved_46_63:18,
__BITFIELD_FIELD(uint64_t gstopen:1,
__BITFIELD_FIELD(uint64_t dstop:1,
__BITFIELD_FIELD(uint64_t cnt:24,
__BITFIELD_FIELD(uint64_t len:16,
__BITFIELD_FIELD(uint64_t state:2,
__BITFIELD_FIELD(uint64_t mode:2,
;)))))))
MIPS: Add Cavium OCTEON processor CSR definitions Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-12-11 15:33:19 -08:00
} s;
};
MIPS: Octeon: Convert CIU types to use bitfields. Convert remaining structures to use __BITFIELD_FIELD macro. Also straighten up the description text and whitespace. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19709/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
2018-07-03 16:44:22 -05:00
#endif /* __CVMX_CIU_DEFS_H__ */
Reference in a new issue Copy permalink