License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 15:07:57 +01:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2018-08-03 16:26:13 +05:30
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/*
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* Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
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* All rights reserved.
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*/
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2015-05-11 14:30:56 +09:00
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#ifndef WILC_WLAN_H
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#define WILC_WLAN_H
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2015-11-16 15:04:55 +01:00
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#include <linux/types.h>
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2020-02-14 11:52:15 +00:00
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#include <linux/bitfield.h>
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2015-11-16 15:04:55 +01:00
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2015-05-11 14:30:56 +09:00
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/********************************************
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*
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* Mac eth header length
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*
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********************************************/
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2015-11-06 11:19:56 +09:00
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#define MAX_MAC_HDR_LEN 26 /* QOS_MAC_HDR_LEN */
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#define SUB_MSDU_HEADER_LENGTH 14
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#define SNAP_HDR_LEN 8
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#define ETHERNET_HDR_LEN 14
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#define WORD_ALIGNMENT_PAD 0
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#define ETH_ETHERNET_HDR_OFFSET (MAX_MAC_HDR_LEN + \
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SUB_MSDU_HEADER_LENGTH + \
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SNAP_HDR_LEN - \
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ETHERNET_HDR_LEN + \
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WORD_ALIGNMENT_PAD)
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#define HOST_HDR_OFFSET 4
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#define ETHERNET_HDR_LEN 14
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#define IP_HDR_LEN 20
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#define IP_HDR_OFFSET ETHERNET_HDR_LEN
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#define UDP_HDR_OFFSET (IP_HDR_LEN + IP_HDR_OFFSET)
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#define UDP_HDR_LEN 8
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#define UDP_DATA_OFFSET (UDP_HDR_OFFSET + UDP_HDR_LEN)
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#define ETH_CONFIG_PKT_HDR_LEN UDP_DATA_OFFSET
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#define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \
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ETH_CONFIG_PKT_HDR_LEN)
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2015-05-11 14:30:56 +09:00
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/********************************************
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*
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* Register Defines
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*
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********************************************/
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2015-11-06 11:19:56 +09:00
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#define WILC_PERIPH_REG_BASE 0x1000
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#define WILC_CHANGING_VIR_IF 0x108c
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#define WILC_CHIPID WILC_PERIPH_REG_BASE
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#define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
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#define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
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#define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
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#define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
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#define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
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#define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78)
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#define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80)
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#define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84)
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#define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88)
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#define WILC_MISC (WILC_PERIPH_REG_BASE + 0x428)
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#define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00)
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#define WILC_INTR_ENABLE WILC_INTR_REG_BASE
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#define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4)
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#define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10)
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#define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20)
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#define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30)
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#define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40)
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2020-02-14 11:52:23 +00:00
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#define WILC_RF_REVISION_ID 0x13f4
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2015-11-06 11:19:56 +09:00
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#define WILC_VMM_TBL_SIZE 64
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#define WILC_VMM_TX_TBL_BASE 0x150400
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#define WILC_VMM_RX_TBL_BASE 0x150500
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#define WILC_VMM_BASE 0x150000
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#define WILC_VMM_CORE_CTL WILC_VMM_BASE
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#define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4)
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#define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8)
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#define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc)
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#define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10)
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#define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14)
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#define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040)
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#define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44)
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#define WILC_SPI_REG_BASE 0xe800
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#define WILC_SPI_CTL WILC_SPI_REG_BASE
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#define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
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#define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
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#define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
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#define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
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#define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
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#define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
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#define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
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2020-02-14 11:52:23 +00:00
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#define WILC_SPI_INT_STATUS (WILC_SPI_REG_BASE + 0x40)
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#define WILC_SPI_INT_CLEAR (WILC_SPI_REG_BASE + 0x44)
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#define WILC_SPI_WAKEUP_REG 0x1
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#define WILC_SPI_WAKEUP_BIT BIT(1)
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2015-11-06 11:19:56 +09:00
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2021-09-16 16:49:19 +00:00
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#define WILC_SPI_CLK_STATUS_REG 0x0f
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#define WILC_SPI_CLK_STATUS_BIT BIT(2)
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2021-02-24 03:33:23 +00:00
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#define WILC_SPI_HOST_TO_FW_REG 0x0b
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#define WILC_SPI_HOST_TO_FW_BIT BIT(0)
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#define WILC_SPI_FW_TO_HOST_REG 0x10
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#define WILC_SPI_FW_TO_HOST_BIT BIT(0)
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2015-11-06 11:19:56 +09:00
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#define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - \
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WILC_SPI_REG_BASE)
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2020-02-14 11:52:23 +00:00
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#define WILC_SPI_CLOCKLESS_ADDR_LIMIT 0x30
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2020-02-14 11:52:21 +00:00
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/* Functions IO enables bits */
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#define WILC_SDIO_CCCR_IO_EN_FUNC1 BIT(1)
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/* Function/Interrupt enables bits */
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#define WILC_SDIO_CCCR_IEN_MASTER BIT(0)
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#define WILC_SDIO_CCCR_IEN_FUNC1 BIT(1)
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/* Abort CCCR register bits */
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#define WILC_SDIO_CCCR_ABORT_RESET BIT(3)
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/* Vendor specific CCCR registers */
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#define WILC_SDIO_WAKEUP_REG 0xf0
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#define WILC_SDIO_WAKEUP_BIT BIT(0)
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#define WILC_SDIO_CLK_STATUS_REG 0xf1
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#define WILC_SDIO_CLK_STATUS_BIT BIT(0)
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#define WILC_SDIO_INTERRUPT_DATA_SZ_REG 0xf2 /* Read size (2 bytes) */
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#define WILC_SDIO_VMM_TBL_CTRL_REG 0xf6
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#define WILC_SDIO_IRQ_FLAG_REG 0xf7
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#define WILC_SDIO_IRQ_CLEAR_FLAG_REG 0xf8
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#define WILC_SDIO_HOST_TO_FW_REG 0xfa
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#define WILC_SDIO_HOST_TO_FW_BIT BIT(0)
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#define WILC_SDIO_FW_TO_HOST_REG 0xfc
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#define WILC_SDIO_FW_TO_HOST_BIT BIT(0)
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/* Function 1 specific FBR register */
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#define WILC_SDIO_FBR_CSA_REG 0x10C /* CSA pointer (3 bytes) */
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#define WILC_SDIO_FBR_DATA_REG 0x10F
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#define WILC_SDIO_F1_DATA_REG 0x0
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#define WILC_SDIO_EXT_IRQ_FLAG_REG 0x4
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2015-11-06 11:19:56 +09:00
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#define WILC_AHB_DATA_MEM_BASE 0x30000
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#define WILC_AHB_SHARE_MEM_BASE 0xd0000
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#define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE
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#define WILC_VMM_TBL_RX_SHADOW_SIZE 256
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2019-08-09 18:25:18 +00:00
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#define WILC_FW_HOST_COMM 0x13c0
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2015-11-06 11:19:56 +09:00
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#define WILC_GP_REG_0 0x149c
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#define WILC_GP_REG_1 0x14a0
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2015-11-06 11:19:57 +09:00
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#define WILC_HAVE_SDIO_IRQ_GPIO BIT(0)
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#define WILC_HAVE_USE_PMU BIT(1)
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#define WILC_HAVE_SLEEP_CLK_SRC_RTC BIT(2)
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#define WILC_HAVE_SLEEP_CLK_SRC_XO BIT(3)
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#define WILC_HAVE_EXT_PA_INV_TX_RX BIT(4)
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#define WILC_HAVE_LEGACY_RF_SETTINGS BIT(5)
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#define WILC_HAVE_XTAL_24 BIT(6)
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#define WILC_HAVE_DISABLE_WILC_UART BIT(7)
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2016-01-25 16:35:07 +09:00
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#define WILC_HAVE_USE_IRQ_AS_HOST_WAKE BIT(8)
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2015-05-11 14:30:56 +09:00
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2020-02-14 11:52:23 +00:00
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#define WILC_CORTUS_INTERRUPT_BASE 0x10A8
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#define WILC_CORTUS_INTERRUPT_1 (WILC_CORTUS_INTERRUPT_BASE + 0x4)
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#define WILC_CORTUS_INTERRUPT_2 (WILC_CORTUS_INTERRUPT_BASE + 0x8)
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/* tx control register 1 to 4 for RX */
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#define WILC_REG_4_TO_1_RX 0x1e1c
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/* tx control register 1 to 4 for TX Bank_0 */
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#define WILC_REG_4_TO_1_TX_BANK0 0x1e9c
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#define WILC_CORTUS_RESET_MUX_SEL 0x1118
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#define WILC_CORTUS_BOOT_REGISTER 0xc0000
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#define WILC_CORTUS_BOOT_FROM_IRAM 0x71
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#define WILC_1000_BASE_ID 0x100000
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#define WILC_1000_BASE_ID_2A 0x1002A0
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#define WILC_1000_BASE_ID_2A_REV1 (WILC_1000_BASE_ID_2A + 1)
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#define WILC_1000_BASE_ID_2B 0x1002B0
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#define WILC_1000_BASE_ID_2B_REV1 (WILC_1000_BASE_ID_2B + 1)
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#define WILC_1000_BASE_ID_2B_REV2 (WILC_1000_BASE_ID_2B + 2)
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#define WILC_CHIP_REV_FIELD GENMASK(11, 0)
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2015-05-11 14:30:56 +09:00
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/********************************************
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*
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* Wlan Defines
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*
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********************************************/
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2015-11-06 11:19:56 +09:00
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#define WILC_CFG_PKT 1
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#define WILC_NET_PKT 0
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#define WILC_MGMT_PKT 2
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2015-05-11 14:30:56 +09:00
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2015-11-06 11:19:56 +09:00
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#define WILC_CFG_SET 1
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#define WILC_CFG_QUERY 0
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2015-05-11 14:30:56 +09:00
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2015-11-06 11:19:56 +09:00
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#define WILC_CFG_RSP 1
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#define WILC_CFG_RSP_STATUS 2
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#define WILC_CFG_RSP_SCAN 3
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2015-05-11 14:30:56 +09:00
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2019-08-09 18:25:18 +00:00
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#define WILC_ABORT_REQ_BIT BIT(31)
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2015-05-11 14:30:56 +09:00
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2019-02-07 11:29:01 +00:00
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#define WILC_RX_BUFF_SIZE (96 * 1024)
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#define WILC_TX_BUFF_SIZE (64 * 1024)
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2016-02-22 13:12:09 +09:00
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2020-11-25 11:41:10 +00:00
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#define NQUEUES 4
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#define AC_BUFFER_SIZE 1000
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#define VO_AC_COUNT_FIELD GENMASK(31, 25)
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#define VO_AC_ACM_STAT_FIELD BIT(24)
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#define VI_AC_COUNT_FIELD GENMASK(23, 17)
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#define VI_AC_ACM_STAT_FIELD BIT(16)
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#define BE_AC_COUNT_FIELD GENMASK(15, 9)
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#define BE_AC_ACM_STAT_FIELD BIT(8)
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#define BK_AC_COUNT_FIELD GENMASK(7, 3)
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#define BK_AC_ACM_STAT_FIELD BIT(1)
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2020-02-14 11:52:15 +00:00
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#define WILC_PKT_HDR_CONFIG_FIELD BIT(31)
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#define WILC_PKT_HDR_OFFSET_FIELD GENMASK(30, 22)
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#define WILC_PKT_HDR_TOTAL_LEN_FIELD GENMASK(21, 11)
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#define WILC_PKT_HDR_LEN_FIELD GENMASK(10, 0)
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#define WILC_INTERRUPT_DATA_SIZE GENMASK(14, 0)
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#define WILC_VMM_BUFFER_SIZE GENMASK(9, 0)
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#define WILC_VMM_HDR_TYPE BIT(31)
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#define WILC_VMM_HDR_MGMT_FIELD BIT(30)
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#define WILC_VMM_HDR_PKT_SIZE GENMASK(29, 15)
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#define WILC_VMM_HDR_BUFF_SIZE GENMASK(14, 0)
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#define WILC_VMM_ENTRY_COUNT GENMASK(8, 3)
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#define WILC_VMM_ENTRY_AVAILABLE BIT(2)
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2015-05-11 14:30:56 +09:00
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/*******************************************/
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/* E0 and later Interrupt flags. */
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/*******************************************/
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/*******************************************/
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/* E0 and later Interrupt flags. */
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/* IRQ Status word */
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/* 15:0 = DMA count in words. */
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/* 16: INT0 flag */
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/* 17: INT1 flag */
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/* 18: INT2 flag */
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/* 19: INT3 flag */
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/* 20: INT4 flag */
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/* 21: INT5 flag */
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/*******************************************/
|
2015-11-06 11:19:56 +09:00
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#define IRG_FLAGS_OFFSET 16
|
2020-02-14 11:52:15 +00:00
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#define IRQ_DMA_WD_CNT_MASK GENMASK(IRG_FLAGS_OFFSET - 1, 0)
|
2015-11-06 11:19:57 +09:00
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#define INT_0 BIT(IRG_FLAGS_OFFSET)
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#define INT_1 BIT(IRG_FLAGS_OFFSET + 1)
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#define INT_2 BIT(IRG_FLAGS_OFFSET + 2)
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#define INT_3 BIT(IRG_FLAGS_OFFSET + 3)
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#define INT_4 BIT(IRG_FLAGS_OFFSET + 4)
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#define INT_5 BIT(IRG_FLAGS_OFFSET + 5)
|
2020-02-14 11:52:16 +00:00
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#define MAX_NUM_INT 5
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2020-02-14 11:52:17 +00:00
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#define IRG_FLAGS_MASK GENMASK(IRG_FLAGS_OFFSET + MAX_NUM_INT, \
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IRG_FLAGS_OFFSET)
|
2015-05-11 14:30:56 +09:00
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/*******************************************/
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/* E0 and later Interrupt flags. */
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/* IRQ Clear word */
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/* 0: Clear INT0 */
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/* 1: Clear INT1 */
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/* 2: Clear INT2 */
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/* 3: Clear INT3 */
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/* 4: Clear INT4 */
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/* 5: Clear INT5 */
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/* 6: Select VMM table 1 */
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/* 7: Select VMM table 2 */
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/* 8: Enable VMM */
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/*******************************************/
|
2015-11-06 11:19:56 +09:00
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#define CLR_INT0 BIT(0)
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#define CLR_INT1 BIT(1)
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#define CLR_INT2 BIT(2)
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#define CLR_INT3 BIT(3)
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#define CLR_INT4 BIT(4)
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#define CLR_INT5 BIT(5)
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#define SEL_VMM_TBL0 BIT(6)
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#define SEL_VMM_TBL1 BIT(7)
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#define EN_VMM BIT(8)
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#define DATA_INT_EXT INT_0
|
2019-09-10 07:46:04 +00:00
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#define ALL_INT_EXT DATA_INT_EXT
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#define NUM_INT_EXT 1
|
2020-02-14 11:52:17 +00:00
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#define UNHANDLED_IRQ_MASK GENMASK(MAX_NUM_INT - 1, NUM_INT_EXT)
|
2015-11-06 11:19:56 +09:00
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#define DATA_INT_CLR CLR_INT0
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#define ENABLE_RX_VMM (SEL_VMM_TBL1 | EN_VMM)
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#define ENABLE_TX_VMM (SEL_VMM_TBL0 | EN_VMM)
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2019-11-05 09:51:33 +00:00
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/* time for expiring the completion of cfg packets */
|
2021-09-16 16:49:23 +00:00
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#define WILC_CFG_PKTS_TIMEOUT msecs_to_jiffies(3000)
|
2018-02-26 22:01:58 +05:30
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#define IS_MANAGMEMENT 0x100
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#define IS_MANAGMEMENT_CALLBACK 0x080
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#define IS_MGMT_STATUS_SUCCES 0x040
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|
2019-11-22 20:52:05 +00:00
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#define WILC_WID_TYPE GENMASK(15, 12)
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2020-01-23 12:50:49 +00:00
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#define WILC_VMM_ENTRY_FULL_RETRY 1
|
2015-05-11 14:30:56 +09:00
|
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|
/********************************************
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*
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|
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|
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* Tx/Rx Queue Structure
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*
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|
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|
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********************************************/
|
2020-11-25 11:41:10 +00:00
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|
enum ip_pkt_priority {
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AC_VO_Q = 0,
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AC_VI_Q = 1,
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AC_BE_Q = 2,
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AC_BK_Q = 3
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};
|
2015-05-11 14:30:56 +09:00
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struct txq_entry_t {
|
2018-06-04 10:59:07 +05:30
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struct list_head list;
|
2015-05-11 14:30:56 +09:00
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int type;
|
2020-11-25 11:41:10 +00:00
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u8 q_num;
|
2018-09-04 12:09:35 +05:30
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int ack_idx;
|
2015-09-15 14:06:14 +09:00
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u8 *buffer;
|
2015-05-11 14:30:56 +09:00
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int buffer_size;
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void *priv;
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int status;
|
2019-06-26 12:40:52 +00:00
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struct wilc_vif *vif;
|
2018-04-23 22:03:23 +05:30
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void (*tx_complete_func)(void *priv, int status);
|
2015-05-11 14:30:56 +09:00
|
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};
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|
2020-11-25 11:41:10 +00:00
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struct txq_fw_recv_queue_stat {
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u8 acm;
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u8 count;
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};
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struct txq_handle {
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struct txq_entry_t txq_head;
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u16 count;
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struct txq_fw_recv_queue_stat fw;
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};
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|
2015-05-11 14:30:56 +09:00
|
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|
struct rxq_entry_t {
|
2018-06-04 10:59:08 +05:30
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struct list_head list;
|
2015-09-15 14:06:14 +09:00
|
|
|
u8 *buffer;
|
2015-05-11 14:30:56 +09:00
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|
int buffer_size;
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|
|
|
};
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|
|
|
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|
|
|
/********************************************
|
|
|
|
|
*
|
|
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|
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* Host IF Structure
|
|
|
|
|
*
|
|
|
|
|
********************************************/
|
2015-11-06 18:40:22 +09:00
|
|
|
struct wilc;
|
2015-11-06 11:20:02 +09:00
|
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|
struct wilc_hif_func {
|
2018-04-23 22:03:23 +05:30
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int (*hif_init)(struct wilc *wilc, bool resume);
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int (*hif_deinit)(struct wilc *wilc);
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int (*hif_read_reg)(struct wilc *wilc, u32 addr, u32 *data);
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int (*hif_write_reg)(struct wilc *wilc, u32 addr, u32 data);
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int (*hif_block_rx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
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int (*hif_block_tx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
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int (*hif_read_int)(struct wilc *wilc, u32 *int_status);
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int (*hif_clear_int_ext)(struct wilc *wilc, u32 val);
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int (*hif_read_size)(struct wilc *wilc, u32 *size);
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int (*hif_block_tx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
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int (*hif_block_rx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
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int (*hif_sync_ext)(struct wilc *wilc, int nint);
|
2015-11-16 15:05:06 +01:00
|
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|
int (*enable_interrupt)(struct wilc *nic);
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void (*disable_interrupt)(struct wilc *nic);
|
2021-09-16 16:49:20 +00:00
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int (*hif_reset)(struct wilc *wilc);
|
2015-11-06 11:20:02 +09:00
|
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};
|
2015-05-11 14:30:56 +09:00
|
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|
|
2019-02-07 11:29:01 +00:00
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#define WILC_MAX_CFG_FRAME_SIZE 1468
|
2015-05-11 14:30:56 +09:00
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|
2019-02-07 11:29:04 +00:00
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|
struct tx_complete_data {
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int size;
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void *buff;
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struct sk_buff *skb;
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};
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|
2019-01-17 13:21:15 +00:00
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struct wilc_cfg_cmd_hdr {
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u8 cmd_type;
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u8 seq_no;
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__le16 total_len;
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__le32 driver_handler;
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|
};
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|
2015-11-06 11:19:59 +09:00
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|
struct wilc_cfg_frame {
|
2019-01-17 13:21:15 +00:00
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|
struct wilc_cfg_cmd_hdr hdr;
|
2019-02-07 11:29:01 +00:00
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|
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u8 frame[WILC_MAX_CFG_FRAME_SIZE];
|
2015-11-06 11:19:59 +09:00
|
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};
|
2015-05-11 14:30:56 +09:00
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|
2015-11-06 11:20:01 +09:00
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struct wilc_cfg_rsp {
|
2019-01-17 13:21:15 +00:00
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u8 type;
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u8 seq_no;
|
2015-11-06 11:20:01 +09:00
|
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};
|
2015-05-11 14:30:56 +09:00
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|
2016-02-04 18:15:31 +09:00
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|
struct wilc_vif;
|
2015-11-16 15:04:55 +01:00
|
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|
2016-02-04 18:15:49 +09:00
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|
int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer,
|
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|
|
|
u32 buffer_size);
|
2017-03-04 21:27:39 +05:30
|
|
|
int wilc_wlan_start(struct wilc *wilc);
|
2019-08-09 18:25:18 +00:00
|
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|
int wilc_wlan_stop(struct wilc *wilc, struct wilc_vif *vif);
|
2021-02-10 20:40:24 +02:00
|
|
|
int wilc_wlan_txq_add_net_pkt(struct net_device *dev,
|
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|
|
struct tx_complete_data *tx_data, u8 *buffer,
|
2019-01-17 13:21:44 +00:00
|
|
|
u32 buffer_size,
|
|
|
|
|
void (*tx_complete_fn)(void *, int));
|
2019-06-26 12:40:52 +00:00
|
|
|
int wilc_wlan_handle_txq(struct wilc *wl, u32 *txq_count);
|
2015-11-16 15:05:10 +01:00
|
|
|
void wilc_handle_isr(struct wilc *wilc);
|
2015-10-27 18:27:54 +09:00
|
|
|
void wilc_wlan_cleanup(struct net_device *dev);
|
2016-03-28 13:55:56 +09:00
|
|
|
int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer,
|
2015-11-18 15:11:34 +09:00
|
|
|
u32 buffer_size, int commit, u32 drv_handler);
|
2016-03-28 13:55:57 +09:00
|
|
|
int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit,
|
2015-11-18 15:11:35 +09:00
|
|
|
u32 drv_handler);
|
2015-10-29 12:18:44 +09:00
|
|
|
int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer,
|
2019-01-17 13:21:44 +00:00
|
|
|
u32 buffer_size, void (*func)(void *, int));
|
2018-09-04 12:09:33 +05:30
|
|
|
void wilc_enable_tcp_ack_filter(struct wilc_vif *vif, bool value);
|
2017-03-04 21:27:39 +05:30
|
|
|
int wilc_wlan_get_num_conn_ifcs(struct wilc *wilc);
|
2018-04-24 15:18:57 +02:00
|
|
|
netdev_tx_t wilc_mac_xmit(struct sk_buff *skb, struct net_device *dev);
|
2015-11-16 15:04:55 +01:00
|
|
|
|
2019-06-26 12:40:52 +00:00
|
|
|
void wilc_wfi_p2p_rx(struct wilc_vif *vif, u8 *buff, u32 size);
|
2016-01-25 16:35:07 +09:00
|
|
|
void host_wakeup_notify(struct wilc *wilc);
|
|
|
|
|
void host_sleep_notify(struct wilc *wilc);
|
2016-01-25 16:35:08 +09:00
|
|
|
void chip_allow_sleep(struct wilc *wilc);
|
|
|
|
|
void chip_wakeup(struct wilc *wilc);
|
2016-02-11 13:46:22 +09:00
|
|
|
int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids,
|
2019-06-26 12:41:04 +00:00
|
|
|
u32 count);
|
2019-02-07 11:29:04 +00:00
|
|
|
int wilc_wlan_init(struct net_device *dev);
|
|
|
|
|
u32 wilc_get_chipid(struct wilc *wilc, bool update);
|
2015-05-11 14:30:56 +09:00
|
|
|
#endif
|