2018-02-11 10:57:18 +02:00
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/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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2020-04-18 11:08:57 +03:00
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* Copyright(c) 2018 - 2020 Intel Corporation
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2018-02-11 10:57:18 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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2020-04-18 11:08:57 +03:00
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* Copyright(c) 2018 - 2020 Intel Corporation
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2018-02-11 10:57:18 +02:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#include "iwl-trans.h"
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#include "iwl-fh.h"
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#include "iwl-context-info-gen3.h"
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#include "internal.h"
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#include "iwl-prph.h"
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2019-07-23 12:34:49 +03:00
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static void
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iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans,
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struct iwl_prph_scratch_hwm_cfg *dbg_cfg,
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u32 *control_flags)
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{
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enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
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struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
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u32 dbg_flags = 0;
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if (!iwl_trans_dbg_ini_valid(trans)) {
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struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
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iwl_pcie_alloc_fw_monitor(trans, 0);
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if (fw_mon->size) {
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dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
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IWL_DEBUG_FW(trans,
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"WRT: Applying DRAM buffer destination\n");
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dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical);
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dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size);
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}
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goto out;
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}
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fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id];
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2020-04-18 11:08:57 +03:00
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switch (le32_to_cpu(fw_mon_cfg->buf_location)) {
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case IWL_FW_INI_LOCATION_SRAM_PATH:
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2019-07-23 12:34:49 +03:00
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dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL;
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IWL_DEBUG_FW(trans,
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2020-04-18 11:08:57 +03:00
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"WRT: Applying SMEM buffer destination\n");
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break;
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2019-07-23 12:34:49 +03:00
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2020-04-18 11:08:57 +03:00
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case IWL_FW_INI_LOCATION_NPK_PATH:
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dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF;
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2019-07-23 12:34:49 +03:00
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IWL_DEBUG_FW(trans,
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2020-04-18 11:08:57 +03:00
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"WRT: Applying NPK buffer destination\n");
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break;
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2019-07-23 12:34:49 +03:00
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2020-04-18 11:08:57 +03:00
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case IWL_FW_INI_LOCATION_DRAM_PATH:
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if (trans->dbg.fw_mon_ini[alloc_id].num_frags) {
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struct iwl_dram_data *frag =
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&trans->dbg.fw_mon_ini[alloc_id].frags[0];
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dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
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dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical);
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dbg_cfg->hwm_size = cpu_to_le32(frag->size);
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IWL_DEBUG_FW(trans,
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"WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n",
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alloc_id,
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trans->dbg.fw_mon_ini[alloc_id].num_frags);
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}
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break;
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default:
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IWL_ERR(trans, "WRT: Invalid buffer destination\n");
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2019-07-23 12:34:49 +03:00
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}
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out:
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if (dbg_flags)
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*control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags;
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}
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2018-02-11 10:57:18 +02:00
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int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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const struct fw_img *fw)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_context_info_gen3 *ctxt_info_gen3;
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struct iwl_prph_scratch *prph_scratch;
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struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
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struct iwl_prph_info *prph_info;
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void *iml_img;
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u32 control_flags = 0;
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int ret;
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2019-03-05 09:48:16 +02:00
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int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
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trans->cfg->min_txq_size);
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2018-02-11 10:57:18 +02:00
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2020-04-17 10:08:11 +03:00
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switch (trans_pcie->rx_buf_size) {
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case IWL_AMSDU_DEF:
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return -EINVAL;
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case IWL_AMSDU_2K:
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break;
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case IWL_AMSDU_4K:
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2020-05-29 09:39:26 +03:00
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control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
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break;
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2020-04-17 10:08:11 +03:00
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case IWL_AMSDU_8K:
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2020-05-29 09:39:26 +03:00
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control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
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/* if firmware supports the ext size, tell it */
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control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K;
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break;
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2020-04-17 10:08:11 +03:00
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case IWL_AMSDU_12K:
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control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
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2020-05-29 09:39:26 +03:00
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/* if firmware supports the ext size, tell it */
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control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K;
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2020-04-17 10:08:11 +03:00
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break;
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}
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2018-02-11 10:57:18 +02:00
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/* Allocate prph scratch */
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prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
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&trans_pcie->prph_scratch_dma_addr,
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GFP_KERNEL);
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if (!prph_scratch)
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return -ENOMEM;
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prph_sc_ctrl = &prph_scratch->ctrl_cfg;
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prph_sc_ctrl->version.version = 0;
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prph_sc_ctrl->version.mac_id =
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cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
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prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4);
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2020-04-17 10:08:11 +03:00
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control_flags |= IWL_PRPH_SCRATCH_MTR_MODE;
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control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT;
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2018-02-11 10:57:18 +02:00
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/* initialize RX default queue */
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prph_sc_ctrl->rbd_cfg.free_rbd_addr =
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cpu_to_le64(trans_pcie->rxq->bd_dma);
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2019-07-23 12:34:49 +03:00
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iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg,
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&control_flags);
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prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags);
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2017-12-26 14:49:30 +02:00
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2018-02-11 10:57:18 +02:00
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/* allocate ucode sections in dram and set addresses */
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ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
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2019-09-27 15:56:04 -05:00
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if (ret)
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goto err_free_prph_scratch;
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2018-02-11 10:57:18 +02:00
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/* Allocate prph information
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* currently we don't assign to the prph info anything, but it would get
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* assigned later */
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prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info),
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&trans_pcie->prph_info_dma_addr,
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GFP_KERNEL);
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2019-09-27 15:56:04 -05:00
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if (!prph_info) {
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ret = -ENOMEM;
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goto err_free_prph_scratch;
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}
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2018-02-11 10:57:18 +02:00
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/* Allocate context info */
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ctxt_info_gen3 = dma_alloc_coherent(trans->dev,
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sizeof(*ctxt_info_gen3),
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&trans_pcie->ctxt_info_dma_addr,
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GFP_KERNEL);
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2019-09-27 15:56:04 -05:00
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if (!ctxt_info_gen3) {
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ret = -ENOMEM;
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goto err_free_prph_info;
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}
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2018-02-11 10:57:18 +02:00
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ctxt_info_gen3->prph_info_base_addr =
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cpu_to_le64(trans_pcie->prph_info_dma_addr);
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ctxt_info_gen3->prph_scratch_base_addr =
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cpu_to_le64(trans_pcie->prph_scratch_dma_addr);
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ctxt_info_gen3->prph_scratch_size =
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cpu_to_le32(sizeof(*prph_scratch));
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ctxt_info_gen3->cr_head_idx_arr_base_addr =
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cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
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ctxt_info_gen3->tr_tail_idx_arr_base_addr =
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cpu_to_le64(trans_pcie->rxq->tr_tail_dma);
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ctxt_info_gen3->cr_tail_idx_arr_base_addr =
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cpu_to_le64(trans_pcie->rxq->cr_tail_dma);
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ctxt_info_gen3->cr_idx_arr_size =
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cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS);
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ctxt_info_gen3->tr_idx_arr_size =
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cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS);
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ctxt_info_gen3->mtr_base_addr =
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2020-05-29 09:39:28 +03:00
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cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr);
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2018-02-11 10:57:18 +02:00
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ctxt_info_gen3->mcr_base_addr =
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cpu_to_le64(trans_pcie->rxq->used_bd_dma);
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ctxt_info_gen3->mtr_size =
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2018-11-19 16:44:05 +02:00
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cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size));
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2018-02-11 10:57:18 +02:00
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ctxt_info_gen3->mcr_size =
|
iwlwifi: allocate more receive buffers for HE devices
For HE-capable devices, we need to allocate more receive buffers as
there could be 256 frames aggregated into a single A-MPDU, and then
they might contain A-MSDUs as well. Until 22000 family, the devices
are able to put multiple frames into a single RB and the default RB
size is 4k, but starting from AX210 family this is no longer true.
On the other hand, those newer devices only use 2k receive buffers
(by default).
Modify the code and configuration to allocate an appropriate number
of RBs depending on the device capabilities:
* 4096 for AX210 HE devices, which use 2k buffers by default,
* 2048 for 22000 family devices which use 4k buffers by default,
* 512 for existing 9000 family devices, which doesn't really
change anything since that's the default before this patch,
* 512 also for AX210/22000 family devices that don't do HE.
Theoretically, for devices lower than AX210, we wouldn't have to
allocate that many RBs if the RB size was manually increased, but
to support that the code got more complex, and it didn't really
seem necessary as that's a use case for monitor mode only, where
hopefully the wasted memory isn't really much of a concern.
Note that AX210 devices actually support bigger than 12-bit VID,
which is required here as we want to allocate 4096 buffers plus
some for quick recycling, so adjust the code for that as well.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2019-09-27 10:36:02 +02:00
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cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds));
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2018-02-11 10:57:18 +02:00
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trans_pcie->ctxt_info_gen3 = ctxt_info_gen3;
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trans_pcie->prph_info = prph_info;
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trans_pcie->prph_scratch = prph_scratch;
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/* Allocate IML */
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iml_img = dma_alloc_coherent(trans->dev, trans->iml_len,
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&trans_pcie->iml_dma_addr, GFP_KERNEL);
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if (!iml_img)
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return -ENOMEM;
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memcpy(iml_img, trans->iml, trans->iml_len);
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|
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2019-05-20 15:18:24 +03:00
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iwl_enable_fw_load_int_ctx_info(trans);
|
2018-02-11 10:57:18 +02:00
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/* kick FW self load */
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iwl_write64(trans, CSR_CTXT_INFO_ADDR,
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trans_pcie->ctxt_info_dma_addr);
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iwl_write64(trans, CSR_IML_DATA_ADDR,
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|
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trans_pcie->iml_dma_addr);
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iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len);
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2018-11-19 16:44:05 +02:00
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2019-01-01 14:03:23 +02:00
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iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,
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CSR_AUTO_FUNC_BOOT_ENA);
|
2020-11-07 10:50:10 +02:00
|
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|
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if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
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|
/*
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* The firmware initializes this again later (to a smaller
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* value), but for the boot process initialize the LTR to
|
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* ~250 usec.
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*/
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|
|
u32 val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
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u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
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CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
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u32_encode_bits(250,
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|
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CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
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CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
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u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
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|
|
CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
|
|
|
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u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
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|
|
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|
|
iwl_write32(trans, CSR_LTR_LONG_VAL_AD, val);
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|
|
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}
|
|
|
|
|
2019-07-12 15:03:48 +03:00
|
|
|
if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
|
2019-01-01 14:03:23 +02:00
|
|
|
iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
|
|
|
|
else
|
2018-11-19 16:44:05 +02:00
|
|
|
iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT);
|
2018-02-11 10:57:18 +02:00
|
|
|
|
|
|
|
return 0;
|
2019-09-27 15:56:04 -05:00
|
|
|
|
|
|
|
err_free_prph_info:
|
|
|
|
dma_free_coherent(trans->dev,
|
|
|
|
sizeof(*prph_info),
|
|
|
|
prph_info,
|
|
|
|
trans_pcie->prph_info_dma_addr);
|
|
|
|
|
|
|
|
err_free_prph_scratch:
|
|
|
|
dma_free_coherent(trans->dev,
|
|
|
|
sizeof(*prph_scratch),
|
|
|
|
prph_scratch,
|
|
|
|
trans_pcie->prph_scratch_dma_addr);
|
|
|
|
return ret;
|
|
|
|
|
2018-02-11 10:57:18 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans)
|
|
|
|
{
|
|
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
|
|
|
|
if (!trans_pcie->ctxt_info_gen3)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
|
|
|
|
trans_pcie->ctxt_info_gen3,
|
|
|
|
trans_pcie->ctxt_info_dma_addr);
|
|
|
|
trans_pcie->ctxt_info_dma_addr = 0;
|
|
|
|
trans_pcie->ctxt_info_gen3 = NULL;
|
|
|
|
|
|
|
|
iwl_pcie_ctxt_info_free_fw_img(trans);
|
|
|
|
|
|
|
|
dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch),
|
|
|
|
trans_pcie->prph_scratch,
|
|
|
|
trans_pcie->prph_scratch_dma_addr);
|
|
|
|
trans_pcie->prph_scratch_dma_addr = 0;
|
|
|
|
trans_pcie->prph_scratch = NULL;
|
|
|
|
|
|
|
|
dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info),
|
|
|
|
trans_pcie->prph_info,
|
|
|
|
trans_pcie->prph_info_dma_addr);
|
|
|
|
trans_pcie->prph_info_dma_addr = 0;
|
|
|
|
trans_pcie->prph_info = NULL;
|
2020-10-08 18:12:48 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
|
|
|
|
const void *data, u32 len)
|
|
|
|
{
|
|
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
|
|
|
|
&trans_pcie->prph_scratch->ctrl_cfg;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len,
|
|
|
|
&trans_pcie->pnvm_dram);
|
|
|
|
if (ret < 0) {
|
|
|
|
IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n",
|
|
|
|
ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
|
|
|
|
cpu_to_le64(trans_pcie->pnvm_dram.physical);
|
|
|
|
prph_sc_ctrl->pnvm_cfg.pnvm_size =
|
|
|
|
cpu_to_le32(trans_pcie->pnvm_dram.size);
|
|
|
|
|
|
|
|
return 0;
|
2018-02-11 10:57:18 +02:00
|
|
|
}
|