License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 15:07:57 +01:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0 */
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
|
|
|
|
#ifndef __ASM_ARC_ENTRY_ARCV2_H
|
|
|
|
|
#define __ASM_ARC_ENTRY_ARCV2_H
|
|
|
|
|
|
|
|
|
|
#include <asm/asm-offsets.h>
|
2020-03-05 23:02:50 +03:00
|
|
|
#include <asm/dsp-impl.h>
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
#include <asm/irqflags-arcv2.h>
|
|
|
|
|
#include <asm/thread_info.h> /* For THREAD_SIZE */
|
|
|
|
|
|
2019-04-09 16:55:15 -07:00
|
|
|
/*
|
|
|
|
|
* Interrupt/Exception stack layout (pt_regs) for ARCv2
|
|
|
|
|
* (End of struct aligned to end of page [unless nested])
|
|
|
|
|
*
|
|
|
|
|
* INTERRUPT EXCEPTION
|
|
|
|
|
*
|
|
|
|
|
* manual --------------------- manual
|
|
|
|
|
* | orig_r0 |
|
|
|
|
|
* | event/ECR |
|
|
|
|
|
* | bta |
|
|
|
|
|
* | gp |
|
|
|
|
|
* | fp |
|
|
|
|
|
* | sp |
|
|
|
|
|
* | r12 |
|
|
|
|
|
* | r30 |
|
|
|
|
|
* | r58 |
|
|
|
|
|
* | r59 |
|
|
|
|
|
* hw autosave ---------------------
|
|
|
|
|
* optional | r0 |
|
|
|
|
|
* | r1 |
|
|
|
|
|
* ~ ~
|
|
|
|
|
* | r9 |
|
|
|
|
|
* | r10 |
|
|
|
|
|
* | r11 |
|
|
|
|
|
* | blink |
|
|
|
|
|
* | lpe |
|
|
|
|
|
* | lps |
|
|
|
|
|
* | lpc |
|
|
|
|
|
* | ei base |
|
|
|
|
|
* | ldi base |
|
|
|
|
|
* | jli base |
|
|
|
|
|
* ---------------------
|
|
|
|
|
* hw autosave | pc / eret |
|
|
|
|
|
* mandatory | stat32 / erstatus |
|
|
|
|
|
* ---------------------
|
|
|
|
|
*/
|
|
|
|
|
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
/*------------------------------------------------------------------------*/
|
2019-05-15 15:36:46 -07:00
|
|
|
.macro INTERRUPT_PROLOGUE
|
|
|
|
|
|
2020-05-19 16:01:52 -07:00
|
|
|
; Before jumping to Interrupt Vector, hardware micro-ops did following:
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
; 1. SP auto-switched to kernel mode stack
|
2019-04-09 16:55:15 -07:00
|
|
|
; 2. STATUS32.Z flag set if in U mode at time of interrupt (U:1,K:0)
|
|
|
|
|
; 3. Auto save: (mandatory) Push PC and STAT32 on stack
|
|
|
|
|
; hardware does even if CONFIG_ARC_IRQ_NO_AUTOSAVE
|
2020-05-19 16:01:52 -07:00
|
|
|
; 4a. Auto save: (optional) r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
;
|
2020-05-19 16:01:52 -07:00
|
|
|
; Now
|
|
|
|
|
; 4b. If Auto-save (optional) not enabled in hw, manually save them
|
|
|
|
|
; 5. Manually save: r12,r30, sp,fp,gp, ACCL pair
|
|
|
|
|
;
|
|
|
|
|
; At the end, SP points to pt_regs
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2018-06-06 10:20:37 -07:00
|
|
|
#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE
|
2019-05-15 15:36:46 -07:00
|
|
|
; carve pt_regs on stack (case #3), PC/STAT32 already on stack
|
|
|
|
|
sub sp, sp, SZ_PT_REGS - 8
|
2018-06-06 10:20:37 -07:00
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
__SAVE_REGFILE_HARD
|
|
|
|
|
#else
|
|
|
|
|
; carve pt_regs on stack (case #4), which grew partially already
|
|
|
|
|
sub sp, sp, PT_r0
|
2017-04-20 15:36:51 -07:00
|
|
|
#endif
|
|
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
__SAVE_REGFILE_SOFT
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------*/
|
2020-05-20 00:39:09 -07:00
|
|
|
.macro EXCEPTION_PROLOGUE_KEEP_AE
|
2019-05-15 15:36:46 -07:00
|
|
|
|
2020-05-19 16:01:52 -07:00
|
|
|
; Before jumping to Exception Vector, hardware micro-ops did following:
|
2019-05-15 15:36:46 -07:00
|
|
|
; 1. SP auto-switched to kernel mode stack
|
|
|
|
|
; 2. STATUS32.Z flag set if in U mode at time of exception (U:1,K:0)
|
|
|
|
|
;
|
2020-05-19 16:01:52 -07:00
|
|
|
; Now manually save rest of reg file
|
|
|
|
|
; At the end, SP points to pt_regs
|
2019-05-15 15:36:46 -07:00
|
|
|
|
2020-05-19 16:01:52 -07:00
|
|
|
sub sp, sp, SZ_PT_REGS ; carve space for pt_regs
|
2019-05-15 15:36:46 -07:00
|
|
|
|
|
|
|
|
; _HARD saves r10 clobbered by _SOFT as scratch hence comes first
|
|
|
|
|
|
|
|
|
|
__SAVE_REGFILE_HARD
|
|
|
|
|
__SAVE_REGFILE_SOFT
|
|
|
|
|
|
|
|
|
|
st r0, [sp] ; orig_r0
|
|
|
|
|
|
|
|
|
|
lr r10, [eret]
|
|
|
|
|
lr r11, [erstatus]
|
|
|
|
|
ST2 r10, r11, PT_ret
|
|
|
|
|
|
|
|
|
|
lr r10, [ecr]
|
|
|
|
|
lr r11, [erbta]
|
|
|
|
|
ST2 r10, r11, PT_event
|
|
|
|
|
|
2019-05-15 16:08:10 -07:00
|
|
|
; OUTPUT: r10 has ECR expected by EV_Trap
|
2019-05-15 15:36:46 -07:00
|
|
|
.endm
|
|
|
|
|
|
2020-05-20 00:39:09 -07:00
|
|
|
.macro EXCEPTION_PROLOGUE
|
|
|
|
|
|
|
|
|
|
EXCEPTION_PROLOGUE_KEEP_AE ; return ECR in r10
|
|
|
|
|
|
|
|
|
|
lr r0, [efa]
|
|
|
|
|
mov r1, sp
|
|
|
|
|
|
|
|
|
|
FAKE_RET_FROM_EXCPN ; clobbers r9
|
|
|
|
|
.endm
|
|
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
/*------------------------------------------------------------------------
|
|
|
|
|
* This macro saves the registers manually which would normally be autosaved
|
|
|
|
|
* by hardware on taken interrupts. It is used by
|
|
|
|
|
* - exception handlers (which don't have autosave)
|
|
|
|
|
* - interrupt autosave disabled due to CONFIG_ARC_IRQ_NO_AUTOSAVE
|
|
|
|
|
*/
|
|
|
|
|
.macro __SAVE_REGFILE_HARD
|
|
|
|
|
|
|
|
|
|
ST2 r0, r1, PT_r0
|
|
|
|
|
ST2 r2, r3, PT_r2
|
|
|
|
|
ST2 r4, r5, PT_r4
|
|
|
|
|
ST2 r6, r7, PT_r6
|
|
|
|
|
ST2 r8, r9, PT_r8
|
|
|
|
|
ST2 r10, r11, PT_r10
|
|
|
|
|
|
|
|
|
|
st blink, [sp, PT_blink]
|
|
|
|
|
|
|
|
|
|
lr r10, [lp_end]
|
|
|
|
|
lr r11, [lp_start]
|
|
|
|
|
ST2 r10, r11, PT_lpe
|
|
|
|
|
|
|
|
|
|
st lp_count, [sp, PT_lpc]
|
|
|
|
|
|
|
|
|
|
; skip JLI, LDI, EI for now
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------
|
|
|
|
|
* This macros saves a bunch of other registers which can't be autosaved for
|
|
|
|
|
* various reasons:
|
|
|
|
|
* - r12: the last caller saved scratch reg since hardware saves in pairs so r0-r11
|
|
|
|
|
* - r30: free reg, used by gcc as scratch
|
|
|
|
|
* - ACCL/ACCH pair when they exist
|
|
|
|
|
*/
|
|
|
|
|
.macro __SAVE_REGFILE_SOFT
|
|
|
|
|
|
2020-05-22 16:24:53 -07:00
|
|
|
st fp, [sp, PT_fp] ; r27
|
2020-05-19 16:01:52 -07:00
|
|
|
st r30, [sp, PT_r30]
|
2020-05-22 16:24:53 -07:00
|
|
|
st r12, [sp, PT_r12]
|
|
|
|
|
st r26, [sp, PT_r26] ; gp
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
|
|
|
|
; Saving pt_regs->sp correctly requires some extra work due to the way
|
|
|
|
|
; Auto stack switch works
|
|
|
|
|
; - U mode: retrieve it from AUX_USER_SP
|
|
|
|
|
; - K mode: add the offset from current SP where H/w starts auto push
|
|
|
|
|
;
|
2019-04-09 16:55:15 -07:00
|
|
|
; 1. Utilize the fact that Z bit is set if Intr taken in U mode
|
|
|
|
|
; 2. Upon entry SP is always saved (for any inspection, unwinding etc),
|
|
|
|
|
; but on return, restored only if U mode
|
|
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
lr r10, [AUX_USER_SP] ; U mode SP
|
2019-05-10 16:24:15 -07:00
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
; ISA requires ADD.nz to have same dest and src reg operands
|
|
|
|
|
mov.nz r10, sp
|
ARC: entry: replace 8 byte ADD.ne with 4 byte ADD2.ne
ARCv2 current
------------
000007e0 <EV_Trap>:
7e0: 2482 3c01 sub sp,sp,112
7e4: 1c28 3006 std r0r1,[sp,40]
7e8: 1c30 3086 std r2r3,[sp,48]
7ec: 1c38 3106 std r4r5,[sp,56]
7f0: 1c40 3186 std r6r7,[sp,64]
7f4: 1c48 3206 std r8r9,[sp,72]
7f8: 1c50 3286 std r10r11,[sp,80]
7fc: 1c58 37c0 st blink,[sp,88]
800: 1c0c 36c0 st fp,[sp,12]
804: 1c18 3680 st gp,[sp,24]
808: 1c10 3780 st r30,[sp,16]
80c: 1c14 3300 st r12,[sp,20]
810: 226a 1340 lr r10,[aux_user_sp]
814: 22ca 1702 mov.ne r10,sp
818: 22c0 1f82 0000 0070 add.ne r10,r10,0x70
^^^^^^^^^
With fix
--------
000007b4 <EV_Trap>:
7b4: 2482 3c01 sub sp,sp,112
7b8: 1c28 3006 std r0r1,[sp,40]
7bc: 1c30 3086 std r2r3,[sp,48]
7c0: 1c38 3106 std r4r5,[sp,56]
7c4: 1c40 3186 std r6r7,[sp,64]
7c8: 1c48 3206 std r8r9,[sp,72]
7cc: 1c50 3286 std r10r11,[sp,80]
7d0: 1c58 37c0 st blink,[sp,88]
7d4: 1c0c 36c0 st fp,[sp,12]
7d8: 1c18 3680 st gp,[sp,24]
7dc: 1c10 3780 st r30,[sp,16]
7e0: 1c14 3300 st r12,[sp,20]
7e4: 226a 1340 lr r10,[aux_user_sp]
7e8: 22ca 1702 mov.ne r10,sp
7ec: 22d5 1722 add2.ne r10,r10,0x1c
Signed-off-by: Vineet Gupta <vgupta@kernel.org>
2020-06-18 12:31:48 -07:00
|
|
|
add2.nz r10, r10, SZ_PT_REGS/4 ; K mode SP
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
st r10, [sp, PT_sp] ; SP (pt_regs->sp)
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
#ifdef CONFIG_ARC_HAS_ACCL_REGS
|
2019-12-27 21:03:43 +03:00
|
|
|
ST2 r58, r59, PT_r58
|
2019-05-15 15:36:46 -07:00
|
|
|
#endif
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2020-03-05 23:02:50 +03:00
|
|
|
/* clobbers r10, r11 registers pair */
|
|
|
|
|
DSP_SAVE_REGFILE_IRQ
|
2020-05-12 22:18:08 -07:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_ARC_CURR_IN_REG
|
|
|
|
|
GET_CURR_TASK_ON_CPU gp
|
|
|
|
|
#endif
|
|
|
|
|
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------*/
|
2019-05-15 15:36:46 -07:00
|
|
|
.macro __RESTORE_REGFILE_SOFT
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2020-05-22 16:24:53 -07:00
|
|
|
ld fp, [sp, PT_fp]
|
2019-12-27 21:03:43 +03:00
|
|
|
ld r30, [sp, PT_r30]
|
2020-05-22 16:24:53 -07:00
|
|
|
ld r12, [sp, PT_r12]
|
|
|
|
|
ld r26, [sp, PT_r26]
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2019-04-09 16:55:15 -07:00
|
|
|
; Restore SP (into AUX_USER_SP) only if returning to U mode
|
|
|
|
|
; - for K mode, it will be implicitly restored as stack is unwound
|
|
|
|
|
; - Z flag set on K is inverse of what hardware does on interrupt entry
|
|
|
|
|
; but that doesn't really matter
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
bz 1f
|
|
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
ld r10, [sp, PT_sp] ; SP (pt_regs->sp)
|
|
|
|
|
sr r10, [AUX_USER_SP]
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
1:
|
|
|
|
|
|
2020-03-05 23:02:51 +03:00
|
|
|
/* clobbers r10, r11 registers pair */
|
|
|
|
|
DSP_RESTORE_REGFILE_IRQ
|
|
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
#ifdef CONFIG_ARC_HAS_ACCL_REGS
|
2019-12-27 21:03:43 +03:00
|
|
|
LD2 r58, r59, PT_r58
|
2018-06-06 10:20:37 -07:00
|
|
|
#endif
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------*/
|
2019-05-15 15:36:46 -07:00
|
|
|
.macro __RESTORE_REGFILE_HARD
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
ld blink, [sp, PT_blink]
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
LD2 r10, r11, PT_lpe
|
|
|
|
|
sr r10, [lp_end]
|
|
|
|
|
sr r11, [lp_start]
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
ld r10, [sp, PT_lpc] ; lp_count can't be target of LD
|
|
|
|
|
mov lp_count, r10
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
LD2 r0, r1, PT_r0
|
|
|
|
|
LD2 r2, r3, PT_r2
|
|
|
|
|
LD2 r4, r5, PT_r4
|
|
|
|
|
LD2 r6, r7, PT_r6
|
|
|
|
|
LD2 r8, r9, PT_r8
|
|
|
|
|
LD2 r10, r11, PT_r10
|
|
|
|
|
.endm
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
|
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
/*------------------------------------------------------------------------*/
|
|
|
|
|
.macro INTERRUPT_EPILOGUE
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
; INPUT: r0 has STAT32 of calling context
|
|
|
|
|
; INPUT: Z flag set if returning to K mode
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
; _SOFT clobbers r10 restored by _HARD hence the order
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2019-05-15 15:36:46 -07:00
|
|
|
__RESTORE_REGFILE_SOFT
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE
|
|
|
|
|
__RESTORE_REGFILE_HARD
|
2020-04-10 14:22:05 -07:00
|
|
|
|
|
|
|
|
; SP points to PC/STAT32: hw restores them despite NO_AUTOSAVE
|
2019-05-15 15:36:46 -07:00
|
|
|
add sp, sp, SZ_PT_REGS - 8
|
|
|
|
|
#else
|
|
|
|
|
add sp, sp, PT_r0
|
|
|
|
|
#endif
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------*/
|
|
|
|
|
.macro EXCEPTION_EPILOGUE
|
|
|
|
|
|
2019-04-09 16:55:15 -07:00
|
|
|
; INPUT: r0 has STAT32 of calling context
|
2019-05-15 15:36:46 -07:00
|
|
|
|
|
|
|
|
btst r0, STATUS_U_BIT ; Z flag set if K, used in restoring SP
|
|
|
|
|
|
2020-05-19 16:01:52 -07:00
|
|
|
ld r10, [sp, PT_bta]
|
2019-05-15 15:36:46 -07:00
|
|
|
sr r10, [erbta]
|
|
|
|
|
|
|
|
|
|
LD2 r10, r11, PT_ret
|
|
|
|
|
sr r10, [eret]
|
|
|
|
|
sr r11, [erstatus]
|
|
|
|
|
|
|
|
|
|
__RESTORE_REGFILE_SOFT
|
|
|
|
|
__RESTORE_REGFILE_HARD
|
|
|
|
|
|
|
|
|
|
add sp, sp, SZ_PT_REGS
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro FAKE_RET_FROM_EXCPN
|
|
|
|
|
lr r9, [status32]
|
ARC: entry: replace 8 byte OR with 4 byte BSET
FAKE_RET_FROM_EXCEPTION drops down to pure kernel mode. It currently has
an 8 byte instruction which can be replaced with 4 byte BSET
This is applicable to both ARCv2 and ARCv3 entr code.
ARCv2 current
------------
00000804 <EV_Trap>:
...
874: 216a 1280 lr r9,[status32]
878: 2146 1809 bic r9,r9,0x20
87c: 2105 1f89 8000 0000 or r9,r9,0x80000000
^^^^^^^^^
884: 2029 8240 kflag r9
ARCv2 after
----------
000007e0 <EV_Trap>:
...
850: 216a 1280 lr r9,[status32]
854: 2150 1149 bclr r9,r9,0x5
858: 214f 17c9 bset r9,r9,0x1f
85c: 2029 8240 kflag r9
Signed-off-by: Vineet Gupta <vgupta@kernel.org>
2020-06-17 16:23:38 -07:00
|
|
|
bclr r9, r9, STATUS_AE_BIT
|
|
|
|
|
bset r9, r9, STATUS_IE_BIT
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
kflag r9
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* Get thread_info of "current" tsk */
|
|
|
|
|
.macro GET_CURR_THR_INFO_FROM_SP reg
|
|
|
|
|
bmskn \reg, sp, THREAD_SHIFT - 1
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* Get CPU-ID of this core */
|
|
|
|
|
.macro GET_CPU_ID reg
|
|
|
|
|
lr \reg, [identity]
|
|
|
|
|
xbfu \reg, \reg, 0xE8 /* 00111 01000 */
|
|
|
|
|
/* M = 8-1 N = 8 */
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
#endif
|