mirror of
				git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
				synced 2025-11-01 09:13:37 +00:00 
			
		
		
		
	
		
			
	
	
		
			149 lines
		
	
	
	
		
			3.5 KiB
		
	
	
	
		
			Text
		
	
	
	
	
	
		
		
			
		
	
	
			149 lines
		
	
	
	
		
			3.5 KiB
		
	
	
	
		
			Text
		
	
	
	
	
	
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								// SPDX-License-Identifier: GPL-2.0 OR MIT
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								//
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								// Copyright 2019 Armadeus Systems <support@armadeus.com>
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								/ {
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									memory@80000000 {
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										device_type = "memory";
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										reg = <0x80000000 0>; /* will be filled by U-Boot */
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									};
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									reg_3v3: regulator-3v3 {
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										compatible = "regulator-fixed";
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										regulator-name = "3V3";
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										regulator-min-microvolt = <3300000>;
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										regulator-max-microvolt = <3300000>;
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									};
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									usdhc3_pwrseq: usdhc3-pwrseq {
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										compatible = "mmc-pwrseq-simple";
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										reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
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									};
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								};
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								&fec1 {
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									pinctrl-names = "default";
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									pinctrl-0 = <&pinctrl_enet1>;
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									phy-mode = "rmii";
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									phy-reset-duration = <1>;
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									phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
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									phy-handle = <ðphy1>;
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									phy-supply = <®_3v3>;
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									status = "okay";
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									mdio: mdio {
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										#address-cells = <1>;
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										#size-cells = <0>;
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										ethphy1: ethernet-phy@1 {
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											compatible = "ethernet-phy-ieee802.3-c22";
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											reg = <1>;
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											interrupt-parent = <&gpio4>;
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											interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
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											status = "okay";
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										};
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									};
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								};
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								/* Bluetooth */
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								&uart8 {
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									pinctrl-names = "default";
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									pinctrl-0 = <&pinctrl_uart8>;
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									uart-has-rtscts;
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									status = "okay";
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								};
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								/* eMMC */
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								&usdhc1 {
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									pinctrl-names = "default";
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									pinctrl-0 = <&pinctrl_usdhc1>;
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									bus-width = <8>;
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									no-1-8-v;
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									non-removable;
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									status = "okay";
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								};
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								/* WiFi */
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								&usdhc2 {
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									pinctrl-names = "default";
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									pinctrl-0 = <&pinctrl_usdhc2>;
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									bus-width = <4>;
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									no-1-8-v;
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									non-removable;
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									mmc-pwrseq = <&usdhc3_pwrseq>;
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									status = "okay";
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									#address-cells = <1>;
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									#size-cells = <0>;
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									brcmf: wifi@1 {
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										compatible = "brcm,bcm4329-fmac";
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										reg = <1>;
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										interrupt-parent = <&gpio2>;
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										interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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										interrupt-names = "host-wake";
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									};
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								};
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								&iomuxc {
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									pinctrl_enet1: enet1grp {
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										fsl,pins = <
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											MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
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											MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
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											MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x130b0
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											MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x130b0
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											MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x130b0
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											MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x130b0
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											MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
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											MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
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											MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
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											/* INT# */
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											MX6UL_PAD_NAND_DQS__GPIO4_IO16		0x1b0b0
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											/* RST# */
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											MX6UL_PAD_NAND_DATA00__GPIO4_IO02	0x130b0
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											MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
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										>;
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									};
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									pinctrl_uart8: uart8grp {
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										fsl,pins = <
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											MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX	0x1b0b0
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											MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX	0x1b0b0
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											MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS	0x1b0b0
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											MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS	0x1b0b0
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											/* BT_REG_ON */
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											MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x130b0
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										>;
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									};
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									pinctrl_usdhc1: usdhc1grp {
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										fsl,pins = <
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											MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
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											MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
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											MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
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											MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
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											MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
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											MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
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											MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
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											MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
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											MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
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											MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
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										>;
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									};
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									pinctrl_usdhc2: usdhc2grp {
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										fsl,pins = <
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											MX6UL_PAD_LCD_DATA18__USDHC2_CMD	0x1b0b0
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											MX6UL_PAD_LCD_DATA19__USDHC2_CLK	0x100b0
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											MX6UL_PAD_LCD_DATA20__USDHC2_DATA0	0x1b0b0
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											MX6UL_PAD_LCD_DATA21__USDHC2_DATA1	0x1b0b0
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											MX6UL_PAD_LCD_DATA22__USDHC2_DATA2	0x1b0b0
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											MX6UL_PAD_LCD_DATA23__USDHC2_DATA3	0x1b0b0
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											/* WL_REG_ON */
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											MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09	0x130b0
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											/* WL_IRQ */
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											MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x1b0b0
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										>;
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									};
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								};
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