enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/* Copyright 2017-2019 NXP */
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#include <linux/timer.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/dma-mapping.h>
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#include <linux/skbuff.h>
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#include <linux/ethtool.h>
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#include <linux/if_vlan.h>
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2020-10-07 12:48:23 +03:00
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#include <linux/phylink.h>
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2020-07-21 10:55:22 +03:00
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#include <linux/dim.h>
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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#include "enetc_hw.h"
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#define ENETC_MAC_MAXFRM_SIZE 9600
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#define ENETC_MAX_MTU (ENETC_MAC_MAXFRM_SIZE - \
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(ETH_FCS_LEN + ETH_HLEN + VLAN_HLEN))
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struct enetc_tx_swbd {
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struct sk_buff *skb;
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dma_addr_t dma;
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u16 len;
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2019-05-23 02:33:29 +00:00
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u8 is_dma_page:1;
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u8 check_wb:1;
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u8 do_tstamp:1;
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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};
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#define ENETC_RX_MAXFRM_SIZE ENETC_MAC_MAXFRM_SIZE
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#define ENETC_RXB_TRUESIZE 2048 /* PAGE_SIZE >> 1 */
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#define ENETC_RXB_PAD NET_SKB_PAD /* add extra space if needed */
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#define ENETC_RXB_DMA_SIZE \
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(SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - ENETC_RXB_PAD)
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struct enetc_rx_swbd {
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dma_addr_t dma;
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struct page *page;
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u16 page_offset;
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};
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struct enetc_ring_stats {
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unsigned int packets;
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unsigned int bytes;
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unsigned int rx_alloc_errs;
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};
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2020-07-21 10:55:17 +03:00
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#define ENETC_RX_RING_DEFAULT_SIZE 512
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#define ENETC_TX_RING_DEFAULT_SIZE 256
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#define ENETC_DEFAULT_TX_WORK (ENETC_TX_RING_DEFAULT_SIZE / 2)
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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struct enetc_bdr {
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struct device *dev; /* for DMA mapping */
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struct net_device *ndev;
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void *bd_base; /* points to Rx or Tx BD ring */
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union {
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void __iomem *tpir;
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void __iomem *rcir;
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};
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u16 index;
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int bd_count; /* # of BDs */
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int next_to_use;
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int next_to_clean;
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union {
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struct enetc_tx_swbd *tx_swbd;
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struct enetc_rx_swbd *rx_swbd;
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};
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union {
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void __iomem *tcir; /* Tx */
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int next_to_alloc; /* Rx */
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};
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void __iomem *idr; /* Interrupt Detect Register pointer */
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struct enetc_ring_stats stats;
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dma_addr_t bd_dma_base;
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2020-01-02 04:59:24 +00:00
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u8 tsd_enable; /* Time specific departure */
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2020-03-10 14:51:24 +02:00
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bool ext_en; /* enable h/w descriptor extensions */
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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} ____cacheline_aligned_in_smp;
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static inline void enetc_bdr_idx_inc(struct enetc_bdr *bdr, int *i)
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{
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if (unlikely(++*i == bdr->bd_count))
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*i = 0;
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}
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static inline int enetc_bd_unused(struct enetc_bdr *bdr)
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{
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if (bdr->next_to_clean > bdr->next_to_use)
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return bdr->next_to_clean - bdr->next_to_use - 1;
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return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1;
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}
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/* Control BD ring */
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#define ENETC_CBDR_DEFAULT_SIZE 64
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struct enetc_cbdr {
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void *bd_base; /* points to Rx or Tx BD ring */
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void __iomem *pir;
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void __iomem *cir;
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int bd_count; /* # of BDs */
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int next_to_use;
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int next_to_clean;
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dma_addr_t bd_dma_base;
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};
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#define ENETC_TXBD(BDR, i) (&(((union enetc_tx_bd *)((BDR).bd_base))[i]))
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2020-03-10 14:51:23 +02:00
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static inline union enetc_rx_bd *enetc_rxbd(struct enetc_bdr *rx_ring, int i)
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{
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2020-03-10 14:51:24 +02:00
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int hw_idx = i;
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#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
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if (rx_ring->ext_en)
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hw_idx = 2 * i;
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#endif
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return &(((union enetc_rx_bd *)rx_ring->bd_base)[hw_idx]);
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2020-03-10 14:51:23 +02:00
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}
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static inline union enetc_rx_bd *enetc_rxbd_next(struct enetc_bdr *rx_ring,
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union enetc_rx_bd *rxbd,
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int i)
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{
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rxbd++;
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2020-03-10 14:51:24 +02:00
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#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
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if (rx_ring->ext_en)
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rxbd++;
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#endif
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2020-03-10 14:51:23 +02:00
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if (unlikely(++i == rx_ring->bd_count))
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rxbd = rx_ring->bd_base;
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return rxbd;
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}
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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2020-03-10 14:51:24 +02:00
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static inline union enetc_rx_bd *enetc_rxbd_ext(union enetc_rx_bd *rxbd)
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{
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return ++rxbd;
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}
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2019-01-22 15:29:56 +02:00
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struct enetc_msg_swbd {
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void *vaddr;
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dma_addr_t dma;
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int size;
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};
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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#define ENETC_REV1 0x1
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enum enetc_errata {
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ENETC_ERR_TXCSUM = BIT(0),
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ENETC_ERR_VLAN_ISOL = BIT(1),
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ENETC_ERR_UCMCSWP = BIT(2),
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};
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2019-11-15 03:33:41 +00:00
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#define ENETC_SI_F_QBV BIT(0)
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2020-05-01 08:53:17 +08:00
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#define ENETC_SI_F_PSFP BIT(1)
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2019-11-15 03:33:41 +00:00
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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/* PCI IEP device data */
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struct enetc_si {
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struct pci_dev *pdev;
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struct enetc_hw hw;
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enum enetc_errata errata;
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struct net_device *ndev; /* back ref. */
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struct enetc_cbdr cbd_ring;
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int num_rx_rings; /* how many rings are available in the SI */
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int num_tx_rings;
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2019-01-22 15:29:57 +02:00
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int num_fs_entries;
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int num_rss; /* number of RSS buckets */
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
unsigned short pad;
|
2019-11-15 03:33:41 +00:00
|
|
|
int hw_features;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
#define ENETC_SI_ALIGN 32
|
|
|
|
|
|
|
|
static inline void *enetc_si_priv(const struct enetc_si *si)
|
|
|
|
{
|
|
|
|
return (char *)si + ALIGN(sizeof(struct enetc_si), ENETC_SI_ALIGN);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool enetc_si_is_pf(struct enetc_si *si)
|
|
|
|
{
|
|
|
|
return !!(si->hw.port);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define ENETC_MAX_NUM_TXQS 8
|
|
|
|
#define ENETC_INT_NAME_MAX (IFNAMSIZ + 8)
|
|
|
|
|
|
|
|
struct enetc_int_vector {
|
|
|
|
void __iomem *rbier;
|
|
|
|
void __iomem *tbier_base;
|
2020-07-21 10:55:21 +03:00
|
|
|
void __iomem *ricr1;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
unsigned long tx_rings_map;
|
|
|
|
int count_tx_rings;
|
2020-07-21 10:55:21 +03:00
|
|
|
u32 rx_ictt;
|
2020-07-21 10:55:22 +03:00
|
|
|
u16 comp_cnt;
|
|
|
|
bool rx_dim_en, rx_napi_work;
|
|
|
|
struct napi_struct napi ____cacheline_aligned_in_smp;
|
|
|
|
struct dim rx_dim ____cacheline_aligned_in_smp;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
char name[ENETC_INT_NAME_MAX];
|
|
|
|
|
2020-07-21 10:55:20 +03:00
|
|
|
struct enetc_bdr rx_ring;
|
2020-02-24 10:43:46 -06:00
|
|
|
struct enetc_bdr tx_ring[];
|
2020-07-21 10:55:22 +03:00
|
|
|
} ____cacheline_aligned_in_smp;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
2019-01-22 15:29:57 +02:00
|
|
|
struct enetc_cls_rule {
|
|
|
|
struct ethtool_rx_flow_spec fs;
|
|
|
|
int used;
|
|
|
|
};
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
#define ENETC_MAX_BDR_INT 2 /* fixed to max # of available cpus */
|
2020-05-01 08:53:17 +08:00
|
|
|
struct psfp_cap {
|
|
|
|
u32 max_streamid;
|
|
|
|
u32 max_psfp_filter;
|
|
|
|
u32 max_psfp_gate;
|
|
|
|
u32 max_psfp_gatelist;
|
|
|
|
u32 max_psfp_meter;
|
|
|
|
};
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
2019-05-23 02:33:29 +00:00
|
|
|
/* TODO: more hardware offloads */
|
|
|
|
enum enetc_active_offloads {
|
|
|
|
ENETC_F_RX_TSTAMP = BIT(0),
|
|
|
|
ENETC_F_TX_TSTAMP = BIT(1),
|
2019-11-15 03:33:41 +00:00
|
|
|
ENETC_F_QBV = BIT(2),
|
2020-05-01 08:53:17 +08:00
|
|
|
ENETC_F_QCI = BIT(3),
|
2019-05-23 02:33:29 +00:00
|
|
|
};
|
|
|
|
|
2020-07-21 10:55:21 +03:00
|
|
|
/* interrupt coalescing modes */
|
|
|
|
enum enetc_ic_mode {
|
|
|
|
/* one interrupt per frame */
|
|
|
|
ENETC_IC_NONE = 0,
|
|
|
|
/* activated when int coalescing time is set to a non-0 value */
|
|
|
|
ENETC_IC_RX_MANUAL = BIT(0),
|
|
|
|
ENETC_IC_TX_MANUAL = BIT(1),
|
2020-07-21 10:55:22 +03:00
|
|
|
/* use dynamic interrupt moderation */
|
|
|
|
ENETC_IC_RX_ADAPTIVE = BIT(2),
|
2020-07-21 10:55:21 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
#define ENETC_RXIC_PKTTHR min_t(u32, 256, ENETC_RX_RING_DEFAULT_SIZE / 2)
|
|
|
|
#define ENETC_TXIC_PKTTHR min_t(u32, 128, ENETC_TX_RING_DEFAULT_SIZE / 2)
|
2020-07-21 10:55:22 +03:00
|
|
|
#define ENETC_TXIC_TIMETHR enetc_usecs_to_cycles(600)
|
2020-07-21 10:55:21 +03:00
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
struct enetc_ndev_priv {
|
|
|
|
struct net_device *ndev;
|
|
|
|
struct device *dev; /* dma-mapping device */
|
|
|
|
struct enetc_si *si;
|
|
|
|
|
|
|
|
int bdr_int_num; /* number of Rx/Tx ring interrupts */
|
|
|
|
struct enetc_int_vector *int_vector[ENETC_MAX_BDR_INT];
|
|
|
|
u16 num_rx_rings, num_tx_rings;
|
|
|
|
u16 rx_bd_count, tx_bd_count;
|
|
|
|
|
|
|
|
u16 msg_enable;
|
2019-05-23 02:33:29 +00:00
|
|
|
int active_offloads;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
2019-11-15 03:33:41 +00:00
|
|
|
u32 speed; /* store speed for compare update pspeed */
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
struct enetc_bdr *tx_ring[16];
|
|
|
|
struct enetc_bdr *rx_ring[16];
|
|
|
|
|
2019-01-22 15:29:57 +02:00
|
|
|
struct enetc_cls_rule *cls_rules;
|
|
|
|
|
2020-05-01 08:53:17 +08:00
|
|
|
struct psfp_cap psfp_cap;
|
|
|
|
|
2020-10-07 12:48:23 +03:00
|
|
|
struct phylink *phylink;
|
2020-07-21 10:55:21 +03:00
|
|
|
int ic_mode;
|
|
|
|
u32 tx_ictt;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
};
|
|
|
|
|
2019-01-22 15:29:56 +02:00
|
|
|
/* Messaging */
|
|
|
|
|
|
|
|
/* VF-PF set primary MAC address message format */
|
|
|
|
struct enetc_msg_cmd_set_primary_mac {
|
|
|
|
struct enetc_msg_cmd_header header;
|
|
|
|
struct sockaddr mac;
|
|
|
|
};
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
#define ENETC_CBD(R, i) (&(((struct enetc_cbd *)((R).bd_base))[i]))
|
|
|
|
|
|
|
|
#define ENETC_CBDR_TIMEOUT 1000 /* usecs */
|
|
|
|
|
2019-05-23 02:33:33 +00:00
|
|
|
/* PTP driver exports */
|
|
|
|
extern int enetc_phc_index;
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
/* SI common */
|
|
|
|
int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv);
|
|
|
|
void enetc_pci_remove(struct pci_dev *pdev);
|
|
|
|
int enetc_alloc_msix(struct enetc_ndev_priv *priv);
|
|
|
|
void enetc_free_msix(struct enetc_ndev_priv *priv);
|
|
|
|
void enetc_get_si_caps(struct enetc_si *si);
|
|
|
|
void enetc_init_si_rings_params(struct enetc_ndev_priv *priv);
|
|
|
|
int enetc_alloc_si_resources(struct enetc_ndev_priv *priv);
|
|
|
|
void enetc_free_si_resources(struct enetc_ndev_priv *priv);
|
|
|
|
|
|
|
|
int enetc_open(struct net_device *ndev);
|
|
|
|
int enetc_close(struct net_device *ndev);
|
2020-07-21 10:55:21 +03:00
|
|
|
void enetc_start(struct net_device *ndev);
|
|
|
|
void enetc_stop(struct net_device *ndev);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev);
|
|
|
|
struct net_device_stats *enetc_get_stats(struct net_device *ndev);
|
2019-01-22 15:29:57 +02:00
|
|
|
int enetc_set_features(struct net_device *ndev,
|
|
|
|
netdev_features_t features);
|
2019-05-23 02:33:29 +00:00
|
|
|
int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd);
|
2019-05-27 18:21:31 +03:00
|
|
|
int enetc_setup_tc(struct net_device *ndev, enum tc_setup_type type,
|
|
|
|
void *type_data);
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
/* ethtool */
|
|
|
|
void enetc_set_ethtool_ops(struct net_device *ndev);
|
|
|
|
|
|
|
|
/* control buffer descriptor ring (CBDR) */
|
|
|
|
int enetc_set_mac_flt_entry(struct enetc_si *si, int index,
|
|
|
|
char *mac_addr, int si_map);
|
|
|
|
int enetc_clear_mac_flt_entry(struct enetc_si *si, int index);
|
2019-01-22 15:29:57 +02:00
|
|
|
int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse,
|
|
|
|
int index);
|
|
|
|
void enetc_set_rss_key(struct enetc_hw *hw, const u8 *bytes);
|
|
|
|
int enetc_get_rss_table(struct enetc_si *si, u32 *table, int count);
|
|
|
|
int enetc_set_rss_table(struct enetc_si *si, const u32 *table, int count);
|
2019-11-15 03:33:33 +00:00
|
|
|
int enetc_send_cmd(struct enetc_si *si, struct enetc_cbd *cbd);
|
|
|
|
|
|
|
|
#ifdef CONFIG_FSL_ENETC_QOS
|
|
|
|
int enetc_setup_tc_taprio(struct net_device *ndev, void *type_data);
|
2020-10-07 12:48:23 +03:00
|
|
|
void enetc_sched_speed_set(struct enetc_ndev_priv *priv, int speed);
|
2019-11-25 05:56:56 +00:00
|
|
|
int enetc_setup_tc_cbs(struct net_device *ndev, void *type_data);
|
2020-01-02 04:59:24 +00:00
|
|
|
int enetc_setup_tc_txtime(struct net_device *ndev, void *type_data);
|
2020-05-01 08:53:18 +08:00
|
|
|
int enetc_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
|
|
|
|
void *cb_priv);
|
|
|
|
int enetc_setup_tc_psfp(struct net_device *ndev, void *type_data);
|
|
|
|
int enetc_psfp_init(struct enetc_ndev_priv *priv);
|
|
|
|
int enetc_psfp_clean(struct enetc_ndev_priv *priv);
|
2020-05-01 08:53:17 +08:00
|
|
|
|
|
|
|
static inline void enetc_get_max_cap(struct enetc_ndev_priv *priv)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
reg = enetc_port_rd(&priv->si->hw, ENETC_PSIDCAPR);
|
|
|
|
priv->psfp_cap.max_streamid = reg & ENETC_PSIDCAPR_MSK;
|
|
|
|
/* Port stream filter capability */
|
|
|
|
reg = enetc_port_rd(&priv->si->hw, ENETC_PSFCAPR);
|
|
|
|
priv->psfp_cap.max_psfp_filter = reg & ENETC_PSFCAPR_MSK;
|
|
|
|
/* Port stream gate capability */
|
|
|
|
reg = enetc_port_rd(&priv->si->hw, ENETC_PSGCAPR);
|
|
|
|
priv->psfp_cap.max_psfp_gate = (reg & ENETC_PSGCAPR_SGIT_MSK);
|
|
|
|
priv->psfp_cap.max_psfp_gatelist = (reg & ENETC_PSGCAPR_GCL_MSK) >> 16;
|
|
|
|
/* Port flow meter capability */
|
|
|
|
reg = enetc_port_rd(&priv->si->hw, ENETC_PFMCAPR);
|
|
|
|
priv->psfp_cap.max_psfp_meter = reg & ENETC_PFMCAPR_MSK;
|
|
|
|
}
|
|
|
|
|
2020-05-01 08:53:18 +08:00
|
|
|
static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv)
|
2020-05-01 08:53:17 +08:00
|
|
|
{
|
2020-05-01 08:53:18 +08:00
|
|
|
struct enetc_hw *hw = &priv->si->hw;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
enetc_get_max_cap(priv);
|
|
|
|
|
|
|
|
err = enetc_psfp_init(priv);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2020-05-01 08:53:17 +08:00
|
|
|
enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) |
|
|
|
|
ENETC_PPSFPMR_PSFPEN | ENETC_PPSFPMR_VS |
|
|
|
|
ENETC_PPSFPMR_PVC | ENETC_PPSFPMR_PVZC);
|
2020-05-01 08:53:18 +08:00
|
|
|
|
|
|
|
return 0;
|
2020-05-01 08:53:17 +08:00
|
|
|
}
|
|
|
|
|
2020-05-01 08:53:18 +08:00
|
|
|
static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv)
|
2020-05-01 08:53:17 +08:00
|
|
|
{
|
2020-05-01 08:53:18 +08:00
|
|
|
struct enetc_hw *hw = &priv->si->hw;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = enetc_psfp_clean(priv);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2020-05-01 08:53:17 +08:00
|
|
|
enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) &
|
|
|
|
~ENETC_PPSFPMR_PSFPEN & ~ENETC_PPSFPMR_VS &
|
|
|
|
~ENETC_PPSFPMR_PVC & ~ENETC_PPSFPMR_PVZC);
|
2020-05-01 08:53:18 +08:00
|
|
|
|
|
|
|
memset(&priv->psfp_cap, 0, sizeof(struct psfp_cap));
|
|
|
|
|
|
|
|
return 0;
|
2020-05-01 08:53:17 +08:00
|
|
|
}
|
2020-05-01 08:53:18 +08:00
|
|
|
|
2019-11-15 03:33:33 +00:00
|
|
|
#else
|
|
|
|
#define enetc_setup_tc_taprio(ndev, type_data) -EOPNOTSUPP
|
2020-10-07 12:48:23 +03:00
|
|
|
#define enetc_sched_speed_set(priv, speed) (void)0
|
2019-11-25 05:56:56 +00:00
|
|
|
#define enetc_setup_tc_cbs(ndev, type_data) -EOPNOTSUPP
|
2020-01-02 04:59:24 +00:00
|
|
|
#define enetc_setup_tc_txtime(ndev, type_data) -EOPNOTSUPP
|
2020-05-01 08:53:18 +08:00
|
|
|
#define enetc_setup_tc_psfp(ndev, type_data) -EOPNOTSUPP
|
|
|
|
#define enetc_setup_tc_block_cb NULL
|
|
|
|
|
2020-05-01 08:53:17 +08:00
|
|
|
#define enetc_get_max_cap(p) \
|
|
|
|
memset(&((p)->psfp_cap), 0, sizeof(struct psfp_cap))
|
|
|
|
|
2020-05-01 08:53:18 +08:00
|
|
|
static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2019-11-15 03:33:33 +00:00
|
|
|
#endif
|