2009-12-11 19:24:15 +10:00
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/*
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* Copyright 1993-2003 NVIDIA, Corporation
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* Copyright 2006 Dave Airlie
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* Copyright 2007 Maarten Maathuis
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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2012-10-02 18:01:07 +01:00
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#include <drm/drm_crtc_helper.h>
|
2019-05-19 16:00:44 +02:00
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#include <drm/drm_fourcc.h>
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2014-10-29 10:03:57 +01:00
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#include <drm/drm_plane_helper.h>
|
2019-05-19 16:00:44 +02:00
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#include <drm/drm_vblank.h>
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2009-12-11 19:24:15 +10:00
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|
2016-05-20 09:22:55 +10:00
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#include "nouveau_drv.h"
|
2012-07-31 16:16:21 +10:00
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#include "nouveau_reg.h"
|
2016-05-20 09:22:55 +10:00
|
|
|
#include "nouveau_ttm.h"
|
2012-07-31 16:16:21 +10:00
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#include "nouveau_bo.h"
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|
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#include "nouveau_gem.h"
|
2009-12-11 19:24:15 +10:00
|
|
|
#include "nouveau_encoder.h"
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|
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#include "nouveau_connector.h"
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|
|
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#include "nouveau_crtc.h"
|
2013-03-21 15:45:11 +10:00
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#include "hw.h"
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2009-12-11 19:24:15 +10:00
|
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#include "nvreg.h"
|
2010-09-26 06:47:27 -05:00
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#include "nouveau_fbcon.h"
|
2013-03-21 15:45:11 +10:00
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#include "disp.h"
|
2019-02-12 22:28:13 +10:00
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#include "nouveau_dma.h"
|
2012-07-31 16:16:21 +10:00
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#include <subdev/bios/pll.h>
|
2015-01-13 23:37:38 +10:00
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#include <subdev/clk.h>
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2009-12-11 19:24:15 +10:00
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2020-06-22 19:36:18 +10:00
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#include <nvif/push006c.h>
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drm/nouveau/kms/nvd9-: Add CRC support
This introduces support for CRC readback on gf119+, using the
documentation generously provided to us by Nvidia:
https://github.com/NVIDIA/open-gpu-doc/blob/master/Display-CRC/display-crc.txt
We expose all available CRC sources. SF, SOR, PIOR, and DAC are exposed
through a single set of "outp" sources: outp-active/auto for a CRC of
the scanout region, outp-complete for a CRC of both the scanout and
blanking/sync region combined, and outp-inactive for a CRC of only the
blanking/sync region. For each source, nouveau selects the appropriate
tap point based on the output path in use. We also expose an "rg"
source, which allows for capturing CRCs of the scanout raster before
it's encoded into a video signal in the output path. This tap point is
referred to as the raster generator.
Note that while there's some other neat features that can be used with
CRC capture on nvidia hardware, like capturing from two CRC sources
simultaneously, I couldn't see any usecase for them and did not
implement them.
Nvidia only allows for accessing CRCs through a shared DMA region that
we program through the core EVO/NvDisplay channel which is referred to
as the notifier context. The notifier context is limited to either 255
(for Fermi-Pascal) or 2047 (Volta+) entries to store CRCs in, and
unfortunately the hardware simply drops CRCs and reports an overflow
once all available entries in the notifier context are filled.
Since the DRM CRC API and igt-gpu-tools don't expect there to be a limit
on how many CRCs can be captured, we work around this in nouveau by
allocating two separate notifier contexts for each head instead of one.
We schedule a vblank worker ahead of time so that once we start getting
close to filling up all of the available entries in the notifier
context, we can swap the currently used notifier context out with
another pre-prepared notifier context in a manner similar to page
flipping.
Unfortunately, the hardware only allows us to this by flushing two
separate updates on the core channel: one to release the current
notifier context handle, and one to program the next notifier context's
handle. When the hardware processes the first update, the CRC for the
current frame is lost. However, the second update can be flushed
immediately without waiting for the first to complete so that CRC
generation resumes on the next frame. According to Nvidia's hardware
engineers, there isn't any cleaner way of flipping notifier contexts
that would avoid this.
Since using vblank workers to swap out the notifier context will ensure
we can usually flush both updates to hardware within the timespan of a
single frame, we can also ensure that there will only be exactly one
frame lost between the first and second update being executed by the
hardware. This gives us the guarantee that we're always correctly
matching each CRC entry with it's respective frame even after a context
flip. And since IGT will retrieve the CRC entry for a frame by waiting
until it receives a CRC for any subsequent frames, this doesn't cause an
issue with any tests and is much simpler than trying to change the
current DRM API to accommodate.
In order to facilitate testing of correct handling of this limitation,
we also expose a debugfs interface to manually control the threshold for
when we start trying to flip the notifier context. We will use this in
igt to trigger a context flip for testing purposes without needing to
wait for the notifier to completely fill up. This threshold is reset
to the default value set by nouveau after each capture, and is exposed
in a separate folder within each CRTC's debugfs directory labelled
"nv_crc".
Changes since v1:
* Forgot to finish saving crc.h before saving, whoops. This just adds
some corrections to the empty function declarations that we use if
CONFIG_DEBUG_FS isn't enabled.
Changes since v2:
* Don't check return code from debugfs_create_dir() or
debugfs_create_file() - Greg K-H
Changes since v3:
(no functional changes)
* Fix SPDX license identifiers (checkpatch)
* s/uint32_t/u32/ (checkpatch)
* Fix indenting in switch cases (checkpatch)
Changes since v4:
* Remove unneeded param changes with nv50_head_flush_clr/set
* Rebase
Changes since v5:
* Remove set but unused variable (outp) in nv50_crc_atomic_check() -
Kbuild bot
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200627194657.156514-10-lyude@redhat.com
2019-10-07 14:20:12 -04:00
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#include <nvif/event.h>
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#include <nvif/cl0046.h>
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|
2009-12-11 19:24:15 +10:00
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static int
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nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb);
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static void
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crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
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{
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NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
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crtcstate->CRTC[index]);
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}
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static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
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{
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
2012-07-18 10:00:50 +10:00
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struct drm_device *dev = crtc->dev;
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struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
|
2009-12-11 19:24:15 +10:00
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regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
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if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
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regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
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regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
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crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
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}
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crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
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}
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static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
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{
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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2012-07-18 10:00:50 +10:00
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struct drm_device *dev = crtc->dev;
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struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
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2009-12-11 19:24:15 +10:00
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nv_crtc->sharpness = level;
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if (level < 0) /* blur is in hw range 0x3f -> 0x20 */
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level += 0x40;
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regp->ramdac_634 = level;
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NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
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}
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#define PLLSEL_VPLL1_MASK \
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(NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \
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| NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
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#define PLLSEL_VPLL2_MASK \
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(NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \
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| NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
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#define PLLSEL_TV_MASK \
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(NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
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| NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \
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| NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
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| NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
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/* NV4x 0x40.. pll notes:
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* gpu pll: 0x4000 + 0x4004
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* ?gpu? pll: 0x4008 + 0x400c
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* vpll1: 0x4010 + 0x4014
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* vpll2: 0x4018 + 0x401c
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* mpll: 0x4020 + 0x4024
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* mpll: 0x4038 + 0x403c
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*
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* the first register of each pair has some unknown details:
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* bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
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* bits 20-23: (mpll) something to do with post divider?
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* bits 28-31: related to single stage mode? (bit 8/12)
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*/
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static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
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{
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struct drm_device *dev = crtc->dev;
|
2012-07-31 16:16:21 +10:00
|
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|
struct nouveau_drm *drm = nouveau_drm(dev);
|
2016-05-18 13:57:42 +10:00
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struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
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struct nvkm_clk *clk = nvxx_clk(&drm->client.device);
|
2009-12-11 19:24:15 +10:00
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
2012-07-18 10:00:50 +10:00
|
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struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
|
2009-12-11 19:24:15 +10:00
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struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
|
2015-01-14 15:36:34 +10:00
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struct nvkm_pll_vals *pv = ®p->pllvals;
|
2012-07-10 17:26:46 +10:00
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struct nvbios_pll pll_lim;
|
2009-12-11 19:24:15 +10:00
|
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|
2012-07-31 16:16:21 +10:00
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if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
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&pll_lim))
|
2009-12-11 19:24:15 +10:00
|
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return;
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/* NM2 == 0 is used to determine single stage mode on two stage plls */
|
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pv->NM2 = 0;
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/* for newer nv4x the blob uses only the first stage of the vpll below a
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* certain clock. for a certain nv4b this is 150MHz. since the max
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* output frequency of the first stage for this card is 300MHz, it is
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* assumed the threshold is given by vco1 maxfreq/2
|
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*/
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/* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
|
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* not 8, others unknown), the blob always uses both plls. no problem
|
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* has yet been observed in allowing the use a single stage pll on all
|
|
|
|
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* nv43 however. the behaviour of single stage use is untested on nv40
|
|
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|
|
*/
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
|
2009-12-11 19:24:15 +10:00
|
|
|
memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
|
|
|
|
|
|
2012-07-31 16:16:21 +10:00
|
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|
|
|
|
|
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if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv))
|
2009-12-11 19:24:15 +10:00
|
|
|
return;
|
|
|
|
|
|
|
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|
|
state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
|
|
|
|
|
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|
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/* The blob uses this always, so let's do the same */
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
|
2009-12-11 19:24:15 +10:00
|
|
|
state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
|
|
|
|
|
/* again nv40 and some nv43 act more like nv3x as described above */
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.chipset < 0x41)
|
2009-12-11 19:24:15 +10:00
|
|
|
state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
|
|
|
|
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NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
|
|
|
|
|
state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
|
|
|
|
|
|
|
|
|
|
if (pv->NM2)
|
2012-07-31 16:16:21 +10:00
|
|
|
NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
|
2009-12-11 19:24:15 +10:00
|
|
|
pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
|
|
|
|
|
else
|
2012-07-31 16:16:21 +10:00
|
|
|
NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n",
|
2009-12-11 19:24:15 +10:00
|
|
|
pv->N1, pv->M1, pv->log2P);
|
|
|
|
|
|
|
|
|
|
nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
nv_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|
|
|
|
{
|
|
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2012-07-31 16:16:21 +10:00
|
|
|
struct nouveau_drm *drm = nouveau_drm(dev);
|
2009-12-11 19:24:15 +10:00
|
|
|
unsigned char seq1 = 0, crtc17 = 0;
|
|
|
|
|
unsigned char crtc1A;
|
|
|
|
|
|
2012-07-31 16:16:21 +10:00
|
|
|
NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode,
|
2009-12-11 19:24:15 +10:00
|
|
|
nv_crtc->index);
|
|
|
|
|
|
2011-03-30 22:57:33 -03:00
|
|
|
if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
|
2009-12-11 19:24:15 +10:00
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
nv_crtc->last_dpms = mode;
|
|
|
|
|
|
|
|
|
|
if (nv_two_heads(dev))
|
|
|
|
|
NVSetOwner(dev, nv_crtc->index);
|
|
|
|
|
|
|
|
|
|
/* nv4ref indicates these two RPC1 bits inhibit h/v sync */
|
|
|
|
|
crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,
|
|
|
|
|
NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
|
|
|
|
|
switch (mode) {
|
|
|
|
|
case DRM_MODE_DPMS_STANDBY:
|
|
|
|
|
/* Screen: Off; HSync: Off, VSync: On -- Not Supported */
|
|
|
|
|
seq1 = 0x20;
|
|
|
|
|
crtc17 = 0x80;
|
|
|
|
|
crtc1A |= 0x80;
|
|
|
|
|
break;
|
|
|
|
|
case DRM_MODE_DPMS_SUSPEND:
|
|
|
|
|
/* Screen: Off; HSync: On, VSync: Off -- Not Supported */
|
|
|
|
|
seq1 = 0x20;
|
|
|
|
|
crtc17 = 0x80;
|
|
|
|
|
crtc1A |= 0x40;
|
|
|
|
|
break;
|
|
|
|
|
case DRM_MODE_DPMS_OFF:
|
|
|
|
|
/* Screen: Off; HSync: Off, VSync: Off */
|
|
|
|
|
seq1 = 0x20;
|
|
|
|
|
crtc17 = 0x00;
|
|
|
|
|
crtc1A |= 0xC0;
|
|
|
|
|
break;
|
|
|
|
|
case DRM_MODE_DPMS_ON:
|
|
|
|
|
default:
|
|
|
|
|
/* Screen: On; HSync: On, VSync: On */
|
|
|
|
|
seq1 = 0x00;
|
|
|
|
|
crtc17 = 0x80;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
NVVgaSeqReset(dev, nv_crtc->index, true);
|
|
|
|
|
/* Each head has it's own sequencer, so we can turn it off when we want */
|
|
|
|
|
seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
|
|
|
|
|
NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
|
|
|
|
|
crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);
|
|
|
|
|
mdelay(10);
|
|
|
|
|
NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
|
|
|
|
|
NVVgaSeqReset(dev, nv_crtc->index, false);
|
|
|
|
|
|
|
|
|
|
NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
2012-07-18 10:00:50 +10:00
|
|
|
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
|
2014-04-01 15:22:40 -07:00
|
|
|
struct drm_framebuffer *fb = crtc->primary->fb;
|
2009-12-11 19:24:15 +10:00
|
|
|
|
|
|
|
|
/* Calculate our timings */
|
2010-03-05 15:15:39 +01:00
|
|
|
int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
|
|
|
|
|
int horizStart = (mode->crtc_hsync_start >> 3) + 1;
|
|
|
|
|
int horizEnd = (mode->crtc_hsync_end >> 3) + 1;
|
2009-12-11 19:24:15 +10:00
|
|
|
int horizTotal = (mode->crtc_htotal >> 3) - 5;
|
|
|
|
|
int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1;
|
|
|
|
|
int horizBlankEnd = (mode->crtc_htotal >> 3) - 1;
|
|
|
|
|
int vertDisplay = mode->crtc_vdisplay - 1;
|
|
|
|
|
int vertStart = mode->crtc_vsync_start - 1;
|
|
|
|
|
int vertEnd = mode->crtc_vsync_end - 1;
|
|
|
|
|
int vertTotal = mode->crtc_vtotal - 2;
|
|
|
|
|
int vertBlankStart = mode->crtc_vdisplay - 1;
|
|
|
|
|
int vertBlankEnd = mode->crtc_vtotal - 1;
|
|
|
|
|
|
|
|
|
|
struct drm_encoder *encoder;
|
|
|
|
|
bool fp_output = false;
|
|
|
|
|
|
|
|
|
|
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
|
|
|
|
|
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
|
|
|
|
|
|
|
|
|
|
if (encoder->crtc == crtc &&
|
2012-07-11 10:44:20 +10:00
|
|
|
(nv_encoder->dcb->type == DCB_OUTPUT_LVDS ||
|
|
|
|
|
nv_encoder->dcb->type == DCB_OUTPUT_TMDS))
|
2009-12-11 19:24:15 +10:00
|
|
|
fp_output = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (fp_output) {
|
|
|
|
|
vertStart = vertTotal - 3;
|
|
|
|
|
vertEnd = vertTotal - 2;
|
|
|
|
|
vertBlankStart = vertStart;
|
|
|
|
|
horizStart = horizTotal - 5;
|
|
|
|
|
horizEnd = horizTotal - 2;
|
|
|
|
|
horizBlankEnd = horizTotal + 4;
|
|
|
|
|
#if 0
|
2016-05-18 13:57:42 +10:00
|
|
|
if (dev->overlayAdaptor && drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
|
2009-12-11 19:24:15 +10:00
|
|
|
/* This reportedly works around some video overlay bandwidth problems */
|
|
|
|
|
horizTotal += 2;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
|
|
|
|
|
vertTotal |= 1;
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
ErrorF("horizDisplay: 0x%X \n", horizDisplay);
|
|
|
|
|
ErrorF("horizStart: 0x%X \n", horizStart);
|
|
|
|
|
ErrorF("horizEnd: 0x%X \n", horizEnd);
|
|
|
|
|
ErrorF("horizTotal: 0x%X \n", horizTotal);
|
|
|
|
|
ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
|
|
|
|
|
ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
|
|
|
|
|
ErrorF("vertDisplay: 0x%X \n", vertDisplay);
|
|
|
|
|
ErrorF("vertStart: 0x%X \n", vertStart);
|
|
|
|
|
ErrorF("vertEnd: 0x%X \n", vertEnd);
|
|
|
|
|
ErrorF("vertTotal: 0x%X \n", vertTotal);
|
|
|
|
|
ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
|
|
|
|
|
ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* compute correct Hsync & Vsync polarity
|
|
|
|
|
*/
|
|
|
|
|
if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))
|
|
|
|
|
&& (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) {
|
|
|
|
|
|
|
|
|
|
regp->MiscOutReg = 0x23;
|
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
|
|
|
|
|
regp->MiscOutReg |= 0x40;
|
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
|
|
|
|
|
regp->MiscOutReg |= 0x80;
|
|
|
|
|
} else {
|
|
|
|
|
int vdisplay = mode->vdisplay;
|
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
|
|
|
|
vdisplay *= 2;
|
|
|
|
|
if (mode->vscan > 1)
|
|
|
|
|
vdisplay *= mode->vscan;
|
|
|
|
|
if (vdisplay < 400)
|
|
|
|
|
regp->MiscOutReg = 0xA3; /* +hsync -vsync */
|
|
|
|
|
else if (vdisplay < 480)
|
|
|
|
|
regp->MiscOutReg = 0x63; /* -hsync +vsync */
|
|
|
|
|
else if (vdisplay < 768)
|
|
|
|
|
regp->MiscOutReg = 0xE3; /* -hsync -vsync */
|
|
|
|
|
else
|
|
|
|
|
regp->MiscOutReg = 0x23; /* +hsync +vsync */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Time Sequencer
|
|
|
|
|
*/
|
|
|
|
|
regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
|
|
|
|
|
/* 0x20 disables the sequencer */
|
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_CLKDIV2)
|
|
|
|
|
regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
|
|
|
|
|
else
|
|
|
|
|
regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
|
|
|
|
|
regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
|
|
|
|
|
regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
|
|
|
|
|
regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* CRTC
|
|
|
|
|
*/
|
|
|
|
|
regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
|
|
|
|
|
XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0);
|
|
|
|
|
regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
|
|
|
|
|
XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0);
|
|
|
|
|
regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
|
|
|
|
|
XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) |
|
|
|
|
|
XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) |
|
|
|
|
|
(1 << 4) |
|
|
|
|
|
XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) |
|
|
|
|
|
XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) |
|
|
|
|
|
XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) |
|
|
|
|
|
XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8);
|
|
|
|
|
regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
|
|
|
|
|
1 << 6 |
|
|
|
|
|
XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9);
|
|
|
|
|
regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
|
|
|
|
|
regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
|
|
|
|
|
/* framebuffer can be larger than crtc scanout area. */
|
2011-12-20 00:06:49 +02:00
|
|
|
regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
|
2009-12-11 19:24:15 +10:00
|
|
|
regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
|
|
|
|
|
regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Some extended CRTC registers (they are not saved with the rest of the vga regs).
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* framebuffer can be larger than crtc scanout area. */
|
2011-05-24 15:57:14 +02:00
|
|
|
regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
|
2011-12-20 00:06:49 +02:00
|
|
|
XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
|
2011-05-24 15:57:14 +02:00
|
|
|
regp->CRTC[NV_CIO_CRE_42] =
|
2011-12-20 00:06:49 +02:00
|
|
|
XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
|
2009-12-11 19:24:15 +10:00
|
|
|
regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
|
|
|
|
|
MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
|
|
|
|
|
XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) |
|
|
|
|
|
XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) |
|
|
|
|
|
XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) |
|
|
|
|
|
XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10);
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
|
|
|
|
|
XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) |
|
|
|
|
|
XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) |
|
|
|
|
|
XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8);
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
|
|
|
|
|
XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) |
|
|
|
|
|
XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) |
|
|
|
|
|
XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11);
|
|
|
|
|
|
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
|
|
|
|
|
horizTotal = (horizTotal >> 1) & ~1;
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
|
|
|
|
|
} else
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Graphics Display Controller
|
|
|
|
|
*/
|
|
|
|
|
regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
|
|
|
|
|
regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
|
|
|
|
|
regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
|
|
|
|
|
regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
|
|
|
|
|
regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
|
|
|
|
|
regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
|
|
|
|
|
regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
|
|
|
|
|
regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
|
|
|
|
|
regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
|
|
|
|
|
|
|
|
|
|
regp->Attribute[0] = 0x00; /* standard colormap translation */
|
|
|
|
|
regp->Attribute[1] = 0x01;
|
|
|
|
|
regp->Attribute[2] = 0x02;
|
|
|
|
|
regp->Attribute[3] = 0x03;
|
|
|
|
|
regp->Attribute[4] = 0x04;
|
|
|
|
|
regp->Attribute[5] = 0x05;
|
|
|
|
|
regp->Attribute[6] = 0x06;
|
|
|
|
|
regp->Attribute[7] = 0x07;
|
|
|
|
|
regp->Attribute[8] = 0x08;
|
|
|
|
|
regp->Attribute[9] = 0x09;
|
|
|
|
|
regp->Attribute[10] = 0x0A;
|
|
|
|
|
regp->Attribute[11] = 0x0B;
|
|
|
|
|
regp->Attribute[12] = 0x0C;
|
|
|
|
|
regp->Attribute[13] = 0x0D;
|
|
|
|
|
regp->Attribute[14] = 0x0E;
|
|
|
|
|
regp->Attribute[15] = 0x0F;
|
|
|
|
|
regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
|
|
|
|
|
/* Non-vga */
|
|
|
|
|
regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
|
|
|
|
|
regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
|
|
|
|
|
regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
|
|
|
|
|
regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Sets up registers for the given mode/adjusted_mode pair.
|
|
|
|
|
*
|
|
|
|
|
* The clocks, CRTCs and outputs attached to this CRTC must be off.
|
|
|
|
|
*
|
|
|
|
|
* This shouldn't enable any clocks, CRTCs, or outputs, but they should
|
|
|
|
|
* be easily turned on/off after this.
|
|
|
|
|
*/
|
|
|
|
|
static void
|
|
|
|
|
nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2012-07-31 16:16:21 +10:00
|
|
|
struct nouveau_drm *drm = nouveau_drm(dev);
|
2009-12-11 19:24:15 +10:00
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
2012-07-18 10:00:50 +10:00
|
|
|
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
|
|
|
|
|
struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
|
2016-11-18 21:52:47 +02:00
|
|
|
const struct drm_framebuffer *fb = crtc->primary->fb;
|
2009-12-11 19:24:15 +10:00
|
|
|
struct drm_encoder *encoder;
|
|
|
|
|
bool lvds_output = false, tmds_output = false, tv_output = false,
|
|
|
|
|
off_chip_digital = false;
|
|
|
|
|
|
|
|
|
|
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
|
|
|
|
|
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
|
|
|
|
|
bool digital = false;
|
|
|
|
|
|
|
|
|
|
if (encoder->crtc != crtc)
|
|
|
|
|
continue;
|
|
|
|
|
|
2012-07-11 10:44:20 +10:00
|
|
|
if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
|
2009-12-11 19:24:15 +10:00
|
|
|
digital = lvds_output = true;
|
2012-07-11 10:44:20 +10:00
|
|
|
if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
|
2009-12-11 19:24:15 +10:00
|
|
|
tv_output = true;
|
2012-07-11 10:44:20 +10:00
|
|
|
if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS)
|
2009-12-11 19:24:15 +10:00
|
|
|
digital = tmds_output = true;
|
|
|
|
|
if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital)
|
|
|
|
|
off_chip_digital = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Registers not directly related to the (s)vga mode */
|
|
|
|
|
|
|
|
|
|
/* What is the meaning of this register? */
|
|
|
|
|
/* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
|
|
|
|
|
|
|
|
|
|
regp->crtc_eng_ctrl = 0;
|
|
|
|
|
/* Except for rare conditions I2C is enabled on the primary crtc */
|
|
|
|
|
if (nv_crtc->index == 0)
|
|
|
|
|
regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
|
|
|
|
|
#if 0
|
|
|
|
|
/* Set overlay to desired crtc. */
|
|
|
|
|
if (dev->overlayAdaptor) {
|
|
|
|
|
NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
|
|
|
|
|
if (pPriv->overlayCRTC == nv_crtc->index)
|
|
|
|
|
regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
|
|
|
|
|
regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
|
|
|
|
|
NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
|
|
|
|
|
NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.chipset >= 0x11)
|
2009-12-11 19:24:15 +10:00
|
|
|
regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
|
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
|
|
|
|
regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
|
|
|
|
|
|
|
|
|
|
/* Unblock some timings */
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_53] = 0;
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_54] = 0;
|
|
|
|
|
|
|
|
|
|
/* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
|
|
|
|
|
if (lvds_output)
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
|
|
|
|
|
else if (tmds_output)
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
|
|
|
|
|
else
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
|
|
|
|
|
|
|
|
|
|
/* These values seem to vary */
|
|
|
|
|
/* This register seems to be used by the bios to make certain decisions on some G70 cards? */
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
|
|
|
|
|
|
|
|
|
|
nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation);
|
|
|
|
|
|
|
|
|
|
/* probably a scratch reg, but kept for cargo-cult purposes:
|
|
|
|
|
* bit0: crtc0?, head A
|
|
|
|
|
* bit6: lvds, head A
|
|
|
|
|
* bit7: (only in X), head A
|
|
|
|
|
*/
|
|
|
|
|
if (nv_crtc->index == 0)
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
|
|
|
|
|
|
|
|
|
|
/* The blob seems to take the current value from crtc 0, add 4 to that
|
|
|
|
|
* and reuse the old value for crtc 1 */
|
2012-07-18 10:00:50 +10:00
|
|
|
regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
|
2009-12-11 19:24:15 +10:00
|
|
|
if (!nv_crtc->index)
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
|
|
|
|
|
|
|
|
|
|
/* the blob sometimes sets |= 0x10 (which is the same as setting |=
|
|
|
|
|
* 1 << 30 on 0x60.830), for no apparent reason */
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
|
|
|
|
|
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
|
2010-07-20 16:48:08 +02:00
|
|
|
regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
|
|
|
|
|
|
2009-12-11 19:24:15 +10:00
|
|
|
regp->crtc_830 = mode->crtc_vdisplay - 3;
|
|
|
|
|
regp->crtc_834 = mode->crtc_vdisplay - 1;
|
|
|
|
|
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
|
2009-12-11 19:24:15 +10:00
|
|
|
/* This is what the blob does */
|
|
|
|
|
regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
|
|
|
|
|
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
|
2009-12-11 19:24:15 +10:00
|
|
|
regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
|
|
|
|
|
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
|
2010-10-22 04:31:02 +02:00
|
|
|
regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
|
|
|
|
|
else
|
|
|
|
|
regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
|
2009-12-11 19:24:15 +10:00
|
|
|
|
|
|
|
|
/* Some misc regs */
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
|
2009-12-11 19:24:15 +10:00
|
|
|
regp->CRTC[NV_CIO_CRE_85] = 0xFF;
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_86] = 0x1;
|
|
|
|
|
}
|
|
|
|
|
|
2016-12-14 23:31:35 +02:00
|
|
|
regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8;
|
2009-12-11 19:24:15 +10:00
|
|
|
/* Enable slaved mode (called MODE_TV in nv4ref.h) */
|
|
|
|
|
if (lvds_output || tmds_output || tv_output)
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
|
|
|
|
|
|
|
|
|
|
/* Generic PRAMDAC regs */
|
|
|
|
|
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
|
2009-12-11 19:24:15 +10:00
|
|
|
/* Only bit that bios and blob set. */
|
|
|
|
|
regp->nv10_cursync = (1 << 25);
|
|
|
|
|
|
|
|
|
|
regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
|
|
|
|
|
NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
|
|
|
|
|
NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
|
2016-12-14 23:31:35 +02:00
|
|
|
if (fb->format->depth == 16)
|
2009-12-11 19:24:15 +10:00
|
|
|
regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.chipset >= 0x11)
|
2009-12-11 19:24:15 +10:00
|
|
|
regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
|
|
|
|
|
|
|
|
|
|
regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
|
|
|
|
|
regp->tv_setup = 0;
|
|
|
|
|
|
|
|
|
|
nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
|
|
|
|
|
|
|
|
|
|
/* Some values the blob sets */
|
|
|
|
|
regp->ramdac_8c0 = 0x100;
|
|
|
|
|
regp->ramdac_a20 = 0x0;
|
|
|
|
|
regp->ramdac_a24 = 0xfffff;
|
|
|
|
|
regp->ramdac_a34 = 0x1;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-21 11:30:36 +10:00
|
|
|
static int
|
|
|
|
|
nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
|
|
|
|
|
{
|
|
|
|
|
struct nv04_display *disp = nv04_display(crtc->dev);
|
2020-02-06 11:19:41 +01:00
|
|
|
struct drm_framebuffer *fb = crtc->primary->fb;
|
|
|
|
|
struct nouveau_bo *nvbo = nouveau_gem_object(fb->obj[0]);
|
2013-08-21 11:30:36 +10:00
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
|
|
|
int ret;
|
|
|
|
|
|
2020-09-08 14:39:36 +02:00
|
|
|
ret = nouveau_bo_pin(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, false);
|
2013-08-21 11:30:36 +10:00
|
|
|
if (ret == 0) {
|
|
|
|
|
if (disp->image[nv_crtc->index])
|
|
|
|
|
nouveau_bo_unpin(disp->image[nv_crtc->index]);
|
2020-02-06 11:19:41 +01:00
|
|
|
nouveau_bo_ref(nvbo, &disp->image[nv_crtc->index]);
|
2013-08-21 11:30:36 +10:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2009-12-11 19:24:15 +10:00
|
|
|
/**
|
|
|
|
|
* Sets up registers for the given mode/adjusted_mode pair.
|
|
|
|
|
*
|
|
|
|
|
* The clocks, CRTCs and outputs attached to this CRTC must be off.
|
|
|
|
|
*
|
|
|
|
|
* This shouldn't enable any clocks, CRTCs, or outputs, but they should
|
|
|
|
|
* be easily turned on/off after this.
|
|
|
|
|
*/
|
|
|
|
|
static int
|
|
|
|
|
nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
|
|
|
|
|
struct drm_display_mode *adjusted_mode,
|
|
|
|
|
int x, int y, struct drm_framebuffer *old_fb)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
2012-07-31 16:16:21 +10:00
|
|
|
struct nouveau_drm *drm = nouveau_drm(dev);
|
2013-08-21 11:30:36 +10:00
|
|
|
int ret;
|
2009-12-11 19:24:15 +10:00
|
|
|
|
2012-07-31 16:16:21 +10:00
|
|
|
NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
|
2009-12-11 19:24:15 +10:00
|
|
|
drm_mode_debug_printmodeline(adjusted_mode);
|
|
|
|
|
|
2013-08-21 11:30:36 +10:00
|
|
|
ret = nv_crtc_swap_fbs(crtc, old_fb);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
2009-12-11 19:24:15 +10:00
|
|
|
/* unlock must come after turning off FP_TG_CONTROL in output_prepare */
|
|
|
|
|
nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
|
|
|
|
|
|
|
|
|
|
nv_crtc_mode_set_vga(crtc, adjusted_mode);
|
|
|
|
|
/* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
|
2012-07-18 10:00:50 +10:00
|
|
|
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
|
2009-12-11 19:24:15 +10:00
|
|
|
nv_crtc_mode_set_regs(crtc, adjusted_mode);
|
|
|
|
|
nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void nv_crtc_save(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
2012-07-18 10:00:50 +10:00
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
|
struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
|
2009-12-11 19:24:15 +10:00
|
|
|
struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
|
2012-07-18 10:00:50 +10:00
|
|
|
struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg;
|
2009-12-11 19:24:15 +10:00
|
|
|
struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
|
|
|
|
|
|
|
|
|
|
if (nv_two_heads(crtc->dev))
|
|
|
|
|
NVSetOwner(crtc->dev, nv_crtc->index);
|
|
|
|
|
|
|
|
|
|
nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);
|
|
|
|
|
|
|
|
|
|
/* init some state to saved value */
|
|
|
|
|
state->sel_clk = saved->sel_clk & ~(0x5 << 16);
|
|
|
|
|
crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];
|
|
|
|
|
state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK);
|
|
|
|
|
crtc_state->gpio_ext = crtc_saved->gpio_ext;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void nv_crtc_restore(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
2012-07-18 10:00:50 +10:00
|
|
|
struct drm_device *dev = crtc->dev;
|
2009-12-11 19:24:15 +10:00
|
|
|
int head = nv_crtc->index;
|
2012-07-18 10:00:50 +10:00
|
|
|
uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
|
2009-12-11 19:24:15 +10:00
|
|
|
|
|
|
|
|
if (nv_two_heads(crtc->dev))
|
|
|
|
|
NVSetOwner(crtc->dev, head);
|
|
|
|
|
|
2012-07-18 10:00:50 +10:00
|
|
|
nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg);
|
2009-12-11 19:24:15 +10:00
|
|
|
nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21);
|
|
|
|
|
|
|
|
|
|
nv_crtc->last_dpms = NV_DPMS_CLEARED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void nv_crtc_prepare(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2012-07-31 16:16:21 +10:00
|
|
|
struct nouveau_drm *drm = nouveau_drm(dev);
|
2009-12-11 19:24:15 +10:00
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
2015-03-11 11:51:04 +02:00
|
|
|
const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
|
2009-12-11 19:24:15 +10:00
|
|
|
|
|
|
|
|
if (nv_two_heads(dev))
|
|
|
|
|
NVSetOwner(dev, nv_crtc->index);
|
|
|
|
|
|
2016-11-15 22:58:19 +01:00
|
|
|
drm_crtc_vblank_off(crtc);
|
2009-12-11 19:24:15 +10:00
|
|
|
funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
|
|
|
|
|
|
|
|
|
|
NVBlankScreen(dev, nv_crtc->index, true);
|
|
|
|
|
|
2011-03-30 22:57:33 -03:00
|
|
|
/* Some more preparation. */
|
2009-12-11 19:24:15 +10:00
|
|
|
NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
|
2009-12-11 19:24:15 +10:00
|
|
|
uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
|
|
|
|
|
NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void nv_crtc_commit(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2015-03-11 11:51:04 +02:00
|
|
|
const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
|
2009-12-11 19:24:15 +10:00
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
|
|
|
|
2012-07-18 10:00:50 +10:00
|
|
|
nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
|
2009-12-11 19:24:15 +10:00
|
|
|
nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL);
|
|
|
|
|
|
|
|
|
|
#ifdef __BIG_ENDIAN
|
|
|
|
|
/* turn on LFB swapping */
|
|
|
|
|
{
|
|
|
|
|
uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);
|
|
|
|
|
tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
|
|
|
|
|
NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
funcs->dpms(crtc, DRM_MODE_DPMS_ON);
|
2016-11-15 22:58:19 +01:00
|
|
|
drm_crtc_vblank_on(crtc);
|
2009-12-11 19:24:15 +10:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void nv_crtc_destroy(struct drm_crtc *crtc)
|
|
|
|
|
{
|
2013-08-21 11:30:36 +10:00
|
|
|
struct nv04_display *disp = nv04_display(crtc->dev);
|
2009-12-11 19:24:15 +10:00
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
|
|
|
|
|
|
|
|
if (!nv_crtc)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
drm_crtc_cleanup(crtc);
|
|
|
|
|
|
2013-08-21 11:30:36 +10:00
|
|
|
if (disp->image[nv_crtc->index])
|
|
|
|
|
nouveau_bo_unpin(disp->image[nv_crtc->index]);
|
|
|
|
|
nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
|
|
|
|
|
|
2010-08-27 13:04:41 +10:00
|
|
|
nouveau_bo_unmap(nv_crtc->cursor.nvbo);
|
2012-11-25 23:04:23 +01:00
|
|
|
nouveau_bo_unpin(nv_crtc->cursor.nvbo);
|
2009-12-11 19:24:15 +10:00
|
|
|
nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
|
2020-06-08 14:47:37 +10:00
|
|
|
nvif_notify_dtor(&nv_crtc->vblank);
|
2009-12-11 19:24:15 +10:00
|
|
|
kfree(nv_crtc);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
nv_crtc_gamma_load(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
|
|
|
struct drm_device *dev = nv_crtc->base.dev;
|
|
|
|
|
struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
|
2017-07-13 18:25:35 +02:00
|
|
|
u16 *r, *g, *b;
|
2009-12-11 19:24:15 +10:00
|
|
|
int i;
|
|
|
|
|
|
2012-07-18 10:00:50 +10:00
|
|
|
rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
|
2017-07-13 18:25:35 +02:00
|
|
|
r = crtc->gamma_store;
|
|
|
|
|
g = r + crtc->gamma_size;
|
|
|
|
|
b = g + crtc->gamma_size;
|
|
|
|
|
|
2009-12-11 19:24:15 +10:00
|
|
|
for (i = 0; i < 256; i++) {
|
2017-07-13 18:25:35 +02:00
|
|
|
rgbs[i].r = *r++ >> 8;
|
|
|
|
|
rgbs[i].g = *g++ >> 8;
|
|
|
|
|
rgbs[i].b = *b++ >> 8;
|
2009-12-11 19:24:15 +10:00
|
|
|
}
|
|
|
|
|
|
2012-07-18 10:00:50 +10:00
|
|
|
nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
|
2009-12-11 19:24:15 +10:00
|
|
|
}
|
|
|
|
|
|
2013-08-21 11:30:36 +10:00
|
|
|
static void
|
|
|
|
|
nv_crtc_disable(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct nv04_display *disp = nv04_display(crtc->dev);
|
|
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
|
|
|
if (disp->image[nv_crtc->index])
|
|
|
|
|
nouveau_bo_unpin(disp->image[nv_crtc->index]);
|
|
|
|
|
nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-07 12:49:30 +02:00
|
|
|
static int
|
|
|
|
|
nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
|
2017-04-03 10:33:01 +02:00
|
|
|
uint32_t size,
|
|
|
|
|
struct drm_modeset_acquire_ctx *ctx)
|
2009-12-11 19:24:15 +10:00
|
|
|
{
|
|
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
|
|
|
|
|
|
|
|
/* We need to know the depth before we upload, but it's possible to
|
|
|
|
|
* get called before a framebuffer is bound. If this is the case,
|
|
|
|
|
* mark the lut values as dirty by setting depth==0, and it'll be
|
|
|
|
|
* uploaded on the first mode_set_base()
|
|
|
|
|
*/
|
2014-04-01 15:22:40 -07:00
|
|
|
if (!nv_crtc->base.primary->fb) {
|
2009-12-11 19:24:15 +10:00
|
|
|
nv_crtc->lut.depth = 0;
|
2016-06-07 12:49:30 +02:00
|
|
|
return 0;
|
2009-12-11 19:24:15 +10:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
nv_crtc_gamma_load(crtc);
|
2016-06-07 12:49:30 +02:00
|
|
|
|
|
|
|
|
return 0;
|
2009-12-11 19:24:15 +10:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
2010-09-26 06:47:24 -05:00
|
|
|
nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
|
|
|
|
|
struct drm_framebuffer *passed_fb,
|
|
|
|
|
int x, int y, bool atomic)
|
2009-12-11 19:24:15 +10:00
|
|
|
{
|
|
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2012-07-31 16:16:21 +10:00
|
|
|
struct nouveau_drm *drm = nouveau_drm(dev);
|
2012-07-18 10:00:50 +10:00
|
|
|
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
|
2020-02-06 11:19:41 +01:00
|
|
|
struct nouveau_bo *nvbo;
|
2011-08-25 21:36:51 +01:00
|
|
|
struct drm_framebuffer *drm_fb;
|
2009-12-11 19:24:15 +10:00
|
|
|
int arb_burst, arb_lwm;
|
|
|
|
|
|
2012-07-31 16:16:21 +10:00
|
|
|
NV_DEBUG(drm, "index %d\n", nv_crtc->index);
|
2011-08-25 21:36:51 +01:00
|
|
|
|
|
|
|
|
/* no fb bound */
|
2014-04-01 15:22:40 -07:00
|
|
|
if (!atomic && !crtc->primary->fb) {
|
2012-07-31 16:16:21 +10:00
|
|
|
NV_DEBUG(drm, "No FB bound\n");
|
2011-08-25 21:36:51 +01:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2010-09-26 06:47:24 -05:00
|
|
|
/* If atomic, we want to switch to the fb we were passed, so
|
2013-08-21 11:30:36 +10:00
|
|
|
* now we update pointers to do that.
|
2010-09-26 06:47:24 -05:00
|
|
|
*/
|
|
|
|
|
if (atomic) {
|
|
|
|
|
drm_fb = passed_fb;
|
2011-03-19 23:31:53 +00:00
|
|
|
} else {
|
2014-04-01 15:22:40 -07:00
|
|
|
drm_fb = crtc->primary->fb;
|
2009-12-11 19:24:15 +10:00
|
|
|
}
|
|
|
|
|
|
2020-02-06 11:19:41 +01:00
|
|
|
nvbo = nouveau_gem_object(drm_fb->obj[0]);
|
2020-06-29 12:15:51 +02:00
|
|
|
nv_crtc->fb.offset = nvbo->offset;
|
2009-12-11 19:24:15 +10:00
|
|
|
|
2016-12-14 23:31:35 +02:00
|
|
|
if (nv_crtc->lut.depth != drm_fb->format->depth) {
|
|
|
|
|
nv_crtc->lut.depth = drm_fb->format->depth;
|
2009-12-11 19:24:15 +10:00
|
|
|
nv_crtc_gamma_load(crtc);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Update the framebuffer format. */
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
|
2016-12-14 23:31:35 +02:00
|
|
|
regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8;
|
2009-12-11 19:24:15 +10:00
|
|
|
regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
|
2016-12-14 23:31:35 +02:00
|
|
|
if (drm_fb->format->depth == 16)
|
2009-12-11 19:24:15 +10:00
|
|
|
regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
|
|
|
|
|
crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
|
|
|
|
|
NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
|
|
|
|
|
regp->ramdac_gen_ctrl);
|
|
|
|
|
|
2011-12-20 00:06:49 +02:00
|
|
|
regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
|
2009-12-11 19:24:15 +10:00
|
|
|
regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
|
2011-12-20 00:06:49 +02:00
|
|
|
XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
|
2011-05-24 15:57:14 +02:00
|
|
|
regp->CRTC[NV_CIO_CRE_42] =
|
2011-12-20 00:06:49 +02:00
|
|
|
XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
|
2009-12-11 19:24:15 +10:00
|
|
|
crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
|
|
|
|
|
crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
|
2011-05-24 15:57:14 +02:00
|
|
|
crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
|
2009-12-11 19:24:15 +10:00
|
|
|
|
|
|
|
|
/* Update the framebuffer location. */
|
|
|
|
|
regp->fb_start = nv_crtc->fb.offset & ~3;
|
2016-12-14 23:32:20 +02:00
|
|
|
regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]);
|
2010-10-22 04:39:14 +02:00
|
|
|
nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
|
2009-12-11 19:24:15 +10:00
|
|
|
|
|
|
|
|
/* Update the arbitration parameters. */
|
2016-12-14 23:32:20 +02:00
|
|
|
nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8,
|
2009-12-11 19:24:15 +10:00
|
|
|
&arb_burst, &arb_lwm);
|
|
|
|
|
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
|
|
|
|
|
regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
|
|
|
|
|
crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
|
|
|
|
|
crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
|
|
|
|
|
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) {
|
2009-12-11 19:24:15 +10:00
|
|
|
regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
|
|
|
|
|
crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2010-09-26 06:47:24 -05:00
|
|
|
static int
|
|
|
|
|
nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
|
|
|
|
|
struct drm_framebuffer *old_fb)
|
|
|
|
|
{
|
2013-08-21 11:30:36 +10:00
|
|
|
int ret = nv_crtc_swap_fbs(crtc, old_fb);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
2010-09-26 06:47:24 -05:00
|
|
|
return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
|
|
|
|
|
struct drm_framebuffer *fb,
|
2010-10-13 14:09:44 -05:00
|
|
|
int x, int y, enum mode_set_atomic state)
|
2010-09-26 06:47:24 -05:00
|
|
|
{
|
2012-07-31 16:16:21 +10:00
|
|
|
struct nouveau_drm *drm = nouveau_drm(crtc->dev);
|
|
|
|
|
struct drm_device *dev = drm->dev;
|
2010-09-26 06:47:27 -05:00
|
|
|
|
2010-10-13 14:09:44 -05:00
|
|
|
if (state == ENTER_ATOMIC_MODE_SET)
|
2014-06-28 20:44:07 +10:00
|
|
|
nouveau_fbcon_accel_save_disable(dev);
|
2010-09-26 06:47:27 -05:00
|
|
|
else
|
2014-06-28 20:44:07 +10:00
|
|
|
nouveau_fbcon_accel_restore(dev);
|
2010-09-26 06:47:27 -05:00
|
|
|
|
2010-09-26 06:47:24 -05:00
|
|
|
return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);
|
|
|
|
|
}
|
|
|
|
|
|
2009-12-11 19:24:15 +10:00
|
|
|
static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
|
|
|
|
|
struct nouveau_bo *dst)
|
|
|
|
|
{
|
|
|
|
|
int width = nv_cursor_width(dev);
|
|
|
|
|
uint32_t pixel;
|
|
|
|
|
int i, j;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < width; i++) {
|
|
|
|
|
for (j = 0; j < width; j++) {
|
|
|
|
|
pixel = nouveau_bo_rd32(src, i*64 + j);
|
|
|
|
|
|
|
|
|
|
nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16
|
|
|
|
|
| (pixel & 0xf80000) >> 9
|
|
|
|
|
| (pixel & 0xf800) >> 6
|
|
|
|
|
| (pixel & 0xf8) >> 3);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
|
|
|
|
|
struct nouveau_bo *dst)
|
|
|
|
|
{
|
|
|
|
|
uint32_t pixel;
|
|
|
|
|
int alpha, i;
|
|
|
|
|
|
|
|
|
|
/* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha
|
|
|
|
|
* cursors (though NPM in combination with fp dithering may not work on
|
|
|
|
|
* nv11, from "nv" driver history)
|
|
|
|
|
* NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the
|
|
|
|
|
* blob uses, however we get given PM cursors so we use PM mode
|
|
|
|
|
*/
|
|
|
|
|
for (i = 0; i < 64 * 64; i++) {
|
|
|
|
|
pixel = nouveau_bo_rd32(src, i);
|
|
|
|
|
|
|
|
|
|
/* hw gets unhappy if alpha <= rgb values. for a PM image "less
|
|
|
|
|
* than" shouldn't happen; fix "equal to" case by adding one to
|
|
|
|
|
* alpha channel (slightly inaccurate, but so is attempting to
|
|
|
|
|
* get back to NPM images, due to limits of integer precision)
|
|
|
|
|
*/
|
|
|
|
|
alpha = pixel >> 24;
|
|
|
|
|
if (alpha > 0 && alpha < 255)
|
|
|
|
|
pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
|
|
|
|
|
|
|
|
|
|
#ifdef __BIG_ENDIAN
|
|
|
|
|
{
|
2012-07-31 16:16:21 +10:00
|
|
|
struct nouveau_drm *drm = nouveau_drm(dev);
|
2009-12-11 19:24:15 +10:00
|
|
|
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.chipset == 0x11) {
|
2009-12-11 19:24:15 +10:00
|
|
|
pixel = ((pixel & 0x000000ff) << 24) |
|
|
|
|
|
((pixel & 0x0000ff00) << 8) |
|
|
|
|
|
((pixel & 0x00ff0000) >> 8) |
|
|
|
|
|
((pixel & 0xff000000) >> 24);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
nouveau_bo_wr32(dst, i, pixel);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
|
|
|
|
|
uint32_t buffer_handle, uint32_t width, uint32_t height)
|
|
|
|
|
{
|
2012-07-31 16:16:21 +10:00
|
|
|
struct nouveau_drm *drm = nouveau_drm(crtc->dev);
|
|
|
|
|
struct drm_device *dev = drm->dev;
|
2009-12-11 19:24:15 +10:00
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
|
|
|
struct nouveau_bo *cursor = NULL;
|
|
|
|
|
struct drm_gem_object *gem;
|
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
if (!buffer_handle) {
|
|
|
|
|
nv_crtc->cursor.hide(nv_crtc, true);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-05-01 23:49:04 +02:00
|
|
|
if (width != 64 || height != 64)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
2016-05-09 11:04:54 +01:00
|
|
|
gem = drm_gem_object_lookup(file_priv, buffer_handle);
|
2009-12-11 19:24:15 +10:00
|
|
|
if (!gem)
|
2010-08-04 14:19:46 +01:00
|
|
|
return -ENOENT;
|
2009-12-11 19:24:15 +10:00
|
|
|
cursor = nouveau_gem_object(gem);
|
|
|
|
|
|
|
|
|
|
ret = nouveau_bo_map(cursor);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto out;
|
|
|
|
|
|
2016-05-18 13:57:42 +10:00
|
|
|
if (drm->client.device.info.chipset >= 0x11)
|
2009-12-11 19:24:15 +10:00
|
|
|
nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
|
|
|
|
|
else
|
|
|
|
|
nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
|
|
|
|
|
|
|
|
|
|
nouveau_bo_unmap(cursor);
|
2020-06-24 20:26:44 +02:00
|
|
|
nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->offset;
|
2009-12-11 19:24:15 +10:00
|
|
|
nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
|
|
|
|
|
nv_crtc->cursor.show(nv_crtc, true);
|
|
|
|
|
out:
|
2020-05-15 10:51:05 +01:00
|
|
|
drm_gem_object_put(gem);
|
2009-12-11 19:24:15 +10:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
|
|
|
|
|
{
|
|
|
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
|
|
|
|
|
|
|
|
|
|
nv_crtc->cursor.set_pos(nv_crtc, x, y);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-02-12 22:28:13 +10:00
|
|
|
struct nv04_page_flip_state {
|
|
|
|
|
struct list_head head;
|
|
|
|
|
struct drm_pending_vblank_event *event;
|
|
|
|
|
struct drm_crtc *crtc;
|
|
|
|
|
int bpp, pitch;
|
|
|
|
|
u64 offset;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
nv04_finish_page_flip(struct nouveau_channel *chan,
|
|
|
|
|
struct nv04_page_flip_state *ps)
|
|
|
|
|
{
|
|
|
|
|
struct nouveau_fence_chan *fctx = chan->fence;
|
|
|
|
|
struct nouveau_drm *drm = chan->drm;
|
|
|
|
|
struct drm_device *dev = drm->dev;
|
|
|
|
|
struct nv04_page_flip_state *s;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
|
|
|
|
|
|
|
|
if (list_empty(&fctx->flip)) {
|
|
|
|
|
NV_ERROR(drm, "unexpected pageflip\n");
|
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
s = list_first_entry(&fctx->flip, struct nv04_page_flip_state, head);
|
|
|
|
|
if (s->event) {
|
|
|
|
|
drm_crtc_arm_vblank_event(s->crtc, s->event);
|
|
|
|
|
} else {
|
|
|
|
|
/* Give up ownership of vblank for page-flipped crtc */
|
|
|
|
|
drm_crtc_vblank_put(s->crtc);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
list_del(&s->head);
|
|
|
|
|
if (ps)
|
|
|
|
|
*ps = *s;
|
|
|
|
|
kfree(s);
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
nv04_flip_complete(struct nvif_notify *notify)
|
|
|
|
|
{
|
|
|
|
|
struct nouveau_cli *cli = (void *)notify->object->client;
|
|
|
|
|
struct nouveau_drm *drm = cli->drm;
|
|
|
|
|
struct nouveau_channel *chan = drm->channel;
|
|
|
|
|
struct nv04_page_flip_state state;
|
|
|
|
|
|
|
|
|
|
if (!nv04_finish_page_flip(chan, &state)) {
|
|
|
|
|
nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc),
|
|
|
|
|
state.offset + state.crtc->y *
|
|
|
|
|
state.pitch + state.crtc->x *
|
|
|
|
|
state.bpp / 8);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return NVIF_NOTIFY_KEEP;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
nv04_page_flip_emit(struct nouveau_channel *chan,
|
|
|
|
|
struct nouveau_bo *old_bo,
|
|
|
|
|
struct nouveau_bo *new_bo,
|
|
|
|
|
struct nv04_page_flip_state *s,
|
|
|
|
|
struct nouveau_fence **pfence)
|
|
|
|
|
{
|
|
|
|
|
struct nouveau_fence_chan *fctx = chan->fence;
|
|
|
|
|
struct nouveau_drm *drm = chan->drm;
|
|
|
|
|
struct drm_device *dev = drm->dev;
|
2020-06-22 19:36:18 +10:00
|
|
|
struct nvif_push *push = chan->chan.push;
|
2019-02-12 22:28:13 +10:00
|
|
|
unsigned long flags;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
/* Queue it to the pending list */
|
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
|
|
|
list_add_tail(&s->head, &fctx->flip);
|
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
|
|
|
|
|
|
/* Synchronize with the old framebuffer */
|
|
|
|
|
ret = nouveau_fence_sync(old_bo, chan, false, false);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
|
|
/* Emit the pageflip */
|
2020-06-22 19:36:18 +10:00
|
|
|
ret = PUSH_WAIT(push, 2);
|
2019-02-12 22:28:13 +10:00
|
|
|
if (ret)
|
|
|
|
|
goto fail;
|
|
|
|
|
|
2020-06-22 19:36:18 +10:00
|
|
|
PUSH_NVSQ(push, NV_SW, NV_SW_PAGE_FLIP, 0x00000000);
|
|
|
|
|
PUSH_KICK(push);
|
2019-02-12 22:28:13 +10:00
|
|
|
|
|
|
|
|
ret = nouveau_fence_new(chan, false, pfence);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
fail:
|
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
|
|
|
list_del(&s->head);
|
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
|
|
|
|
|
struct drm_pending_vblank_event *event, u32 flags,
|
|
|
|
|
struct drm_modeset_acquire_ctx *ctx)
|
|
|
|
|
{
|
|
|
|
|
const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1;
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
|
struct nouveau_drm *drm = nouveau_drm(dev);
|
2020-02-06 11:19:41 +01:00
|
|
|
struct drm_framebuffer *old_fb = crtc->primary->fb;
|
|
|
|
|
struct nouveau_bo *old_bo = nouveau_gem_object(old_fb->obj[0]);
|
|
|
|
|
struct nouveau_bo *new_bo = nouveau_gem_object(fb->obj[0]);
|
2019-02-12 22:28:13 +10:00
|
|
|
struct nv04_page_flip_state *s;
|
|
|
|
|
struct nouveau_channel *chan;
|
|
|
|
|
struct nouveau_cli *cli;
|
|
|
|
|
struct nouveau_fence *fence;
|
|
|
|
|
struct nv04_display *dispnv04 = nv04_display(dev);
|
2020-06-22 19:39:36 +10:00
|
|
|
struct nvif_push *push;
|
2019-02-12 22:28:13 +10:00
|
|
|
int head = nouveau_crtc(crtc)->index;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
chan = drm->channel;
|
|
|
|
|
if (!chan)
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
cli = (void *)chan->user.client;
|
2020-06-22 19:39:36 +10:00
|
|
|
push = chan->chan.push;
|
2019-02-12 22:28:13 +10:00
|
|
|
|
|
|
|
|
s = kzalloc(sizeof(*s), GFP_KERNEL);
|
|
|
|
|
if (!s)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
if (new_bo != old_bo) {
|
2020-09-08 14:39:36 +02:00
|
|
|
ret = nouveau_bo_pin(new_bo, NOUVEAU_GEM_DOMAIN_VRAM, true);
|
2019-02-12 22:28:13 +10:00
|
|
|
if (ret)
|
|
|
|
|
goto fail_free;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mutex_lock(&cli->mutex);
|
|
|
|
|
ret = ttm_bo_reserve(&new_bo->bo, true, false, NULL);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto fail_unpin;
|
|
|
|
|
|
|
|
|
|
/* synchronise rendering channel with the kernel's channel */
|
|
|
|
|
ret = nouveau_fence_sync(new_bo, chan, false, true);
|
|
|
|
|
if (ret) {
|
|
|
|
|
ttm_bo_unreserve(&new_bo->bo);
|
|
|
|
|
goto fail_unpin;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (new_bo != old_bo) {
|
|
|
|
|
ttm_bo_unreserve(&new_bo->bo);
|
|
|
|
|
|
|
|
|
|
ret = ttm_bo_reserve(&old_bo->bo, true, false, NULL);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto fail_unpin;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Initialize a page flip struct */
|
|
|
|
|
*s = (struct nv04_page_flip_state)
|
|
|
|
|
{ { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0],
|
2020-06-24 20:26:44 +02:00
|
|
|
new_bo->offset };
|
2019-02-12 22:28:13 +10:00
|
|
|
|
|
|
|
|
/* Keep vblanks on during flip, for the target crtc of this flip */
|
|
|
|
|
drm_crtc_vblank_get(crtc);
|
|
|
|
|
|
|
|
|
|
/* Emit a page flip */
|
|
|
|
|
if (swap_interval) {
|
2020-06-22 19:39:36 +10:00
|
|
|
ret = PUSH_WAIT(push, 8);
|
2019-02-12 22:28:13 +10:00
|
|
|
if (ret)
|
|
|
|
|
goto fail_unreserve;
|
|
|
|
|
|
2020-06-22 19:39:36 +10:00
|
|
|
PUSH_NVSQ(push, NV05F, 0x012c, 0);
|
|
|
|
|
PUSH_NVSQ(push, NV05F, 0x0134, head);
|
|
|
|
|
PUSH_NVSQ(push, NV05F, 0x0100, 0);
|
|
|
|
|
PUSH_NVSQ(push, NV05F, 0x0130, 0);
|
2019-02-12 22:28:13 +10:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
nouveau_bo_ref(new_bo, &dispnv04->image[head]);
|
|
|
|
|
|
|
|
|
|
ret = nv04_page_flip_emit(chan, old_bo, new_bo, s, &fence);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto fail_unreserve;
|
|
|
|
|
mutex_unlock(&cli->mutex);
|
|
|
|
|
|
|
|
|
|
/* Update the crtc struct and cleanup */
|
|
|
|
|
crtc->primary->fb = fb;
|
|
|
|
|
|
|
|
|
|
nouveau_bo_fence(old_bo, fence, false);
|
|
|
|
|
ttm_bo_unreserve(&old_bo->bo);
|
|
|
|
|
if (old_bo != new_bo)
|
|
|
|
|
nouveau_bo_unpin(old_bo);
|
|
|
|
|
nouveau_fence_unref(&fence);
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
fail_unreserve:
|
|
|
|
|
drm_crtc_vblank_put(crtc);
|
|
|
|
|
ttm_bo_unreserve(&old_bo->bo);
|
|
|
|
|
fail_unpin:
|
|
|
|
|
mutex_unlock(&cli->mutex);
|
|
|
|
|
if (old_bo != new_bo)
|
|
|
|
|
nouveau_bo_unpin(new_bo);
|
|
|
|
|
fail_free:
|
|
|
|
|
kfree(s);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2009-12-11 19:24:15 +10:00
|
|
|
static const struct drm_crtc_funcs nv04_crtc_funcs = {
|
|
|
|
|
.cursor_set = nv04_crtc_cursor_set,
|
|
|
|
|
.cursor_move = nv04_crtc_cursor_move,
|
|
|
|
|
.gamma_set = nv_crtc_gamma_set,
|
2019-08-07 19:47:05 -04:00
|
|
|
.set_config = drm_crtc_helper_set_config,
|
2019-02-12 22:28:13 +10:00
|
|
|
.page_flip = nv04_crtc_page_flip,
|
2009-12-11 19:24:15 +10:00
|
|
|
.destroy = nv_crtc_destroy,
|
2020-01-23 14:59:30 +01:00
|
|
|
.enable_vblank = nouveau_display_vblank_enable,
|
|
|
|
|
.disable_vblank = nouveau_display_vblank_disable,
|
|
|
|
|
.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
|
2009-12-11 19:24:15 +10:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
|
|
|
|
|
.dpms = nv_crtc_dpms,
|
|
|
|
|
.prepare = nv_crtc_prepare,
|
|
|
|
|
.commit = nv_crtc_commit,
|
|
|
|
|
.mode_set = nv_crtc_mode_set,
|
|
|
|
|
.mode_set_base = nv04_crtc_mode_set_base,
|
2010-09-26 06:47:24 -05:00
|
|
|
.mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
|
2013-08-21 11:30:36 +10:00
|
|
|
.disable = nv_crtc_disable,
|
2020-01-23 14:59:29 +01:00
|
|
|
.get_scanout_position = nouveau_display_scanoutpos,
|
2009-12-11 19:24:15 +10:00
|
|
|
};
|
|
|
|
|
|
2017-08-05 22:25:05 -04:00
|
|
|
static const uint32_t modeset_formats[] = {
|
|
|
|
|
DRM_FORMAT_XRGB8888,
|
|
|
|
|
DRM_FORMAT_RGB565,
|
|
|
|
|
DRM_FORMAT_XRGB1555,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct drm_plane *
|
|
|
|
|
create_primary_plane(struct drm_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct drm_plane *primary;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
primary = kzalloc(sizeof(*primary), GFP_KERNEL);
|
|
|
|
|
if (primary == NULL) {
|
|
|
|
|
DRM_DEBUG_KMS("Failed to allocate primary plane\n");
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* possible_crtc's will be filled in later by crtc_init */
|
|
|
|
|
ret = drm_universal_plane_init(dev, primary, 0,
|
|
|
|
|
&drm_primary_helper_funcs,
|
|
|
|
|
modeset_formats,
|
|
|
|
|
ARRAY_SIZE(modeset_formats), NULL,
|
|
|
|
|
DRM_PLANE_TYPE_PRIMARY, NULL);
|
|
|
|
|
if (ret) {
|
|
|
|
|
kfree(primary);
|
|
|
|
|
primary = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return primary;
|
|
|
|
|
}
|
|
|
|
|
|
drm/nouveau/kms/nvd9-: Add CRC support
This introduces support for CRC readback on gf119+, using the
documentation generously provided to us by Nvidia:
https://github.com/NVIDIA/open-gpu-doc/blob/master/Display-CRC/display-crc.txt
We expose all available CRC sources. SF, SOR, PIOR, and DAC are exposed
through a single set of "outp" sources: outp-active/auto for a CRC of
the scanout region, outp-complete for a CRC of both the scanout and
blanking/sync region combined, and outp-inactive for a CRC of only the
blanking/sync region. For each source, nouveau selects the appropriate
tap point based on the output path in use. We also expose an "rg"
source, which allows for capturing CRCs of the scanout raster before
it's encoded into a video signal in the output path. This tap point is
referred to as the raster generator.
Note that while there's some other neat features that can be used with
CRC capture on nvidia hardware, like capturing from two CRC sources
simultaneously, I couldn't see any usecase for them and did not
implement them.
Nvidia only allows for accessing CRCs through a shared DMA region that
we program through the core EVO/NvDisplay channel which is referred to
as the notifier context. The notifier context is limited to either 255
(for Fermi-Pascal) or 2047 (Volta+) entries to store CRCs in, and
unfortunately the hardware simply drops CRCs and reports an overflow
once all available entries in the notifier context are filled.
Since the DRM CRC API and igt-gpu-tools don't expect there to be a limit
on how many CRCs can be captured, we work around this in nouveau by
allocating two separate notifier contexts for each head instead of one.
We schedule a vblank worker ahead of time so that once we start getting
close to filling up all of the available entries in the notifier
context, we can swap the currently used notifier context out with
another pre-prepared notifier context in a manner similar to page
flipping.
Unfortunately, the hardware only allows us to this by flushing two
separate updates on the core channel: one to release the current
notifier context handle, and one to program the next notifier context's
handle. When the hardware processes the first update, the CRC for the
current frame is lost. However, the second update can be flushed
immediately without waiting for the first to complete so that CRC
generation resumes on the next frame. According to Nvidia's hardware
engineers, there isn't any cleaner way of flipping notifier contexts
that would avoid this.
Since using vblank workers to swap out the notifier context will ensure
we can usually flush both updates to hardware within the timespan of a
single frame, we can also ensure that there will only be exactly one
frame lost between the first and second update being executed by the
hardware. This gives us the guarantee that we're always correctly
matching each CRC entry with it's respective frame even after a context
flip. And since IGT will retrieve the CRC entry for a frame by waiting
until it receives a CRC for any subsequent frames, this doesn't cause an
issue with any tests and is much simpler than trying to change the
current DRM API to accommodate.
In order to facilitate testing of correct handling of this limitation,
we also expose a debugfs interface to manually control the threshold for
when we start trying to flip the notifier context. We will use this in
igt to trigger a context flip for testing purposes without needing to
wait for the notifier to completely fill up. This threshold is reset
to the default value set by nouveau after each capture, and is exposed
in a separate folder within each CRTC's debugfs directory labelled
"nv_crc".
Changes since v1:
* Forgot to finish saving crc.h before saving, whoops. This just adds
some corrections to the empty function declarations that we use if
CONFIG_DEBUG_FS isn't enabled.
Changes since v2:
* Don't check return code from debugfs_create_dir() or
debugfs_create_file() - Greg K-H
Changes since v3:
(no functional changes)
* Fix SPDX license identifiers (checkpatch)
* s/uint32_t/u32/ (checkpatch)
* Fix indenting in switch cases (checkpatch)
Changes since v4:
* Remove unneeded param changes with nv50_head_flush_clr/set
* Rebase
Changes since v5:
* Remove set but unused variable (outp) in nv50_crc_atomic_check() -
Kbuild bot
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200627194657.156514-10-lyude@redhat.com
2019-10-07 14:20:12 -04:00
|
|
|
static int nv04_crtc_vblank_handler(struct nvif_notify *notify)
|
|
|
|
|
{
|
|
|
|
|
struct nouveau_crtc *nv_crtc =
|
|
|
|
|
container_of(notify, struct nouveau_crtc, vblank);
|
|
|
|
|
|
|
|
|
|
drm_crtc_handle_vblank(&nv_crtc->base);
|
|
|
|
|
return NVIF_NOTIFY_KEEP;
|
|
|
|
|
}
|
|
|
|
|
|
2009-12-11 19:24:15 +10:00
|
|
|
int
|
|
|
|
|
nv04_crtc_create(struct drm_device *dev, int crtc_num)
|
|
|
|
|
{
|
drm/nouveau/kms/nvd9-: Add CRC support
This introduces support for CRC readback on gf119+, using the
documentation generously provided to us by Nvidia:
https://github.com/NVIDIA/open-gpu-doc/blob/master/Display-CRC/display-crc.txt
We expose all available CRC sources. SF, SOR, PIOR, and DAC are exposed
through a single set of "outp" sources: outp-active/auto for a CRC of
the scanout region, outp-complete for a CRC of both the scanout and
blanking/sync region combined, and outp-inactive for a CRC of only the
blanking/sync region. For each source, nouveau selects the appropriate
tap point based on the output path in use. We also expose an "rg"
source, which allows for capturing CRCs of the scanout raster before
it's encoded into a video signal in the output path. This tap point is
referred to as the raster generator.
Note that while there's some other neat features that can be used with
CRC capture on nvidia hardware, like capturing from two CRC sources
simultaneously, I couldn't see any usecase for them and did not
implement them.
Nvidia only allows for accessing CRCs through a shared DMA region that
we program through the core EVO/NvDisplay channel which is referred to
as the notifier context. The notifier context is limited to either 255
(for Fermi-Pascal) or 2047 (Volta+) entries to store CRCs in, and
unfortunately the hardware simply drops CRCs and reports an overflow
once all available entries in the notifier context are filled.
Since the DRM CRC API and igt-gpu-tools don't expect there to be a limit
on how many CRCs can be captured, we work around this in nouveau by
allocating two separate notifier contexts for each head instead of one.
We schedule a vblank worker ahead of time so that once we start getting
close to filling up all of the available entries in the notifier
context, we can swap the currently used notifier context out with
another pre-prepared notifier context in a manner similar to page
flipping.
Unfortunately, the hardware only allows us to this by flushing two
separate updates on the core channel: one to release the current
notifier context handle, and one to program the next notifier context's
handle. When the hardware processes the first update, the CRC for the
current frame is lost. However, the second update can be flushed
immediately without waiting for the first to complete so that CRC
generation resumes on the next frame. According to Nvidia's hardware
engineers, there isn't any cleaner way of flipping notifier contexts
that would avoid this.
Since using vblank workers to swap out the notifier context will ensure
we can usually flush both updates to hardware within the timespan of a
single frame, we can also ensure that there will only be exactly one
frame lost between the first and second update being executed by the
hardware. This gives us the guarantee that we're always correctly
matching each CRC entry with it's respective frame even after a context
flip. And since IGT will retrieve the CRC entry for a frame by waiting
until it receives a CRC for any subsequent frames, this doesn't cause an
issue with any tests and is much simpler than trying to change the
current DRM API to accommodate.
In order to facilitate testing of correct handling of this limitation,
we also expose a debugfs interface to manually control the threshold for
when we start trying to flip the notifier context. We will use this in
igt to trigger a context flip for testing purposes without needing to
wait for the notifier to completely fill up. This threshold is reset
to the default value set by nouveau after each capture, and is exposed
in a separate folder within each CRTC's debugfs directory labelled
"nv_crc".
Changes since v1:
* Forgot to finish saving crc.h before saving, whoops. This just adds
some corrections to the empty function declarations that we use if
CONFIG_DEBUG_FS isn't enabled.
Changes since v2:
* Don't check return code from debugfs_create_dir() or
debugfs_create_file() - Greg K-H
Changes since v3:
(no functional changes)
* Fix SPDX license identifiers (checkpatch)
* s/uint32_t/u32/ (checkpatch)
* Fix indenting in switch cases (checkpatch)
Changes since v4:
* Remove unneeded param changes with nv50_head_flush_clr/set
* Rebase
Changes since v5:
* Remove set but unused variable (outp) in nv50_crc_atomic_check() -
Kbuild bot
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200627194657.156514-10-lyude@redhat.com
2019-10-07 14:20:12 -04:00
|
|
|
struct nouveau_display *disp = nouveau_display(dev);
|
2009-12-11 19:24:15 +10:00
|
|
|
struct nouveau_crtc *nv_crtc;
|
2017-07-13 18:25:35 +02:00
|
|
|
int ret;
|
2009-12-11 19:24:15 +10:00
|
|
|
|
|
|
|
|
nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
|
|
|
|
|
if (!nv_crtc)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
nv_crtc->lut.depth = 0;
|
|
|
|
|
|
|
|
|
|
nv_crtc->index = crtc_num;
|
|
|
|
|
nv_crtc->last_dpms = NV_DPMS_CLEARED;
|
|
|
|
|
|
2015-12-04 17:13:38 +01:00
|
|
|
nv_crtc->save = nv_crtc_save;
|
|
|
|
|
nv_crtc->restore = nv_crtc_restore;
|
|
|
|
|
|
2017-08-05 22:25:05 -04:00
|
|
|
drm_crtc_init_with_planes(dev, &nv_crtc->base,
|
|
|
|
|
create_primary_plane(dev), NULL,
|
|
|
|
|
&nv04_crtc_funcs, NULL);
|
2009-12-11 19:24:15 +10:00
|
|
|
drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs);
|
|
|
|
|
drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
|
|
|
|
|
|
2016-05-24 17:26:48 +10:00
|
|
|
ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100,
|
2020-09-08 14:39:36 +02:00
|
|
|
NOUVEAU_GEM_DOMAIN_VRAM, 0, 0x0000, NULL, NULL,
|
2016-05-24 17:26:48 +10:00
|
|
|
&nv_crtc->cursor.nvbo);
|
2009-12-11 19:24:15 +10:00
|
|
|
if (!ret) {
|
2020-09-08 14:39:36 +02:00
|
|
|
ret = nouveau_bo_pin(nv_crtc->cursor.nvbo,
|
|
|
|
|
NOUVEAU_GEM_DOMAIN_VRAM, false);
|
2012-11-25 23:04:23 +01:00
|
|
|
if (!ret) {
|
2009-12-11 19:24:15 +10:00
|
|
|
ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
|
2012-11-25 23:04:23 +01:00
|
|
|
if (ret)
|
|
|
|
|
nouveau_bo_unpin(nv_crtc->cursor.nvbo);
|
|
|
|
|
}
|
2009-12-11 19:24:15 +10:00
|
|
|
if (ret)
|
|
|
|
|
nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
nv04_cursor_init(nv_crtc);
|
|
|
|
|
|
2020-06-08 14:47:37 +10:00
|
|
|
ret = nvif_notify_ctor(&disp->disp.object, "kmsVbl", nv04_crtc_vblank_handler,
|
drm/nouveau/kms/nvd9-: Add CRC support
This introduces support for CRC readback on gf119+, using the
documentation generously provided to us by Nvidia:
https://github.com/NVIDIA/open-gpu-doc/blob/master/Display-CRC/display-crc.txt
We expose all available CRC sources. SF, SOR, PIOR, and DAC are exposed
through a single set of "outp" sources: outp-active/auto for a CRC of
the scanout region, outp-complete for a CRC of both the scanout and
blanking/sync region combined, and outp-inactive for a CRC of only the
blanking/sync region. For each source, nouveau selects the appropriate
tap point based on the output path in use. We also expose an "rg"
source, which allows for capturing CRCs of the scanout raster before
it's encoded into a video signal in the output path. This tap point is
referred to as the raster generator.
Note that while there's some other neat features that can be used with
CRC capture on nvidia hardware, like capturing from two CRC sources
simultaneously, I couldn't see any usecase for them and did not
implement them.
Nvidia only allows for accessing CRCs through a shared DMA region that
we program through the core EVO/NvDisplay channel which is referred to
as the notifier context. The notifier context is limited to either 255
(for Fermi-Pascal) or 2047 (Volta+) entries to store CRCs in, and
unfortunately the hardware simply drops CRCs and reports an overflow
once all available entries in the notifier context are filled.
Since the DRM CRC API and igt-gpu-tools don't expect there to be a limit
on how many CRCs can be captured, we work around this in nouveau by
allocating two separate notifier contexts for each head instead of one.
We schedule a vblank worker ahead of time so that once we start getting
close to filling up all of the available entries in the notifier
context, we can swap the currently used notifier context out with
another pre-prepared notifier context in a manner similar to page
flipping.
Unfortunately, the hardware only allows us to this by flushing two
separate updates on the core channel: one to release the current
notifier context handle, and one to program the next notifier context's
handle. When the hardware processes the first update, the CRC for the
current frame is lost. However, the second update can be flushed
immediately without waiting for the first to complete so that CRC
generation resumes on the next frame. According to Nvidia's hardware
engineers, there isn't any cleaner way of flipping notifier contexts
that would avoid this.
Since using vblank workers to swap out the notifier context will ensure
we can usually flush both updates to hardware within the timespan of a
single frame, we can also ensure that there will only be exactly one
frame lost between the first and second update being executed by the
hardware. This gives us the guarantee that we're always correctly
matching each CRC entry with it's respective frame even after a context
flip. And since IGT will retrieve the CRC entry for a frame by waiting
until it receives a CRC for any subsequent frames, this doesn't cause an
issue with any tests and is much simpler than trying to change the
current DRM API to accommodate.
In order to facilitate testing of correct handling of this limitation,
we also expose a debugfs interface to manually control the threshold for
when we start trying to flip the notifier context. We will use this in
igt to trigger a context flip for testing purposes without needing to
wait for the notifier to completely fill up. This threshold is reset
to the default value set by nouveau after each capture, and is exposed
in a separate folder within each CRTC's debugfs directory labelled
"nv_crc".
Changes since v1:
* Forgot to finish saving crc.h before saving, whoops. This just adds
some corrections to the empty function declarations that we use if
CONFIG_DEBUG_FS isn't enabled.
Changes since v2:
* Don't check return code from debugfs_create_dir() or
debugfs_create_file() - Greg K-H
Changes since v3:
(no functional changes)
* Fix SPDX license identifiers (checkpatch)
* s/uint32_t/u32/ (checkpatch)
* Fix indenting in switch cases (checkpatch)
Changes since v4:
* Remove unneeded param changes with nv50_head_flush_clr/set
* Rebase
Changes since v5:
* Remove set but unused variable (outp) in nv50_crc_atomic_check() -
Kbuild bot
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200627194657.156514-10-lyude@redhat.com
2019-10-07 14:20:12 -04:00
|
|
|
false, NV04_DISP_NTFY_VBLANK,
|
|
|
|
|
&(struct nvif_notify_head_req_v0) {
|
|
|
|
|
.head = nv_crtc->index,
|
|
|
|
|
},
|
|
|
|
|
sizeof(struct nvif_notify_head_req_v0),
|
|
|
|
|
sizeof(struct nvif_notify_head_rep_v0),
|
|
|
|
|
&nv_crtc->vblank);
|
|
|
|
|
|
|
|
|
|
return ret;
|
2009-12-11 19:24:15 +10:00
|
|
|
}
|