2019-06-03 07:44:50 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#ifndef __MSM_GEM_H__
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#define __MSM_GEM_H__
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2017-03-07 10:02:52 -07:00
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#include <linux/kref.h>
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2019-08-11 10:06:32 +02:00
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#include <linux/dma-resv.h>
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
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#include "msm_drv.h"
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2015-03-03 15:04:25 -05:00
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/* Additional internal-use only BO flags: */
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#define MSM_BO_STOLEN 0x10000000 /* try to use stolen/splash memory */
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2020-04-23 17:09:14 -04:00
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#define MSM_BO_MAP_PRIV 0x20000000 /* use IOMMU_PRIV when mapping */
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2015-03-03 15:04:25 -05:00
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2016-09-28 19:58:32 -04:00
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struct msm_gem_address_space {
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const char *name;
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/* NOTE: mm managed at the page level, size is in # of pages
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* and position mm_node->start is in # of pages:
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*/
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struct drm_mm mm;
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2017-06-13 16:52:54 -06:00
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spinlock_t lock; /* Protects drm_mm node allocation/removal */
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2016-09-28 19:58:32 -04:00
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struct msm_mmu *mmu;
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2017-03-07 10:02:52 -07:00
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struct kref kref;
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2020-08-17 15:01:45 -07:00
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/* For address spaces associated with a specific process, this
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* will be non-NULL:
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*/
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struct pid *pid;
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2016-09-28 19:58:32 -04:00
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};
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struct msm_gem_vma {
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struct drm_mm_node node;
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uint64_t iova;
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2017-06-13 13:54:13 -04:00
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struct msm_gem_address_space *aspace;
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struct list_head list; /* node in msm_gem_object::vmas */
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2018-11-07 15:35:48 -07:00
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bool mapped;
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2018-11-07 15:35:51 -07:00
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int inuse;
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2016-09-28 19:58:32 -04:00
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};
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
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struct msm_gem_object {
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struct drm_gem_object base;
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uint32_t flags;
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2016-05-17 15:44:49 -04:00
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/**
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* Advice: are the backing pages purgeable?
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*/
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uint8_t madv;
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2016-05-27 11:16:28 -04:00
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/**
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* count of active vmap'ing
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*/
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uint8_t vmap_count;
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2013-07-19 12:59:32 -04:00
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/* And object is either:
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* inactive - on priv->inactive_list
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* active - on one one of the gpu's active_list.. well, at
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* least for now we don't have (I don't think) hw sync between
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* 2d and 3d one devices which have both, meaning we need to
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* block on submit if a bo is already on other ring
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*
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*/
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
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struct list_head mm_list;
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2013-07-19 12:59:32 -04:00
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/* Transiently in the process of submit ioctl, objects associated
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* with the submit are on submit->bo_list.. this only lasts for
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* the duration of the ioctl, so one bo can never be on multiple
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* submit lists.
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*/
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struct list_head submit_entry;
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
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struct page **pages;
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struct sg_table *sgt;
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void *vaddr;
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2017-06-13 13:54:13 -04:00
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struct list_head vmas; /* list of msm_gem_vma */
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2013-07-19 12:59:32 -04:00
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2019-03-20 10:09:08 -07:00
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struct llist_node freed;
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2013-11-16 12:56:06 -05:00
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/* For physically contiguous buffers. Used when we don't have
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2015-03-03 15:04:25 -05:00
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* an IOMMU. Also used for stolen/splashscreen buffer.
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2013-11-16 12:56:06 -05:00
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*/
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struct drm_mm_node *vram_node;
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2018-11-07 15:35:52 -07:00
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char name[32]; /* Identifier to print for the debugfs files */
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2020-09-22 20:25:26 +05:30
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2020-11-16 09:48:49 -08:00
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int active_count;
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
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};
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#define to_msm_bo(x) container_of(x, struct msm_gem_object, base)
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2020-10-23 09:51:05 -07:00
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int msm_gem_mmap_obj(struct drm_gem_object *obj,
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struct vm_area_struct *vma);
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int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
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uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
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int msm_gem_get_iova(struct drm_gem_object *obj,
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struct msm_gem_address_space *aspace, uint64_t *iova);
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int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj,
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struct msm_gem_address_space *aspace, uint64_t *iova,
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u64 range_start, u64 range_end);
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2020-10-23 09:51:06 -07:00
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int msm_gem_get_and_pin_iova_locked(struct drm_gem_object *obj,
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struct msm_gem_address_space *aspace, uint64_t *iova);
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2020-10-23 09:51:05 -07:00
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int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
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struct msm_gem_address_space *aspace, uint64_t *iova);
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uint64_t msm_gem_iova(struct drm_gem_object *obj,
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struct msm_gem_address_space *aspace);
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2020-10-23 09:51:06 -07:00
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void msm_gem_unpin_iova_locked(struct drm_gem_object *obj,
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struct msm_gem_address_space *aspace);
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2020-10-23 09:51:05 -07:00
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void msm_gem_unpin_iova(struct drm_gem_object *obj,
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struct msm_gem_address_space *aspace);
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struct page **msm_gem_get_pages(struct drm_gem_object *obj);
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void msm_gem_put_pages(struct drm_gem_object *obj);
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int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
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struct drm_mode_create_dumb *args);
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int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
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uint32_t handle, uint64_t *offset);
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2020-10-23 09:51:06 -07:00
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void *msm_gem_get_vaddr_locked(struct drm_gem_object *obj);
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2020-10-23 09:51:05 -07:00
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void *msm_gem_get_vaddr(struct drm_gem_object *obj);
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void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
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2020-10-23 09:51:06 -07:00
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void msm_gem_put_vaddr_locked(struct drm_gem_object *obj);
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2020-10-23 09:51:05 -07:00
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void msm_gem_put_vaddr(struct drm_gem_object *obj);
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int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
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int msm_gem_sync_object(struct drm_gem_object *obj,
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struct msm_fence_context *fctx, bool exclusive);
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void msm_gem_active_get(struct drm_gem_object *obj, struct msm_gpu *gpu);
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void msm_gem_active_put(struct drm_gem_object *obj);
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int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
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int msm_gem_cpu_fini(struct drm_gem_object *obj);
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void msm_gem_free_object(struct drm_gem_object *obj);
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int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
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uint32_t size, uint32_t flags, uint32_t *handle, char *name);
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struct drm_gem_object *msm_gem_new(struct drm_device *dev,
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uint32_t size, uint32_t flags);
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struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
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uint32_t size, uint32_t flags);
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void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
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uint32_t flags, struct msm_gem_address_space *aspace,
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struct drm_gem_object **bo, uint64_t *iova);
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void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size,
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uint32_t flags, struct msm_gem_address_space *aspace,
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struct drm_gem_object **bo, uint64_t *iova);
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void msm_gem_kernel_put(struct drm_gem_object *bo,
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struct msm_gem_address_space *aspace, bool locked);
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struct drm_gem_object *msm_gem_import(struct drm_device *dev,
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struct dma_buf *dmabuf, struct sg_table *sgt);
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__printf(2, 3)
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void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...);
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#ifdef CONFIG_DEBUG_FS
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void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
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void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
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#endif
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2020-10-23 09:51:03 -07:00
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static inline void
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msm_gem_lock(struct drm_gem_object *obj)
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{
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2020-10-23 09:51:10 -07:00
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dma_resv_lock(obj->resv, NULL);
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2020-10-23 09:51:03 -07:00
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}
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2020-10-23 09:51:07 -07:00
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static inline bool __must_check
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msm_gem_trylock(struct drm_gem_object *obj)
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{
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2020-10-23 09:51:10 -07:00
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return dma_resv_trylock(obj->resv);
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2020-10-23 09:51:07 -07:00
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}
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2020-10-23 09:51:03 -07:00
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static inline int
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msm_gem_lock_interruptible(struct drm_gem_object *obj)
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{
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2020-10-23 09:51:10 -07:00
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return dma_resv_lock_interruptible(obj->resv, NULL);
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2020-10-23 09:51:03 -07:00
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}
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static inline void
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msm_gem_unlock(struct drm_gem_object *obj)
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{
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2020-10-23 09:51:10 -07:00
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dma_resv_unlock(obj->resv);
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2020-10-23 09:51:03 -07:00
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}
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static inline bool
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msm_gem_is_locked(struct drm_gem_object *obj)
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{
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2020-10-23 09:51:10 -07:00
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return dma_resv_is_locked(obj->resv);
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2020-10-23 09:51:03 -07:00
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}
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2013-07-19 12:59:32 -04:00
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static inline bool is_active(struct msm_gem_object *msm_obj)
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{
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2020-11-16 09:48:49 -08:00
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WARN_ON(!msm_gem_is_locked(&msm_obj->base));
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return msm_obj->active_count;
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2013-07-19 12:59:32 -04:00
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}
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2016-05-17 16:19:32 -04:00
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static inline bool is_purgeable(struct msm_gem_object *msm_obj)
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{
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return (msm_obj->madv == MSM_MADV_DONTNEED) && msm_obj->sgt &&
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!msm_obj->base.dma_buf && !msm_obj->base.import_attach;
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}
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2016-05-27 11:16:28 -04:00
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static inline bool is_vunmapable(struct msm_gem_object *msm_obj)
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{
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2020-10-23 09:51:07 -07:00
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WARN_ON(!msm_gem_is_locked(&msm_obj->base));
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2016-05-27 11:16:28 -04:00
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return (msm_obj->vmap_count == 0) && msm_obj->vaddr;
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}
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2020-10-23 09:51:07 -07:00
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void msm_gem_purge(struct drm_gem_object *obj);
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void msm_gem_vunmap(struct drm_gem_object *obj);
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2017-06-13 16:52:54 -06:00
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2013-07-19 12:59:32 -04:00
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/* Created per submit-ioctl, to track bo's and cmdstream bufs, etc,
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* associated with the cmdstream submission for synchronization (and
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* make it easier to unwind when things go wrong, etc). This only
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* lasts for the duration of the submit-ioctl.
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*/
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struct msm_gem_submit {
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2020-10-23 09:51:17 -07:00
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struct kref ref;
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2013-07-19 12:59:32 -04:00
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struct drm_device *dev;
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struct msm_gpu *gpu;
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2019-05-07 12:02:07 -06:00
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struct msm_gem_address_space *aspace;
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2017-10-20 11:06:57 -06:00
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struct list_head node; /* node in ring submit list */
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2013-07-19 12:59:32 -04:00
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struct list_head bo_list;
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struct ww_acquire_ctx ticket;
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2017-10-20 11:06:57 -06:00
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uint32_t seqno; /* Sequence number of the submit on the ring */
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2016-10-25 13:00:45 +01:00
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struct dma_fence *fence;
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2017-10-20 11:06:55 -06:00
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struct msm_gpu_submitqueue *queue;
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2016-05-03 10:10:15 -04:00
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struct pid *pid; /* submitting process */
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2016-03-14 13:56:37 -04:00
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bool valid; /* true if no cmdstream patching needed */
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2017-12-13 15:12:57 -05:00
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bool in_rb; /* "sudo" mode, copy cmds into RB */
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2017-10-20 11:06:57 -06:00
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struct msm_ringbuffer *ring;
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2020-08-17 15:01:36 -07:00
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struct msm_file_private *ctx;
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2013-07-19 12:59:32 -04:00
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unsigned int nr_cmds;
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unsigned int nr_bos;
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2018-11-02 09:25:21 -06:00
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u32 ident; /* A "identifier" for the submit for logging */
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2013-07-19 12:59:32 -04:00
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struct {
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uint32_t type;
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uint32_t size; /* in dwords */
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2016-11-11 12:06:46 -05:00
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uint64_t iova;
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2020-10-23 09:51:08 -07:00
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uint32_t offset;/* in dwords */
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2014-05-30 14:47:38 -04:00
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uint32_t idx; /* cmdstream buffer idx in bos[] */
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2020-10-23 09:51:08 -07:00
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uint32_t nr_relocs;
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struct drm_msm_gem_submit_reloc *relocs;
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2016-06-01 14:17:40 -04:00
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} *cmd; /* array of size nr_cmds */
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2013-07-19 12:59:32 -04:00
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struct {
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uint32_t flags;
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2019-03-20 10:09:10 -07:00
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union {
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struct msm_gem_object *obj;
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uint32_t handle;
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};
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2016-11-11 12:06:46 -05:00
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uint64_t iova;
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2020-03-05 04:54:51 -06:00
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} bos[];
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2013-07-19 12:59:32 -04:00
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};
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2020-10-23 09:51:17 -07:00
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void __msm_gem_submit_destroy(struct kref *kref);
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static inline void msm_gem_submit_get(struct msm_gem_submit *submit)
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{
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kref_get(&submit->ref);
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}
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static inline void msm_gem_submit_put(struct msm_gem_submit *submit)
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{
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kref_put(&submit->ref, __msm_gem_submit_destroy);
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}
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2020-02-18 13:20:12 -08:00
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/* helper to determine of a buffer in submit should be dumped, used for both
|
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* devcoredump and debugfs cmdstream dumping:
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*/
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static inline bool
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should_dump(struct msm_gem_submit *submit, int idx)
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|
|
|
{
|
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|
|
extern bool rd_full;
|
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|
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return rd_full || (submit->bos[idx].flags & MSM_SUBMIT_BO_DUMP);
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}
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
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#endif /* __MSM_GEM_H__ */
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