2018-10-11 10:17:08 +03:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018 Intel Corporation */
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#ifndef _IGC_H_
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#define _IGC_H_
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#include <linux/kobject.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/vmalloc.h>
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#include <linux/ethtool.h>
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#include <linux/sctp.h>
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2019-12-02 15:19:49 -08:00
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#include <linux/ptp_clock_kernel.h>
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#include <linux/timecounter.h>
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#include <linux/net_tstamp.h>
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2018-10-11 10:17:08 +03:00
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2018-10-11 10:17:10 +03:00
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#include "igc_hw.h"
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2020-04-24 13:16:09 -07:00
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void igc_ethtool_set_ops(struct net_device *);
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2019-01-30 19:13:14 +02:00
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2020-02-28 02:25:15 +02:00
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/* Transmit and receive queues */
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#define IGC_MAX_RX_QUEUES 4
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#define IGC_MAX_TX_QUEUES 4
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#define MAX_Q_VECTORS 8
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#define MAX_STD_JUMBO_FRAME_SIZE 9216
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2020-04-07 14:07:09 -07:00
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#define MAX_ETYPE_FILTER 8
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2020-02-28 02:25:15 +02:00
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#define IGC_RETA_SIZE 128
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igc: enable auxiliary PHC functions for the i225
The i225 device offers a number of special PTP Hardware Clock features on
the Software Defined Pins (SDPs) - much like i210, which is used as
inspiration for this patch. It enables two possible functions, namely
time stamping external events and periodic output signals.
The assignment of PHC functions to the four SDP can be freely chosen by
the user.
For the external events time stamping, when the SDP (configured as input
by user) level changes, an interrupt is generated and the kernel
Precision Time Protocol (PTP) is informed.
For the periodic output signals, the i225 is configured to generate them
(so the SDP level will change periodically) and the driver also has to
keep updating the time of the next level change. However, this work is
not necessary for some frequencies as the i225 takes care of them
(namely, anything with a half-cycle of 500ms, 250ms, 125ms or < 70ms).
While i225 allows up to four timers to be used to source the time used
on the external events or output signals, this patch uses only one of
those timers. Main reason is to keep it simple, as it's not clear how
these extra timers would be exposed to users. Note that currently a NIC
can expose a single PTP device.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Tested-by: Dvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2021-02-18 17:31:04 -08:00
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/* SDP support */
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#define IGC_N_EXTTS 2
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#define IGC_N_PEROUT 2
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#define IGC_N_SDP 4
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2021-06-28 21:43:28 -07:00
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#define MAX_FLEX_FILTER 32
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2020-04-10 17:28:33 -07:00
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enum igc_mac_filter_type {
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IGC_MAC_FILTER_TYPE_DST = 0,
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IGC_MAC_FILTER_TYPE_SRC
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};
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2020-02-28 02:25:15 +02:00
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struct igc_tx_queue_stats {
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u64 packets;
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u64 bytes;
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u64 restart_queue;
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u64 restart_queue2;
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};
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struct igc_rx_queue_stats {
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u64 packets;
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u64 bytes;
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u64 drops;
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u64 csum_err;
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u64 alloc_failed;
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};
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struct igc_rx_packet_stats {
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u64 ipv4_packets; /* IPv4 headers processed */
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u64 ipv4e_packets; /* IPv4E headers with extensions processed */
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u64 ipv6_packets; /* IPv6 headers processed */
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u64 ipv6e_packets; /* IPv6E headers with extensions processed */
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u64 tcp_packets; /* TCP headers processed */
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u64 udp_packets; /* UDP headers processed */
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u64 sctp_packets; /* SCTP headers processed */
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u64 nfs_packets; /* NFS headers processe */
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u64 other_packets;
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};
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struct igc_ring_container {
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struct igc_ring *ring; /* pointer to linked list of rings */
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_packets; /* total packets processed this int */
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u16 work_limit; /* total work allowed per interrupt */
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u8 count; /* total number of rings in vector */
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u8 itr; /* current ITR setting for ring */
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};
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struct igc_ring {
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struct igc_q_vector *q_vector; /* backlink to q_vector */
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struct net_device *netdev; /* back pointer to net_device */
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struct device *dev; /* device for dma mapping */
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union { /* array of buffer info structs */
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struct igc_tx_buffer *tx_buffer_info;
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struct igc_rx_buffer *rx_buffer_info;
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};
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void *desc; /* descriptor ring memory */
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unsigned long flags; /* ring specific flags */
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void __iomem *tail; /* pointer to ring tail register */
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dma_addr_t dma; /* phys address of the ring */
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unsigned int size; /* length of desc. ring in bytes */
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u16 count; /* number of desc. in the ring */
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u8 queue_index; /* logical index of the ring*/
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u8 reg_idx; /* physical index of the ring */
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bool launchtime_enable; /* true if LaunchTime is enabled */
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igc: Enhance Qbv scheduling by using first flag bit
The I225 hardware has a limitation that packets can only be scheduled
in the [0, cycle-time] interval. So, scheduling a packet to the start
of the next cycle doesn't usually work.
To overcome this, we use the Transmit Descriptor first flag to indicates
that a packet should be the first packet (from a queue) in a cycle
according to the section 7.5.2.9.3.4 The First Packet on Each QBV Cycle
in Intel Discrete I225/6 User Manual.
But this only works if there was any packet from that queue during the
current cycle, to avoid this issue, we issue an empty packet if that's
not the case. Also require one more descriptor to be available, to take
into account the empty packet that might be issued.
Test Setup:
Talker: Use l2_tai to generate the launchtime into packet load.
Listener: Use timedump.c to compute the delta between packet arrival
and LaunchTime packet payload.
Test Result:
Before:
1666000610127300000,1666000610127300096,96,621273
1666000610127400000,1666000610127400192,192,621274
1666000610127500000,1666000610127500032,32,621275
1666000610127600000,1666000610127600128,128,621276
1666000610127700000,1666000610127700224,224,621277
1666000610127800000,1666000610127800064,64,621278
1666000610127900000,1666000610127900160,160,621279
1666000610128000000,1666000610128000000,0,621280
1666000610128100000,1666000610128100096,96,621281
1666000610128200000,1666000610128200192,192,621282
1666000610128300000,1666000610128300032,32,621283
1666000610128400000,1666000610128301056,-98944,621284
1666000610128500000,1666000610128302080,-197920,621285
1666000610128600000,1666000610128302848,-297152,621286
1666000610128700000,1666000610128303872,-396128,621287
1666000610128800000,1666000610128304896,-495104,621288
1666000610128900000,1666000610128305664,-594336,621289
1666000610129000000,1666000610128306688,-693312,621290
1666000610129100000,1666000610128307712,-792288,621291
1666000610129200000,1666000610128308480,-891520,621292
1666000610129300000,1666000610128309504,-990496,621293
1666000610129400000,1666000610128310528,-1089472,621294
1666000610129500000,1666000610128311296,-1188704,621295
1666000610129600000,1666000610128312320,-1287680,621296
1666000610129700000,1666000610128313344,-1386656,621297
1666000610129800000,1666000610128314112,-1485888,621298
1666000610129900000,1666000610128315136,-1584864,621299
1666000610130000000,1666000610128316160,-1683840,621300
1666000610130100000,1666000610128316928,-1783072,621301
1666000610130200000,1666000610128317952,-1882048,621302
1666000610130300000,1666000610128318976,-1981024,621303
1666000610130400000,1666000610128319744,-2080256,621304
1666000610130500000,1666000610128320768,-2179232,621305
1666000610130600000,1666000610128321792,-2278208,621306
1666000610130700000,1666000610128322816,-2377184,621307
1666000610130800000,1666000610128323584,-2476416,621308
1666000610130900000,1666000610128324608,-2575392,621309
1666000610131000000,1666000610128325632,-2674368,621310
1666000610131100000,1666000610128326400,-2773600,621311
1666000610131200000,1666000610128327424,-2872576,621312
1666000610131300000,1666000610128328448,-2971552,621313
1666000610131400000,1666000610128329216,-3070784,621314
1666000610131500000,1666000610131500032,32,621315
1666000610131600000,1666000610131600128,128,621316
1666000610131700000,1666000610131700224,224,621317
After:
1666073510646200000,1666073510646200064,64,2676462
1666073510646300000,1666073510646300160,160,2676463
1666073510646400000,1666073510646400256,256,2676464
1666073510646500000,1666073510646500096,96,2676465
1666073510646600000,1666073510646600192,192,2676466
1666073510646700000,1666073510646700032,32,2676467
1666073510646800000,1666073510646800128,128,2676468
1666073510646900000,1666073510646900224,224,2676469
1666073510647000000,1666073510647000064,64,2676470
1666073510647100000,1666073510647100160,160,2676471
1666073510647200000,1666073510647200256,256,2676472
1666073510647300000,1666073510647300096,96,2676473
1666073510647400000,1666073510647400192,192,2676474
1666073510647500000,1666073510647500032,32,2676475
1666073510647600000,1666073510647600128,128,2676476
1666073510647700000,1666073510647700224,224,2676477
1666073510647800000,1666073510647800064,64,2676478
1666073510647900000,1666073510647900160,160,2676479
1666073510648000000,1666073510648000000,0,2676480
1666073510648100000,1666073510648100096,96,2676481
1666073510648200000,1666073510648200192,192,2676482
1666073510648300000,1666073510648300032,32,2676483
1666073510648400000,1666073510648400128,128,2676484
1666073510648500000,1666073510648500224,224,2676485
1666073510648600000,1666073510648600064,64,2676486
1666073510648700000,1666073510648700160,160,2676487
1666073510648800000,1666073510648800000,0,2676488
1666073510648900000,1666073510648900096,96,2676489
1666073510649000000,1666073510649000192,192,2676490
1666073510649100000,1666073510649100032,32,2676491
1666073510649200000,1666073510649200128,128,2676492
1666073510649300000,1666073510649300224,224,2676493
1666073510649400000,1666073510649400064,64,2676494
1666073510649500000,1666073510649500160,160,2676495
1666073510649600000,1666073510649600000,0,2676496
1666073510649700000,1666073510649700096,96,2676497
1666073510649800000,1666073510649800192,192,2676498
1666073510649900000,1666073510649900032,32,2676499
1666073510650000000,1666073510650000128,128,2676500
Fixes: 82faa9b79950 ("igc: Add support for ETF offloading")
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Co-developed-by: Aravindhan Gunasekaran <aravindhan.gunasekaran@intel.com>
Signed-off-by: Aravindhan Gunasekaran <aravindhan.gunasekaran@intel.com>
Co-developed-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>
Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>
Signed-off-by: Malli C <mallikarjuna.chilakala@intel.com>
Tested-by: Naama Meir <naamax.meir@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2022-12-09 12:15:17 +08:00
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ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
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ktime_t last_ff_cycle; /* Last cycle with an active first flag */
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2020-02-28 02:25:15 +02:00
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u32 start_time;
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u32 end_time;
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2021-08-09 20:23:40 +05:30
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/* CBS parameters */
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bool cbs_enable; /* indicates if CBS is enabled */
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s32 idleslope; /* idleSlope in kbps */
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s32 sendslope; /* sendSlope in kbps */
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s32 hicredit; /* hiCredit in bytes */
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s32 locredit; /* loCredit in bytes */
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2020-02-28 02:25:15 +02:00
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/* everything past this point are written often */
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u16 next_to_clean;
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u16 next_to_use;
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u16 next_to_alloc;
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union {
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/* TX */
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struct {
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struct igc_tx_queue_stats tx_stats;
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struct u64_stats_sync tx_syncp;
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struct u64_stats_sync tx_syncp2;
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};
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/* RX */
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struct {
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struct igc_rx_queue_stats rx_stats;
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struct igc_rx_packet_stats pkt_stats;
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struct u64_stats_sync rx_syncp;
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struct sk_buff *skb;
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};
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};
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2021-03-09 23:13:21 -08:00
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struct xdp_rxq_info xdp_rxq;
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2021-04-22 23:25:54 -07:00
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struct xsk_buff_pool *xsk_pool;
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2020-02-28 02:25:15 +02:00
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} ____cacheline_internodealigned_in_smp;
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/* Board specific private data structure */
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struct igc_adapter {
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struct net_device *netdev;
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2020-05-27 13:51:32 -07:00
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struct ethtool_eee eee;
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u16 eee_advert;
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2020-02-28 02:25:15 +02:00
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unsigned long state;
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unsigned int flags;
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unsigned int num_q_vectors;
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struct msix_entry *msix_entries;
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/* TX */
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u16 tx_work_limit;
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u32 tx_timeout_count;
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int num_tx_queues;
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struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
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/* RX */
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int num_rx_queues;
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struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
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struct timer_list watchdog_timer;
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struct timer_list dma_err_timer;
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struct timer_list phy_info_timer;
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u32 wol;
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u32 en_mng_pt;
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u16 link_speed;
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u16 link_duplex;
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u8 port_num;
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u8 __iomem *io_addr;
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/* Interrupt Throttle Rate */
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u32 rx_itr_setting;
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u32 tx_itr_setting;
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struct work_struct reset_task;
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struct work_struct watchdog_task;
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struct work_struct dma_err_task;
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bool fc_autoneg;
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u8 tx_timeout_factor;
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int msg_enable;
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u32 max_frame_size;
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u32 min_frame_size;
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ktime_t base_time;
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ktime_t cycle_time;
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2022-12-09 12:15:20 +08:00
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bool qbv_enable;
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2020-02-28 02:25:15 +02:00
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/* OS defined structs */
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struct pci_dev *pdev;
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/* lock for statistics */
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spinlock_t stats64_lock;
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struct rtnl_link_stats64 stats64;
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/* structs defined in igc_hw.h */
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struct igc_hw hw;
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struct igc_hw_stats stats;
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struct igc_q_vector *q_vector[MAX_Q_VECTORS];
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u32 eims_enable_mask;
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u32 eims_other;
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u16 tx_ring_count;
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u16 rx_ring_count;
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u32 tx_hwtstamp_timeouts;
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u32 tx_hwtstamp_skipped;
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u32 rx_hwtstamp_cleared;
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u32 rss_queues;
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u32 rss_indir_tbl_init;
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2020-04-24 13:16:10 -07:00
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/* Any access to elements in nfc_rule_list is protected by the
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* nfc_rule_lock.
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*/
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2020-04-24 13:16:22 -07:00
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struct mutex nfc_rule_lock;
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igc: Fix NFC rules restoration
When network interface is brought up, the driver re-enables the NFC
rules previously configured. However, this is done in reverse order
the rules were added and hardware filters are configured differently.
For example, consider the following rules:
$ ethtool -N eth0 flow-type ether dst 00:00:00:00:00:AA queue 0
$ ethtool -N eth0 flow-type ether dst 00:00:00:00:00:BB queue 1
$ ethtool -N eth0 flow-type ether dst 00:00:00:00:00:CC queue 2
$ ethtool -N eth0 flow-type ether dst 00:00:00:00:00:DD queue 3
RAL/RAH registers are configure so filter index 1 has address ending
with AA, filter index 2 has address ending in BB, and so on.
If we bring the interface down and up again, RAL/RAH registers are
configured so filter index 1 has address ending in DD, filter index 2
has CC, and so on. IOW, in reverse order we had before bringing the
interface down.
This issue can be fixed by traversing adapter->nfc_rule_list in
backwards when restoring the rules. Since hlist doesn't support
backwards traversal, this patch replaces it by list_head and fixes
igc_restore_nfc_rules() accordingly.
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2020-04-24 13:16:17 -07:00
|
|
|
struct list_head nfc_rule_list;
|
2020-04-24 13:16:10 -07:00
|
|
|
unsigned int nfc_rule_count;
|
2020-02-28 02:25:15 +02:00
|
|
|
|
|
|
|
u8 rss_indir_tbl[IGC_RETA_SIZE];
|
|
|
|
|
|
|
|
unsigned long link_check_timeout;
|
|
|
|
struct igc_info ei;
|
|
|
|
|
2020-05-05 17:06:38 +03:00
|
|
|
u32 test_icr;
|
|
|
|
|
2020-02-28 02:25:15 +02:00
|
|
|
struct ptp_clock *ptp_clock;
|
|
|
|
struct ptp_clock_info ptp_caps;
|
|
|
|
struct work_struct ptp_tx_work;
|
|
|
|
struct sk_buff *ptp_tx_skb;
|
|
|
|
struct hwtstamp_config tstamp_config;
|
|
|
|
unsigned long ptp_tx_start;
|
|
|
|
unsigned int ptp_flags;
|
|
|
|
/* System time value lock */
|
|
|
|
spinlock_t tmreg_lock;
|
|
|
|
struct cyclecounter cc;
|
|
|
|
struct timecounter tc;
|
2020-08-20 16:02:17 -07:00
|
|
|
struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
|
|
|
|
ktime_t ptp_reset_start; /* Reset time in clock mono */
|
igc: Add support for PTP getcrosststamp()
i225 supports PCIe Precision Time Measurement (PTM), allowing us to
support the PTP_SYS_OFFSET_PRECISE ioctl() in the driver via the
getcrosststamp() function.
The easiest way to expose the PTM registers would be to configure the PTM
dialogs to run periodically, but the PTP_SYS_OFFSET_PRECISE ioctl()
semantics are more aligned to using a kind of "one-shot" way of retrieving
the PTM timestamps. But this causes a bit more code to be written: the
trigger registers for the PTM dialogs are not cleared automatically.
i225 can be configured to send "fake" packets with the PTM
information, adding support for handling these types of packets is
left for the future.
PTM improves the accuracy of time synchronization, for example, using
phc2sys, while a simple application is sending packets as fast as
possible. First, without .getcrosststamp():
phc2sys[191.382]: enp4s0 sys offset -959 s2 freq -454 delay 4492
phc2sys[191.482]: enp4s0 sys offset 798 s2 freq +1015 delay 4069
phc2sys[191.583]: enp4s0 sys offset 962 s2 freq +1418 delay 3849
phc2sys[191.683]: enp4s0 sys offset 924 s2 freq +1669 delay 3753
phc2sys[191.783]: enp4s0 sys offset 664 s2 freq +1686 delay 3349
phc2sys[191.883]: enp4s0 sys offset 218 s2 freq +1439 delay 2585
phc2sys[191.983]: enp4s0 sys offset 761 s2 freq +2048 delay 3750
phc2sys[192.083]: enp4s0 sys offset 756 s2 freq +2271 delay 4061
phc2sys[192.183]: enp4s0 sys offset 809 s2 freq +2551 delay 4384
phc2sys[192.283]: enp4s0 sys offset -108 s2 freq +1877 delay 2480
phc2sys[192.383]: enp4s0 sys offset -1145 s2 freq +807 delay 4438
phc2sys[192.484]: enp4s0 sys offset 571 s2 freq +2180 delay 3849
phc2sys[192.584]: enp4s0 sys offset 241 s2 freq +2021 delay 3389
phc2sys[192.684]: enp4s0 sys offset 405 s2 freq +2257 delay 3829
phc2sys[192.784]: enp4s0 sys offset 17 s2 freq +1991 delay 3273
phc2sys[192.884]: enp4s0 sys offset 152 s2 freq +2131 delay 3948
phc2sys[192.984]: enp4s0 sys offset -187 s2 freq +1837 delay 3162
phc2sys[193.084]: enp4s0 sys offset -1595 s2 freq +373 delay 4557
phc2sys[193.184]: enp4s0 sys offset 107 s2 freq +1597 delay 3740
phc2sys[193.284]: enp4s0 sys offset 199 s2 freq +1721 delay 4010
phc2sys[193.385]: enp4s0 sys offset -169 s2 freq +1413 delay 3701
phc2sys[193.485]: enp4s0 sys offset -47 s2 freq +1484 delay 3581
phc2sys[193.585]: enp4s0 sys offset -65 s2 freq +1452 delay 3778
phc2sys[193.685]: enp4s0 sys offset 95 s2 freq +1592 delay 3888
phc2sys[193.785]: enp4s0 sys offset 206 s2 freq +1732 delay 4445
phc2sys[193.885]: enp4s0 sys offset -652 s2 freq +936 delay 2521
phc2sys[193.985]: enp4s0 sys offset -203 s2 freq +1189 delay 3391
phc2sys[194.085]: enp4s0 sys offset -376 s2 freq +955 delay 2951
phc2sys[194.185]: enp4s0 sys offset -134 s2 freq +1084 delay 3330
phc2sys[194.285]: enp4s0 sys offset -22 s2 freq +1156 delay 3479
phc2sys[194.386]: enp4s0 sys offset 32 s2 freq +1204 delay 3602
phc2sys[194.486]: enp4s0 sys offset 122 s2 freq +1303 delay 3731
Statistics for this run (total of 2179 lines), in nanoseconds:
average: -1.12
stdev: 634.80
max: 1551
min: -2215
With .getcrosststamp() via PCIe PTM:
phc2sys[367.859]: enp4s0 sys offset 6 s2 freq +1727 delay 0
phc2sys[367.959]: enp4s0 sys offset -2 s2 freq +1721 delay 0
phc2sys[368.059]: enp4s0 sys offset 5 s2 freq +1727 delay 0
phc2sys[368.160]: enp4s0 sys offset -1 s2 freq +1723 delay 0
phc2sys[368.260]: enp4s0 sys offset -4 s2 freq +1719 delay 0
phc2sys[368.360]: enp4s0 sys offset -5 s2 freq +1717 delay 0
phc2sys[368.460]: enp4s0 sys offset 1 s2 freq +1722 delay 0
phc2sys[368.560]: enp4s0 sys offset -3 s2 freq +1718 delay 0
phc2sys[368.660]: enp4s0 sys offset 5 s2 freq +1725 delay 0
phc2sys[368.760]: enp4s0 sys offset -1 s2 freq +1721 delay 0
phc2sys[368.860]: enp4s0 sys offset 0 s2 freq +1721 delay 0
phc2sys[368.960]: enp4s0 sys offset 0 s2 freq +1721 delay 0
phc2sys[369.061]: enp4s0 sys offset 4 s2 freq +1725 delay 0
phc2sys[369.161]: enp4s0 sys offset 1 s2 freq +1724 delay 0
phc2sys[369.261]: enp4s0 sys offset 4 s2 freq +1727 delay 0
phc2sys[369.361]: enp4s0 sys offset 8 s2 freq +1732 delay 0
phc2sys[369.461]: enp4s0 sys offset 7 s2 freq +1733 delay 0
phc2sys[369.561]: enp4s0 sys offset 4 s2 freq +1733 delay 0
phc2sys[369.661]: enp4s0 sys offset 1 s2 freq +1731 delay 0
phc2sys[369.761]: enp4s0 sys offset 1 s2 freq +1731 delay 0
phc2sys[369.861]: enp4s0 sys offset -5 s2 freq +1725 delay 0
phc2sys[369.961]: enp4s0 sys offset -4 s2 freq +1725 delay 0
phc2sys[370.062]: enp4s0 sys offset 2 s2 freq +1730 delay 0
phc2sys[370.162]: enp4s0 sys offset -7 s2 freq +1721 delay 0
phc2sys[370.262]: enp4s0 sys offset -3 s2 freq +1723 delay 0
phc2sys[370.362]: enp4s0 sys offset 1 s2 freq +1726 delay 0
phc2sys[370.462]: enp4s0 sys offset -3 s2 freq +1723 delay 0
phc2sys[370.562]: enp4s0 sys offset -1 s2 freq +1724 delay 0
phc2sys[370.662]: enp4s0 sys offset -4 s2 freq +1720 delay 0
phc2sys[370.762]: enp4s0 sys offset -7 s2 freq +1716 delay 0
phc2sys[370.862]: enp4s0 sys offset -2 s2 freq +1719 delay 0
Statistics for this run (total of 2179 lines), in nanoseconds:
average: 0.14
stdev: 5.03
max: 48
min: -27
For reference, the statistics for runs without PCIe congestion show
that the improvements from enabling PTM are less dramatic. For two
runs of 16466 entries:
without PTM: avg -0.04 stdev 10.57 max 39 min -42
with PTM: avg 0.01 stdev 4.20 max 19 min -16
One possible explanation is that when PTM is not enabled, and there's a lot
of traffic in the PCIe fabric, some register reads will take more time
than the others because of congestion on the PCIe fabric.
When PTM is enabled, even if the PTM dialogs take more time to
complete under heavy traffic, the time measurements do not depend on
the time to read the registers.
This was implemented following the i225 EAS version 0.993.
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Tested-by: Dvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2021-07-26 20:36:57 -07:00
|
|
|
struct system_time_snapshot snapshot;
|
2020-12-10 08:42:09 +02:00
|
|
|
|
2020-12-20 11:16:49 +02:00
|
|
|
char fw_version[32];
|
2021-03-09 23:13:20 -08:00
|
|
|
|
|
|
|
struct bpf_prog *xdp_prog;
|
2021-02-18 17:31:03 -08:00
|
|
|
|
|
|
|
bool pps_sys_wrap_on;
|
igc: enable auxiliary PHC functions for the i225
The i225 device offers a number of special PTP Hardware Clock features on
the Software Defined Pins (SDPs) - much like i210, which is used as
inspiration for this patch. It enables two possible functions, namely
time stamping external events and periodic output signals.
The assignment of PHC functions to the four SDP can be freely chosen by
the user.
For the external events time stamping, when the SDP (configured as input
by user) level changes, an interrupt is generated and the kernel
Precision Time Protocol (PTP) is informed.
For the periodic output signals, the i225 is configured to generate them
(so the SDP level will change periodically) and the driver also has to
keep updating the time of the next level change. However, this work is
not necessary for some frequencies as the i225 takes care of them
(namely, anything with a half-cycle of 500ms, 250ms, 125ms or < 70ms).
While i225 allows up to four timers to be used to source the time used
on the external events or output signals, this patch uses only one of
those timers. Main reason is to keep it simple, as it's not clear how
these extra timers would be exposed to users. Note that currently a NIC
can expose a single PTP device.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Tested-by: Dvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2021-02-18 17:31:04 -08:00
|
|
|
|
|
|
|
struct ptp_pin_desc sdp_config[IGC_N_SDP];
|
|
|
|
struct {
|
|
|
|
struct timespec64 start;
|
|
|
|
struct timespec64 period;
|
|
|
|
} perout[IGC_N_PEROUT];
|
2020-02-28 02:25:15 +02:00
|
|
|
};
|
2019-01-30 19:13:14 +02:00
|
|
|
|
|
|
|
void igc_up(struct igc_adapter *adapter);
|
|
|
|
void igc_down(struct igc_adapter *adapter);
|
2020-05-05 17:06:38 +03:00
|
|
|
int igc_open(struct net_device *netdev);
|
|
|
|
int igc_close(struct net_device *netdev);
|
2019-01-30 19:13:14 +02:00
|
|
|
int igc_setup_tx_resources(struct igc_ring *ring);
|
|
|
|
int igc_setup_rx_resources(struct igc_ring *ring);
|
|
|
|
void igc_free_tx_resources(struct igc_ring *ring);
|
|
|
|
void igc_free_rx_resources(struct igc_ring *ring);
|
|
|
|
unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
|
|
|
|
void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
|
|
|
|
const u32 max_rss_queues);
|
|
|
|
int igc_reinit_queues(struct igc_adapter *adapter);
|
2019-02-06 09:48:37 +02:00
|
|
|
void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
|
2019-01-30 19:13:14 +02:00
|
|
|
bool igc_has_link(struct igc_adapter *adapter);
|
|
|
|
void igc_reset(struct igc_adapter *adapter);
|
2019-02-18 10:37:31 +02:00
|
|
|
void igc_update_stats(struct igc_adapter *adapter);
|
2021-04-22 23:25:54 -07:00
|
|
|
void igc_disable_rx_ring(struct igc_ring *ring);
|
|
|
|
void igc_enable_rx_ring(struct igc_ring *ring);
|
2021-04-22 23:25:55 -07:00
|
|
|
void igc_disable_tx_ring(struct igc_ring *ring);
|
|
|
|
void igc_enable_tx_ring(struct igc_ring *ring);
|
2021-04-22 23:25:54 -07:00
|
|
|
int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
|
2019-01-30 19:13:14 +02:00
|
|
|
|
2020-01-14 09:55:54 +02:00
|
|
|
/* igc_dump declarations */
|
|
|
|
void igc_rings_dump(struct igc_adapter *adapter);
|
|
|
|
void igc_regs_dump(struct igc_adapter *adapter);
|
|
|
|
|
2018-10-11 10:17:08 +03:00
|
|
|
extern char igc_driver_name[];
|
|
|
|
|
2019-01-30 19:13:14 +02:00
|
|
|
#define IGC_REGS_LEN 740
|
|
|
|
|
2019-12-02 15:19:49 -08:00
|
|
|
/* flags controlling PTP/1588 function */
|
|
|
|
#define IGC_PTP_ENABLED BIT(0)
|
|
|
|
|
2020-02-03 10:11:50 +02:00
|
|
|
/* Flags definitions */
|
2018-10-11 10:17:16 +03:00
|
|
|
#define IGC_FLAG_HAS_MSI BIT(0)
|
2019-01-30 19:13:14 +02:00
|
|
|
#define IGC_FLAG_QUEUE_PAIRS BIT(3)
|
|
|
|
#define IGC_FLAG_DMAC BIT(4)
|
2019-12-02 15:19:49 -08:00
|
|
|
#define IGC_FLAG_PTP BIT(8)
|
2020-02-03 09:55:20 +02:00
|
|
|
#define IGC_FLAG_WOL_SUPPORTED BIT(8)
|
2018-10-11 10:17:22 +03:00
|
|
|
#define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
|
2018-10-11 10:17:36 +03:00
|
|
|
#define IGC_FLAG_MEDIA_RESET BIT(10)
|
|
|
|
#define IGC_FLAG_MAS_ENABLE BIT(12)
|
2018-10-11 10:17:16 +03:00
|
|
|
#define IGC_FLAG_HAS_MSIX BIT(13)
|
2020-05-27 13:51:32 -07:00
|
|
|
#define IGC_FLAG_EEE BIT(14)
|
2018-10-11 10:17:22 +03:00
|
|
|
#define IGC_FLAG_VLAN_PROMISC BIT(15)
|
2019-01-30 19:13:14 +02:00
|
|
|
#define IGC_FLAG_RX_LEGACY BIT(16)
|
2020-02-14 15:52:02 -08:00
|
|
|
#define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
|
2021-08-09 20:23:40 +05:30
|
|
|
#define IGC_FLAG_TSN_QAV_ENABLED BIT(18)
|
2018-10-11 10:17:16 +03:00
|
|
|
|
2021-08-09 20:23:40 +05:30
|
|
|
#define IGC_FLAG_TSN_ANY_ENABLED \
|
|
|
|
(IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED)
|
2021-08-09 20:23:39 +05:30
|
|
|
|
2019-02-06 09:48:37 +02:00
|
|
|
#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
|
|
|
|
#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
|
|
|
|
|
|
|
|
#define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
|
|
|
|
#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
|
|
|
|
#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
|
|
|
|
|
2020-02-28 19:50:07 +02:00
|
|
|
/* Interrupt defines */
|
2018-10-11 10:17:16 +03:00
|
|
|
#define IGC_START_ITR 648 /* ~6000 ints/sec */
|
|
|
|
#define IGC_4K_ITR 980
|
|
|
|
#define IGC_20K_ITR 196
|
|
|
|
#define IGC_70K_ITR 56
|
|
|
|
|
2018-10-11 10:17:22 +03:00
|
|
|
#define IGC_DEFAULT_ITR 3 /* dynamic */
|
|
|
|
#define IGC_MAX_ITR_USECS 10000
|
|
|
|
#define IGC_MIN_ITR_USECS 10
|
|
|
|
#define NON_Q_VECTORS 1
|
|
|
|
#define MAX_MSIX_ENTRIES 10
|
|
|
|
|
|
|
|
/* TX/RX descriptor defines */
|
|
|
|
#define IGC_DEFAULT_TXD 256
|
|
|
|
#define IGC_DEFAULT_TX_WORK 128
|
|
|
|
#define IGC_MIN_TXD 80
|
|
|
|
#define IGC_MAX_TXD 4096
|
|
|
|
|
|
|
|
#define IGC_DEFAULT_RXD 256
|
|
|
|
#define IGC_MIN_RXD 80
|
|
|
|
#define IGC_MAX_RXD 4096
|
|
|
|
|
2018-10-11 10:17:19 +03:00
|
|
|
/* Supported Rx Buffer Sizes */
|
|
|
|
#define IGC_RXBUFFER_256 256
|
|
|
|
#define IGC_RXBUFFER_2048 2048
|
|
|
|
#define IGC_RXBUFFER_3072 3072
|
|
|
|
|
2019-01-30 19:13:14 +02:00
|
|
|
#define AUTO_ALL_MODES 0
|
2018-10-11 10:17:19 +03:00
|
|
|
#define IGC_RX_HDR_LEN IGC_RXBUFFER_256
|
|
|
|
|
2019-12-02 15:19:50 -08:00
|
|
|
/* Transmit and receive latency (for PTP timestamps) */
|
2020-08-18 16:40:01 -07:00
|
|
|
#define IGC_I225_TX_LATENCY_10 240
|
|
|
|
#define IGC_I225_TX_LATENCY_100 58
|
|
|
|
#define IGC_I225_TX_LATENCY_1000 80
|
|
|
|
#define IGC_I225_TX_LATENCY_2500 1325
|
|
|
|
#define IGC_I225_RX_LATENCY_10 6450
|
|
|
|
#define IGC_I225_RX_LATENCY_100 185
|
|
|
|
#define IGC_I225_RX_LATENCY_1000 300
|
|
|
|
#define IGC_I225_RX_LATENCY_2500 1485
|
2019-12-02 15:19:50 -08:00
|
|
|
|
2018-10-11 10:17:19 +03:00
|
|
|
/* RX and TX descriptor control thresholds.
|
|
|
|
* PTHRESH - MAC will consider prefetch if it has fewer than this number of
|
|
|
|
* descriptors available in its onboard memory.
|
|
|
|
* Setting this to 0 disables RX descriptor prefetch.
|
|
|
|
* HTHRESH - MAC will only prefetch if there are at least this many descriptors
|
|
|
|
* available in host memory.
|
|
|
|
* If PTHRESH is 0, this should also be 0.
|
|
|
|
* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
|
|
|
|
* descriptors until either it has this many to write back, or the
|
|
|
|
* ITR timer expires.
|
|
|
|
*/
|
|
|
|
#define IGC_RX_PTHRESH 8
|
|
|
|
#define IGC_RX_HTHRESH 8
|
|
|
|
#define IGC_TX_PTHRESH 8
|
|
|
|
#define IGC_TX_HTHRESH 1
|
|
|
|
#define IGC_RX_WTHRESH 4
|
|
|
|
#define IGC_TX_WTHRESH 16
|
|
|
|
|
|
|
|
#define IGC_RX_DMA_ATTR \
|
|
|
|
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
|
|
|
|
|
|
|
|
#define IGC_TS_HDR_LEN 16
|
|
|
|
|
|
|
|
#define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
|
|
|
|
|
|
|
|
#if (PAGE_SIZE < 8192)
|
|
|
|
#define IGC_MAX_FRAME_BUILD_SKB \
|
|
|
|
(SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
|
|
|
|
#else
|
|
|
|
#define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
|
|
|
|
#endif
|
|
|
|
|
2018-10-11 10:17:22 +03:00
|
|
|
/* How many Rx Buffers do we bundle into one write to the hardware ? */
|
|
|
|
#define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
|
|
|
|
|
2019-08-08 09:12:23 +03:00
|
|
|
/* VLAN info */
|
|
|
|
#define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
|
2021-06-04 01:44:54 +08:00
|
|
|
#define IGC_TX_FLAGS_VLAN_SHIFT 16
|
2019-08-08 09:12:23 +03:00
|
|
|
|
2018-10-11 10:17:22 +03:00
|
|
|
/* igc_test_staterr - tests bits within Rx descriptor status and error fields */
|
|
|
|
static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
|
|
|
|
const u32 stat_err_bits)
|
|
|
|
{
|
|
|
|
return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
|
|
|
|
}
|
|
|
|
|
2018-10-11 10:17:13 +03:00
|
|
|
enum igc_state_t {
|
|
|
|
__IGC_TESTING,
|
|
|
|
__IGC_RESETTING,
|
|
|
|
__IGC_DOWN,
|
|
|
|
__IGC_PTP_TX_IN_PROGRESS,
|
|
|
|
};
|
|
|
|
|
2018-10-11 10:17:22 +03:00
|
|
|
enum igc_tx_flags {
|
|
|
|
/* cmd_type flags */
|
|
|
|
IGC_TX_FLAGS_VLAN = 0x01,
|
|
|
|
IGC_TX_FLAGS_TSO = 0x02,
|
|
|
|
IGC_TX_FLAGS_TSTAMP = 0x04,
|
|
|
|
|
|
|
|
/* olinfo flags */
|
|
|
|
IGC_TX_FLAGS_IPV4 = 0x10,
|
|
|
|
IGC_TX_FLAGS_CSUM = 0x20,
|
|
|
|
};
|
|
|
|
|
2018-10-11 10:17:28 +03:00
|
|
|
enum igc_boards {
|
|
|
|
board_base,
|
|
|
|
};
|
|
|
|
|
2018-10-11 10:17:22 +03:00
|
|
|
/* The largest size we can write to the descriptor is 65535. In order to
|
|
|
|
* maintain a power of two alignment we have to limit ourselves to 32K.
|
|
|
|
*/
|
|
|
|
#define IGC_MAX_TXD_PWR 15
|
|
|
|
#define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
|
|
|
|
|
|
|
|
/* Tx Descriptors needed, worst case */
|
|
|
|
#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
|
|
|
|
#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
|
|
|
|
|
2021-04-22 23:25:53 -07:00
|
|
|
enum igc_tx_buffer_type {
|
|
|
|
IGC_TX_BUFFER_TYPE_SKB,
|
|
|
|
IGC_TX_BUFFER_TYPE_XDP,
|
2021-04-22 23:25:55 -07:00
|
|
|
IGC_TX_BUFFER_TYPE_XSK,
|
2021-04-22 23:25:53 -07:00
|
|
|
};
|
|
|
|
|
2018-10-11 10:17:19 +03:00
|
|
|
/* wrapper around a pointer to a socket buffer,
|
|
|
|
* so a DMA handle can be stored along with the buffer
|
|
|
|
*/
|
|
|
|
struct igc_tx_buffer {
|
|
|
|
union igc_adv_tx_desc *next_to_watch;
|
|
|
|
unsigned long time_stamp;
|
2021-04-22 23:25:53 -07:00
|
|
|
enum igc_tx_buffer_type type;
|
2021-03-09 23:13:21 -08:00
|
|
|
union {
|
|
|
|
struct sk_buff *skb;
|
|
|
|
struct xdp_frame *xdpf;
|
|
|
|
};
|
2018-10-11 10:17:19 +03:00
|
|
|
unsigned int bytecount;
|
|
|
|
u16 gso_segs;
|
|
|
|
__be16 protocol;
|
|
|
|
|
|
|
|
DEFINE_DMA_UNMAP_ADDR(dma);
|
|
|
|
DEFINE_DMA_UNMAP_LEN(len);
|
|
|
|
u32 tx_flags;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct igc_rx_buffer {
|
2021-04-22 23:25:54 -07:00
|
|
|
union {
|
|
|
|
struct {
|
|
|
|
dma_addr_t dma;
|
|
|
|
struct page *page;
|
2018-10-11 10:17:19 +03:00
|
|
|
#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
|
2021-04-22 23:25:54 -07:00
|
|
|
__u32 page_offset;
|
2018-10-11 10:17:19 +03:00
|
|
|
#else
|
2021-04-22 23:25:54 -07:00
|
|
|
__u16 page_offset;
|
2018-10-11 10:17:19 +03:00
|
|
|
#endif
|
2021-04-22 23:25:54 -07:00
|
|
|
__u16 pagecnt_bias;
|
|
|
|
};
|
|
|
|
struct xdp_buff *xdp;
|
|
|
|
};
|
2018-10-11 10:17:19 +03:00
|
|
|
};
|
|
|
|
|
2018-10-11 10:17:13 +03:00
|
|
|
struct igc_q_vector {
|
|
|
|
struct igc_adapter *adapter; /* backlink */
|
2018-10-11 10:17:16 +03:00
|
|
|
void __iomem *itr_register;
|
|
|
|
u32 eims_value; /* EIMS mask value */
|
|
|
|
|
|
|
|
u16 itr_val;
|
|
|
|
u8 set_itr;
|
|
|
|
|
|
|
|
struct igc_ring_container rx, tx;
|
2018-10-11 10:17:13 +03:00
|
|
|
|
|
|
|
struct napi_struct napi;
|
2018-10-11 10:17:16 +03:00
|
|
|
|
|
|
|
struct rcu_head rcu; /* to avoid race with update stats on free */
|
|
|
|
char name[IFNAMSIZ + 9];
|
|
|
|
struct net_device poll_dev;
|
|
|
|
|
|
|
|
/* for dynamic allocation of rings associated with this q_vector */
|
2020-02-24 10:41:06 -06:00
|
|
|
struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
|
2018-10-11 10:17:13 +03:00
|
|
|
};
|
|
|
|
|
2019-02-14 13:31:37 +02:00
|
|
|
enum igc_filter_match_flags {
|
2021-06-28 21:43:29 -07:00
|
|
|
IGC_FILTER_FLAG_ETHER_TYPE = BIT(0),
|
|
|
|
IGC_FILTER_FLAG_VLAN_TCI = BIT(1),
|
|
|
|
IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2),
|
|
|
|
IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3),
|
|
|
|
IGC_FILTER_FLAG_USER_DATA = BIT(4),
|
|
|
|
IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5),
|
2019-02-14 13:31:37 +02:00
|
|
|
};
|
|
|
|
|
2020-04-24 13:16:10 -07:00
|
|
|
struct igc_nfc_filter {
|
2019-02-14 13:31:37 +02:00
|
|
|
u8 match_flags;
|
2020-04-24 13:16:11 -07:00
|
|
|
u16 etype;
|
2021-06-28 21:43:29 -07:00
|
|
|
__be16 vlan_etype;
|
2020-04-24 13:16:11 -07:00
|
|
|
u16 vlan_tci;
|
2019-02-14 13:31:37 +02:00
|
|
|
u8 src_addr[ETH_ALEN];
|
|
|
|
u8 dst_addr[ETH_ALEN];
|
2021-06-28 21:43:29 -07:00
|
|
|
u8 user_data[8];
|
|
|
|
u8 user_mask[8];
|
|
|
|
u8 flex_index;
|
|
|
|
u8 rx_queue;
|
|
|
|
u8 prio;
|
|
|
|
u8 immediate_irq;
|
|
|
|
u8 drop;
|
2019-02-14 13:31:37 +02:00
|
|
|
};
|
|
|
|
|
2020-04-24 13:16:10 -07:00
|
|
|
struct igc_nfc_rule {
|
igc: Fix NFC rules restoration
When network interface is brought up, the driver re-enables the NFC
rules previously configured. However, this is done in reverse order
the rules were added and hardware filters are configured differently.
For example, consider the following rules:
$ ethtool -N eth0 flow-type ether dst 00:00:00:00:00:AA queue 0
$ ethtool -N eth0 flow-type ether dst 00:00:00:00:00:BB queue 1
$ ethtool -N eth0 flow-type ether dst 00:00:00:00:00:CC queue 2
$ ethtool -N eth0 flow-type ether dst 00:00:00:00:00:DD queue 3
RAL/RAH registers are configure so filter index 1 has address ending
with AA, filter index 2 has address ending in BB, and so on.
If we bring the interface down and up again, RAL/RAH registers are
configured so filter index 1 has address ending in DD, filter index 2
has CC, and so on. IOW, in reverse order we had before bringing the
interface down.
This issue can be fixed by traversing adapter->nfc_rule_list in
backwards when restoring the rules. Since hlist doesn't support
backwards traversal, this patch replaces it by list_head and fixes
igc_restore_nfc_rules() accordingly.
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2020-04-24 13:16:17 -07:00
|
|
|
struct list_head list;
|
2020-04-24 13:16:10 -07:00
|
|
|
struct igc_nfc_filter filter;
|
2020-04-24 13:16:13 -07:00
|
|
|
u32 location;
|
2019-02-14 13:31:37 +02:00
|
|
|
u16 action;
|
2021-06-28 21:43:31 -07:00
|
|
|
bool flex;
|
2019-02-14 13:31:37 +02:00
|
|
|
};
|
|
|
|
|
2021-06-28 21:43:29 -07:00
|
|
|
/* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority
|
|
|
|
* based, 8 ethertype based and 32 Flex filter based rules.
|
2020-05-12 10:35:53 -07:00
|
|
|
*/
|
2021-06-28 21:43:29 -07:00
|
|
|
#define IGC_MAX_RXNFC_RULES 64
|
2018-10-11 10:17:13 +03:00
|
|
|
|
2021-06-28 21:43:28 -07:00
|
|
|
struct igc_flex_filter {
|
|
|
|
u8 index;
|
|
|
|
u8 data[128];
|
|
|
|
u8 mask[16];
|
|
|
|
u8 length;
|
|
|
|
u8 rx_queue;
|
|
|
|
u8 prio;
|
|
|
|
u8 immediate_irq;
|
|
|
|
u8 drop;
|
|
|
|
};
|
|
|
|
|
2018-10-11 10:17:19 +03:00
|
|
|
/* igc_desc_unused - calculate if we have unused descriptors */
|
|
|
|
static inline u16 igc_desc_unused(const struct igc_ring *ring)
|
|
|
|
{
|
|
|
|
u16 ntc = ring->next_to_clean;
|
|
|
|
u16 ntu = ring->next_to_use;
|
|
|
|
|
|
|
|
return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
|
|
|
|
}
|
|
|
|
|
2018-10-11 10:17:31 +03:00
|
|
|
static inline s32 igc_get_phy_info(struct igc_hw *hw)
|
|
|
|
{
|
|
|
|
if (hw->phy.ops.get_phy_info)
|
|
|
|
return hw->phy.ops.get_phy_info(hw);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline s32 igc_reset_phy(struct igc_hw *hw)
|
|
|
|
{
|
|
|
|
if (hw->phy.ops.reset)
|
|
|
|
return hw->phy.ops.reset(hw);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-10-11 10:17:19 +03:00
|
|
|
static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
|
|
|
|
{
|
|
|
|
return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
|
|
|
|
}
|
|
|
|
|
|
|
|
enum igc_ring_flags_t {
|
|
|
|
IGC_RING_FLAG_RX_3K_BUFFER,
|
|
|
|
IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
|
|
|
|
IGC_RING_FLAG_RX_SCTP_CSUM,
|
|
|
|
IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
|
|
|
|
IGC_RING_FLAG_TX_CTX_IDX,
|
2021-04-22 23:25:54 -07:00
|
|
|
IGC_RING_FLAG_TX_DETECT_HANG,
|
|
|
|
IGC_RING_FLAG_AF_XDP_ZC,
|
2018-10-11 10:17:19 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
#define ring_uses_large_buffer(ring) \
|
|
|
|
test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
|
2021-03-09 23:13:19 -08:00
|
|
|
#define set_ring_uses_large_buffer(ring) \
|
|
|
|
set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
|
|
|
|
#define clear_ring_uses_large_buffer(ring) \
|
|
|
|
clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
|
2018-10-11 10:17:19 +03:00
|
|
|
|
|
|
|
#define ring_uses_build_skb(ring) \
|
|
|
|
test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
|
|
|
|
|
|
|
|
static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
|
|
|
|
{
|
|
|
|
#if (PAGE_SIZE < 8192)
|
|
|
|
if (ring_uses_large_buffer(ring))
|
|
|
|
return IGC_RXBUFFER_3072;
|
|
|
|
|
|
|
|
if (ring_uses_build_skb(ring))
|
|
|
|
return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
|
|
|
|
#endif
|
|
|
|
return IGC_RXBUFFER_2048;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
|
|
|
|
{
|
|
|
|
#if (PAGE_SIZE < 8192)
|
|
|
|
if (ring_uses_large_buffer(ring))
|
|
|
|
return 1;
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-10-11 10:17:36 +03:00
|
|
|
static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
|
|
|
|
{
|
|
|
|
if (hw->phy.ops.read_reg)
|
|
|
|
return hw->phy.ops.read_reg(hw, offset, data);
|
|
|
|
|
2021-05-21 12:50:19 -07:00
|
|
|
return -EOPNOTSUPP;
|
2018-10-11 10:17:36 +03:00
|
|
|
}
|
|
|
|
|
2019-01-30 19:13:14 +02:00
|
|
|
void igc_reinit_locked(struct igc_adapter *);
|
2020-04-24 13:16:18 -07:00
|
|
|
struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
|
|
|
|
u32 location);
|
|
|
|
int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
|
|
|
|
void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
|
2019-01-30 19:13:14 +02:00
|
|
|
|
2019-12-02 15:19:49 -08:00
|
|
|
void igc_ptp_init(struct igc_adapter *adapter);
|
|
|
|
void igc_ptp_reset(struct igc_adapter *adapter);
|
2020-01-22 11:21:13 +02:00
|
|
|
void igc_ptp_suspend(struct igc_adapter *adapter);
|
2019-12-02 15:19:49 -08:00
|
|
|
void igc_ptp_stop(struct igc_adapter *adapter);
|
2021-03-09 23:13:18 -08:00
|
|
|
ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
|
2019-12-02 15:19:49 -08:00
|
|
|
int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
|
|
|
|
int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
|
2019-12-02 15:19:51 -08:00
|
|
|
void igc_ptp_tx_hang(struct igc_adapter *adapter);
|
2020-09-02 16:36:56 -07:00
|
|
|
void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
|
2019-12-02 15:19:51 -08:00
|
|
|
|
2018-10-11 10:17:19 +03:00
|
|
|
#define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
|
|
|
|
|
2018-10-11 10:17:22 +03:00
|
|
|
#define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
|
|
|
|
|
2018-10-11 10:17:19 +03:00
|
|
|
#define IGC_RX_DESC(R, i) \
|
|
|
|
(&(((union igc_adv_rx_desc *)((R)->desc))[i]))
|
|
|
|
#define IGC_TX_DESC(R, i) \
|
|
|
|
(&(((union igc_adv_tx_desc *)((R)->desc))[i]))
|
|
|
|
#define IGC_TX_CTXTDESC(R, i) \
|
|
|
|
(&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
|
|
|
|
|
2018-10-11 10:17:08 +03:00
|
|
|
#endif /* _IGC_H_ */
|