2021-07-18 13:40:49 +02:00
|
|
|
# SPDX-License-Identifier: GPL-2.0
|
|
|
|
%YAML 1.2
|
|
|
|
---
|
|
|
|
$id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
|
|
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
|
|
|
|
title: Synopsys DesignWare PCIe endpoint interface
|
|
|
|
|
|
|
|
maintainers:
|
|
|
|
- Jingoo Han <jingoohan1@gmail.com>
|
|
|
|
- Gustavo Pimentel <gustavo.pimentel@synopsys.com>
|
|
|
|
|
|
|
|
description: |
|
|
|
|
Synopsys DesignWare PCIe host controller endpoint
|
|
|
|
|
|
|
|
allOf:
|
|
|
|
- $ref: /schemas/pci/pci-ep.yaml#
|
dt-bindings: PCI: dwc: Detach common RP/EP DT bindings
Currently both DW PCIe Root Port and End-point DT bindings are defined as
separate schemas. Carefully looking at them, at the hardware reference
manuals and seeing there is a generic part of the driver used by the both
RP and EP drivers we can greatly simplify the DW PCIe controller bindings
by moving some of the properties into the common DT schema. It concerns
the PERST GPIO control, number of lanes, number of iATU windows and CDM
check properties. They will be defined in the snps,dw-pcie-common.yaml
schema which will be referenced in the DW PCIe Root Port and End-point DT
bindings in order to evaluate the common for both of these controllers
properties. The rest of properties like reg{,-names}, clock{s,-names},
reset{s,-names}, etc will be consolidate there in one of the next commits.
Link: https://lore.kernel.org/r/20221113191301.5526-4-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
2022-11-13 22:12:44 +03:00
|
|
|
- $ref: /schemas/pci/snps,dw-pcie-common.yaml#
|
2021-07-18 13:40:49 +02:00
|
|
|
|
|
|
|
properties:
|
|
|
|
compatible:
|
|
|
|
anyOf:
|
|
|
|
- {}
|
|
|
|
- const: snps,dw-pcie-ep
|
|
|
|
|
|
|
|
reg:
|
|
|
|
description: |
|
|
|
|
It should contain Data Bus Interface (dbi) and config registers for all
|
|
|
|
versions.
|
|
|
|
For designware core version >= 4.80, it may contain ATU address space.
|
|
|
|
minItems: 2
|
|
|
|
maxItems: 4
|
|
|
|
|
|
|
|
reg-names:
|
|
|
|
minItems: 2
|
|
|
|
maxItems: 4
|
|
|
|
items:
|
|
|
|
enum: [dbi, dbi2, config, atu, addr_space, link, atu_dma, appl]
|
|
|
|
|
|
|
|
required:
|
|
|
|
- reg
|
|
|
|
- reg-names
|
|
|
|
- compatible
|
|
|
|
|
dt-bindings: PCI: designware: Fix 'unevaluatedProperties' warnings
With 'unevaluatedProperties' support implemented, there's a number of
warnings from the Designware PCIe based bindings:
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dt.yaml: pcie@1ffc000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'device_type', 'bus-range', 'ranges', '#interrupt-cells', 'interrupt-map-mask', 'interrupt-map' were unexpected)
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dt.yaml: pcie@1ffc000: Unevaluated properties are not allowed ('clock-names' was unexpected)
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f4000000: Unevaluated properties are not allowed ('bus-range', '#address-cells', '#size-cells', 'device_type', 'ranges', 'num-lanes', '#interrupt-cells', 'interrupts', 'interrupt-names', 'interrupt-map-mask', 'interrupt-map', 'clocks', 'clock-names' were unexpected)
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f4000000: Unevaluated properties are not allowed ('clock-names' was unexpected)
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: Unevaluated properties are not allowed ('bus-range', '#address-cells', '#size-cells', 'device_type', 'phys', 'ranges', 'num-lanes', '#interrupt-cells', 'interrupts', 'interrupt-names', 'interrupt-map-mask', 'interrupt-map', 'reset-gpios', 'pcie@0,0' were unexpected)
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: Unevaluated properties are not allowed ('phys', 'hisilicon,clken-gpios' were unexpected)
Documentation/devicetree/bindings/pci/intel-gw-pcie.example.dt.yaml: pcie@d0e00000: Unevaluated properties are not allowed ('device_type', '#address-cells', '#size-cells', 'linux,pci-domain', 'bus-range', '#interrupt-cells', 'interrupt-map-mask', 'interrupt-map' were unexpected)
Documentation/devicetree/bindings/pci/intel-gw-pcie.example.dt.yaml: pcie@d0e00000: Unevaluated properties are not allowed ('resets', 'phys', 'phy-names', 'reset-assert-ms' were unexpected)
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.example.dt.yaml: pcie@fe280000: Unevaluated properties are not allowed ('clock-names', 'msi-map', 'phys', 'phy-names', 'power-domains', 'resets', 'reset-names' were unexpected)
Documentation/devicetree/bindings/pci/samsung,exynos-pcie.example.dt.yaml: pcie@15700000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', '#interrupt-cells', 'device_type', 'bus-range', 'ranges', 'interrupt-map-mask', 'interrupt-map' were unexpected)
Documentation/devicetree/bindings/pci/samsung,exynos-pcie.example.dt.yaml: pcie@15700000: Unevaluated properties are not allowed ('clock-names', 'phys', 'vdd10-supply', 'vdd18-supply' were unexpected)
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.example.dt.yaml: pcie@e00000000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', '#interrupt-cells', 'device_type', 'dma-coherent', 'bus-range', 'ranges', 'interrupts', 'interrupt-parent', 'interrupt-map-mask', 'interrupt-map', 'clock-names', 'clocks' were unexpected)
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.example.dt.yaml: pcie@e00000000: Unevaluated properties are not allowed ('dma-coherent', 'clock-names', 'resets', 'pwren-gpios' were unexpected)
Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.example.dt.yaml: pcie-ep@66000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'reset-names', 'resets', 'phy-names', 'phys' were unexpected)
Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.example.dt.yaml: pcie@28400000: Unevaluated properties are not allowed ('clock-names' was unexpected)
Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.example.dt.yaml: pcie@28400000: Unevaluated properties are not allowed ('device_type', 'bus-range', 'num-viewport', '#address-cells', '#size-cells', '#interrupt-cells', 'ranges', 'interrupt-names', 'interrupt-map-mask', 'interrupt-map', 'max-link-speed' were unexpected)
The main problem is that snps,dw-pcie.yaml and snps,dw-pcie-ep.yaml
shouldn't set 'unevaluatedProperties: false'. Otherwise, bindings that
reference them cannot add additional properties. With that addressed,
there's a handful of other undocumented properties to add.
Cc: Xiaowei Song <songxiaowei@hisilicon.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Greentime Hu <greentime.hu@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: linux-pci@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211206194426.2470080-1-robh@kernel.org
2021-12-06 13:44:25 -06:00
|
|
|
additionalProperties: true
|
2021-07-18 13:40:49 +02:00
|
|
|
|
|
|
|
examples:
|
|
|
|
- |
|
|
|
|
bus {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
pcie-ep@dfd00000 {
|
|
|
|
compatible = "snps,dw-pcie-ep";
|
|
|
|
reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
|
|
|
|
<0xdfc01000 0x0001000>, /* IP registers 2 */
|
|
|
|
<0xd0000000 0x2000000>; /* Configuration space */
|
|
|
|
reg-names = "dbi", "dbi2", "addr_space";
|
|
|
|
};
|
|
|
|
};
|