2023-11-02 13:39:05 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2023 SUSE LLC */
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#include <linux/bpf.h>
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#include <bpf/bpf_helpers.h>
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selftests/bpf: Add selftests for load-acquire and store-release instructions
Add several ./test_progs tests:
- arena_atomics/load_acquire
- arena_atomics/store_release
- verifier_load_acquire/*
- verifier_store_release/*
- verifier_precision/bpf_load_acquire
- verifier_precision/bpf_store_release
The last two tests are added to check if backtrack_insn() handles the
new instructions correctly.
Additionally, the last test also makes sure that the verifier
"remembers" the value (in src_reg) we store-release into e.g. a stack
slot. For example, if we take a look at the test program:
#0: r1 = 8;
/* store_release((u64 *)(r10 - 8), r1); */
#1: .8byte %[store_release];
#2: r1 = *(u64 *)(r10 - 8);
#3: r2 = r10;
#4: r2 += r1;
#5: r0 = 0;
#6: exit;
At #1, if the verifier doesn't remember that we wrote 8 to the stack,
then later at #4 we would be adding an unbounded scalar value to the
stack pointer, which would cause the program to be rejected:
VERIFIER LOG:
=============
...
math between fp pointer and register with unbounded min value is not allowed
For easier CI integration, instead of using built-ins like
__atomic_{load,store}_n() which depend on the new
__BPF_FEATURE_LOAD_ACQ_STORE_REL pre-defined macro, manually craft
load-acquire/store-release instructions using __imm_insn(), as suggested
by Eduard.
All new tests depend on:
(1) Clang major version >= 18, and
(2) ENABLE_ATOMICS_TESTS is defined (currently implies -mcpu=v3 or
v4), and
(3) JIT supports load-acquire/store-release (currently arm64 and
x86-64)
In .../progs/arena_atomics.c:
/* 8-byte-aligned */
__u8 __arena_global load_acquire8_value = 0x12;
/* 1-byte hole */
__u16 __arena_global load_acquire16_value = 0x1234;
That 1-byte hole in the .addr_space.1 ELF section caused clang-17 to
crash:
fatal error: error in backend: unable to write nop sequence of 1 bytes
To work around such llvm-17 CI job failures, conditionally define
__arena_global variables as 64-bit if __clang_major__ < 18, to make sure
.addr_space.1 has no holes. Ideally we should avoid compiling this file
using clang-17 at all (arena tests depend on
__BPF_FEATURE_ADDR_SPACE_CAST, and are skipped for llvm-17 anyway), but
that is a separate topic.
Acked-by: Eduard Zingerman <eddyz87@gmail.com>
Signed-off-by: Peilin Ye <yepeilin@google.com>
Link: https://lore.kernel.org/r/1b46c6feaf0f1b6984d9ec80e500cc7383e9da1a.1741049567.git.yepeilin@google.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2025-03-04 01:06:46 +00:00
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#include "../../../include/linux/filter.h"
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2023-11-02 13:39:05 +08:00
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#include "bpf_misc.h"
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SEC("?raw_tp")
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__success __log_level(2)
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__msg("mark_precise: frame0: regs=r2 stack= before 3: (bf) r1 = r10")
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__msg("mark_precise: frame0: regs=r2 stack= before 2: (55) if r2 != 0xfffffff8 goto pc+2")
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__msg("mark_precise: frame0: regs=r2 stack= before 1: (87) r2 = -r2")
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__msg("mark_precise: frame0: regs=r2 stack= before 0: (b7) r2 = 8")
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__naked int bpf_neg(void)
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{
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asm volatile (
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"r2 = 8;"
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"r2 = -r2;"
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"if r2 != -8 goto 1f;"
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"r1 = r10;"
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"r1 += r2;"
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"1:"
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"r0 = 0;"
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"exit;"
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::: __clobber_all);
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}
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SEC("?raw_tp")
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__success __log_level(2)
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__msg("mark_precise: frame0: regs=r2 stack= before 3: (bf) r1 = r10")
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__msg("mark_precise: frame0: regs=r2 stack= before 2: (55) if r2 != 0x0 goto pc+2")
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__msg("mark_precise: frame0: regs=r2 stack= before 1: (d4) r2 = le16 r2")
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__msg("mark_precise: frame0: regs=r2 stack= before 0: (b7) r2 = 0")
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__naked int bpf_end_to_le(void)
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{
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asm volatile (
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"r2 = 0;"
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"r2 = le16 r2;"
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"if r2 != 0 goto 1f;"
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"r1 = r10;"
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"r1 += r2;"
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"1:"
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"r0 = 0;"
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"exit;"
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::: __clobber_all);
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}
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SEC("?raw_tp")
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__success __log_level(2)
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__msg("mark_precise: frame0: regs=r2 stack= before 3: (bf) r1 = r10")
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__msg("mark_precise: frame0: regs=r2 stack= before 2: (55) if r2 != 0x0 goto pc+2")
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__msg("mark_precise: frame0: regs=r2 stack= before 1: (dc) r2 = be16 r2")
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__msg("mark_precise: frame0: regs=r2 stack= before 0: (b7) r2 = 0")
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__naked int bpf_end_to_be(void)
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{
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asm volatile (
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"r2 = 0;"
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"r2 = be16 r2;"
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"if r2 != 0 goto 1f;"
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"r1 = r10;"
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"r1 += r2;"
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"1:"
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"r0 = 0;"
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"exit;"
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::: __clobber_all);
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}
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#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86) || \
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(defined(__TARGET_ARCH_riscv) && __riscv_xlen == 64) || \
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defined(__TARGET_ARCH_arm) || defined(__TARGET_ARCH_s390)) && \
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__clang_major__ >= 18
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SEC("?raw_tp")
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__success __log_level(2)
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__msg("mark_precise: frame0: regs=r2 stack= before 3: (bf) r1 = r10")
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__msg("mark_precise: frame0: regs=r2 stack= before 2: (55) if r2 != 0x0 goto pc+2")
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__msg("mark_precise: frame0: regs=r2 stack= before 1: (d7) r2 = bswap16 r2")
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__msg("mark_precise: frame0: regs=r2 stack= before 0: (b7) r2 = 0")
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__naked int bpf_end_bswap(void)
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{
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asm volatile (
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"r2 = 0;"
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"r2 = bswap16 r2;"
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"if r2 != 0 goto 1f;"
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"r1 = r10;"
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"r1 += r2;"
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"1:"
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"r0 = 0;"
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"exit;"
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::: __clobber_all);
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}
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2025-05-07 03:43:13 +00:00
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#ifdef CAN_USE_LOAD_ACQ_STORE_REL
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selftests/bpf: Add selftests for load-acquire and store-release instructions
Add several ./test_progs tests:
- arena_atomics/load_acquire
- arena_atomics/store_release
- verifier_load_acquire/*
- verifier_store_release/*
- verifier_precision/bpf_load_acquire
- verifier_precision/bpf_store_release
The last two tests are added to check if backtrack_insn() handles the
new instructions correctly.
Additionally, the last test also makes sure that the verifier
"remembers" the value (in src_reg) we store-release into e.g. a stack
slot. For example, if we take a look at the test program:
#0: r1 = 8;
/* store_release((u64 *)(r10 - 8), r1); */
#1: .8byte %[store_release];
#2: r1 = *(u64 *)(r10 - 8);
#3: r2 = r10;
#4: r2 += r1;
#5: r0 = 0;
#6: exit;
At #1, if the verifier doesn't remember that we wrote 8 to the stack,
then later at #4 we would be adding an unbounded scalar value to the
stack pointer, which would cause the program to be rejected:
VERIFIER LOG:
=============
...
math between fp pointer and register with unbounded min value is not allowed
For easier CI integration, instead of using built-ins like
__atomic_{load,store}_n() which depend on the new
__BPF_FEATURE_LOAD_ACQ_STORE_REL pre-defined macro, manually craft
load-acquire/store-release instructions using __imm_insn(), as suggested
by Eduard.
All new tests depend on:
(1) Clang major version >= 18, and
(2) ENABLE_ATOMICS_TESTS is defined (currently implies -mcpu=v3 or
v4), and
(3) JIT supports load-acquire/store-release (currently arm64 and
x86-64)
In .../progs/arena_atomics.c:
/* 8-byte-aligned */
__u8 __arena_global load_acquire8_value = 0x12;
/* 1-byte hole */
__u16 __arena_global load_acquire16_value = 0x1234;
That 1-byte hole in the .addr_space.1 ELF section caused clang-17 to
crash:
fatal error: error in backend: unable to write nop sequence of 1 bytes
To work around such llvm-17 CI job failures, conditionally define
__arena_global variables as 64-bit if __clang_major__ < 18, to make sure
.addr_space.1 has no holes. Ideally we should avoid compiling this file
using clang-17 at all (arena tests depend on
__BPF_FEATURE_ADDR_SPACE_CAST, and are skipped for llvm-17 anyway), but
that is a separate topic.
Acked-by: Eduard Zingerman <eddyz87@gmail.com>
Signed-off-by: Peilin Ye <yepeilin@google.com>
Link: https://lore.kernel.org/r/1b46c6feaf0f1b6984d9ec80e500cc7383e9da1a.1741049567.git.yepeilin@google.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2025-03-04 01:06:46 +00:00
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SEC("?raw_tp")
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__success __log_level(2)
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__msg("mark_precise: frame0: regs=r2 stack= before 3: (bf) r3 = r10")
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__msg("mark_precise: frame0: regs=r2 stack= before 2: (db) r2 = load_acquire((u64 *)(r10 -8))")
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__msg("mark_precise: frame0: regs= stack=-8 before 1: (7b) *(u64 *)(r10 -8) = r1")
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__msg("mark_precise: frame0: regs=r1 stack= before 0: (b7) r1 = 8")
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__naked int bpf_load_acquire(void)
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{
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asm volatile (
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"r1 = 8;"
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"*(u64 *)(r10 - 8) = r1;"
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".8byte %[load_acquire_insn];" /* r2 = load_acquire((u64 *)(r10 - 8)); */
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"r3 = r10;"
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"r3 += r2;" /* mark_precise */
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"r0 = 0;"
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"exit;"
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:
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: __imm_insn(load_acquire_insn,
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BPF_ATOMIC_OP(BPF_DW, BPF_LOAD_ACQ, BPF_REG_2, BPF_REG_10, -8))
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: __clobber_all);
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}
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SEC("?raw_tp")
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__success __log_level(2)
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__msg("mark_precise: frame0: regs=r1 stack= before 3: (bf) r2 = r10")
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__msg("mark_precise: frame0: regs=r1 stack= before 2: (79) r1 = *(u64 *)(r10 -8)")
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__msg("mark_precise: frame0: regs= stack=-8 before 1: (db) store_release((u64 *)(r10 -8), r1)")
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__msg("mark_precise: frame0: regs=r1 stack= before 0: (b7) r1 = 8")
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__naked int bpf_store_release(void)
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{
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asm volatile (
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"r1 = 8;"
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".8byte %[store_release_insn];" /* store_release((u64 *)(r10 - 8), r1); */
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"r1 = *(u64 *)(r10 - 8);"
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"r2 = r10;"
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"r2 += r1;" /* mark_precise */
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"r0 = 0;"
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"exit;"
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:
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: __imm_insn(store_release_insn,
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BPF_ATOMIC_OP(BPF_DW, BPF_STORE_REL, BPF_REG_10, BPF_REG_1, -8))
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: __clobber_all);
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}
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2025-05-07 03:43:13 +00:00
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#endif /* CAN_USE_LOAD_ACQ_STORE_REL */
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2023-11-02 13:39:05 +08:00
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#endif /* v4 instruction */
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2023-11-09 16:26:38 -08:00
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SEC("?raw_tp")
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__success __log_level(2)
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/*
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* Without the bug fix there will be no history between "last_idx 3 first_idx 3"
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* and "parent state regs=" lines. "R0_w=6" parts are here to help anchor
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* expected log messages to the one specific mark_chain_precision operation.
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*
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* This is quite fragile: if verifier checkpointing heuristic changes, this
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* might need adjusting.
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*/
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__msg("2: (07) r0 += 1 ; R0_w=6")
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__msg("3: (35) if r0 >= 0xa goto pc+1")
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__msg("mark_precise: frame0: last_idx 3 first_idx 3 subseq_idx -1")
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__msg("mark_precise: frame0: regs=r0 stack= before 2: (07) r0 += 1")
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__msg("mark_precise: frame0: regs=r0 stack= before 1: (07) r0 += 1")
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__msg("mark_precise: frame0: regs=r0 stack= before 4: (05) goto pc-4")
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__msg("mark_precise: frame0: regs=r0 stack= before 3: (35) if r0 >= 0xa goto pc+1")
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__msg("mark_precise: frame0: parent state regs= stack=: R0_rw=P4")
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__msg("3: R0_w=6")
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__naked int state_loop_first_last_equal(void)
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{
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asm volatile (
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"r0 = 0;"
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"l0_%=:"
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"r0 += 1;"
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"r0 += 1;"
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/* every few iterations we'll have a checkpoint here with
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* first_idx == last_idx, potentially confusing precision
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* backtracking logic
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*/
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"if r0 >= 10 goto l1_%=;" /* checkpoint + mark_precise */
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"goto l0_%=;"
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"l1_%=:"
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"exit;"
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::: __clobber_common
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);
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}
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2025-05-23 21:13:40 -07:00
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__used __naked static void __bpf_cond_op_r10(void)
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{
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asm volatile (
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"r2 = 2314885393468386424 ll;"
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"goto +0;"
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"if r2 <= r10 goto +3;"
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"if r1 >= -1835016 goto +0;"
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"if r2 <= 8 goto +0;"
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"if r3 <= 0 goto +0;"
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"exit;"
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::: __clobber_all);
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}
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SEC("?raw_tp")
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__success __log_level(2)
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__msg("8: (bd) if r2 <= r10 goto pc+3")
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__msg("9: (35) if r1 >= 0xffe3fff8 goto pc+0")
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__msg("10: (b5) if r2 <= 0x8 goto pc+0")
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__msg("mark_precise: frame1: last_idx 10 first_idx 0 subseq_idx -1")
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__msg("mark_precise: frame1: regs=r2 stack= before 9: (35) if r1 >= 0xffe3fff8 goto pc+0")
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__msg("mark_precise: frame1: regs=r2 stack= before 8: (bd) if r2 <= r10 goto pc+3")
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__msg("mark_precise: frame1: regs=r2 stack= before 7: (05) goto pc+0")
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__naked void bpf_cond_op_r10(void)
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{
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asm volatile (
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"r3 = 0 ll;"
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"call __bpf_cond_op_r10;"
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"r0 = 0;"
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"exit;"
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::: __clobber_all);
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}
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SEC("?raw_tp")
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__success __log_level(2)
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__msg("3: (bf) r3 = r10")
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__msg("4: (bd) if r3 <= r2 goto pc+1")
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__msg("5: (b5) if r2 <= 0x8 goto pc+2")
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__msg("mark_precise: frame0: last_idx 5 first_idx 0 subseq_idx -1")
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__msg("mark_precise: frame0: regs=r2 stack= before 4: (bd) if r3 <= r2 goto pc+1")
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__msg("mark_precise: frame0: regs=r2 stack= before 3: (bf) r3 = r10")
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__naked void bpf_cond_op_not_r10(void)
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{
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asm volatile (
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"r0 = 0;"
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"r2 = 2314885393468386424 ll;"
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"r3 = r10;"
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"if r3 <= r2 goto +1;"
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"if r2 <= 8 goto +2;"
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"r0 = 2 ll;"
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"exit;"
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::: __clobber_all);
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}
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2025-06-25 09:40:25 -07:00
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SEC("lsm.s/socket_connect")
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__success __log_level(2)
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__msg("0: (b7) r0 = 1 ; R0_w=1")
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__msg("1: (84) w0 = -w0 ; R0_w=0xffffffff")
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__msg("mark_precise: frame0: last_idx 2 first_idx 0 subseq_idx -1")
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__msg("mark_precise: frame0: regs=r0 stack= before 1: (84) w0 = -w0")
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__msg("mark_precise: frame0: regs=r0 stack= before 0: (b7) r0 = 1")
|
|
|
|
__naked int bpf_neg_2(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* lsm.s/socket_connect requires a return value within [-4095, 0].
|
|
|
|
* Returning -1 is allowed
|
|
|
|
*/
|
|
|
|
asm volatile (
|
|
|
|
"r0 = 1;"
|
|
|
|
"w0 = -w0;"
|
|
|
|
"exit;"
|
|
|
|
::: __clobber_all);
|
|
|
|
}
|
|
|
|
|
|
|
|
SEC("lsm.s/socket_connect")
|
|
|
|
__failure __msg("At program exit the register R0 has")
|
|
|
|
__naked int bpf_neg_3(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* lsm.s/socket_connect requires a return value within [-4095, 0].
|
|
|
|
* Returning -10000 is not allowed.
|
|
|
|
*/
|
|
|
|
asm volatile (
|
|
|
|
"r0 = 10000;"
|
|
|
|
"w0 = -w0;"
|
|
|
|
"exit;"
|
|
|
|
::: __clobber_all);
|
|
|
|
}
|
|
|
|
|
|
|
|
SEC("lsm.s/socket_connect")
|
|
|
|
__success __log_level(2)
|
|
|
|
__msg("0: (b7) r0 = 1 ; R0_w=1")
|
|
|
|
__msg("1: (87) r0 = -r0 ; R0_w=-1")
|
|
|
|
__msg("mark_precise: frame0: last_idx 2 first_idx 0 subseq_idx -1")
|
|
|
|
__msg("mark_precise: frame0: regs=r0 stack= before 1: (87) r0 = -r0")
|
|
|
|
__msg("mark_precise: frame0: regs=r0 stack= before 0: (b7) r0 = 1")
|
|
|
|
__naked int bpf_neg_4(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* lsm.s/socket_connect requires a return value within [-4095, 0].
|
|
|
|
* Returning -1 is allowed
|
|
|
|
*/
|
|
|
|
asm volatile (
|
|
|
|
"r0 = 1;"
|
|
|
|
"r0 = -r0;"
|
|
|
|
"exit;"
|
|
|
|
::: __clobber_all);
|
|
|
|
}
|
|
|
|
|
|
|
|
SEC("lsm.s/socket_connect")
|
|
|
|
__failure __msg("At program exit the register R0 has")
|
|
|
|
__naked int bpf_neg_5(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* lsm.s/socket_connect requires a return value within [-4095, 0].
|
|
|
|
* Returning -10000 is not allowed.
|
|
|
|
*/
|
|
|
|
asm volatile (
|
|
|
|
"r0 = 10000;"
|
|
|
|
"r0 = -r0;"
|
|
|
|
"exit;"
|
|
|
|
::: __clobber_all);
|
|
|
|
}
|
|
|
|
|
2023-11-09 16:26:38 -08:00
|
|
|
char _license[] SEC("license") = "GPL";
|