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48 lines
1.3 KiB
C
48 lines
1.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Register definitions for Cirrus Logic CS48L32
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*
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* Copyright (C) 2017-2018, 2020, 2022, 2025 Cirrus Logic, Inc. and
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* Cirrus Logic International Semiconductor Ltd.
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*/
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#ifndef CS48L32_H
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#define CS48L32_H
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/* pll_id for snd_soc_component_set_pll() */
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#define CS48L32_FLL1_REFCLK 1
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/* source for snd_soc_component_set_pll() */
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#define CS48L32_FLL_SRC_NONE -1
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#define CS48L32_FLL_SRC_MCLK1 0
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#define CS48L32_FLL_SRC_PDMCLK 5
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#define CS48L32_FLL_SRC_ASP1_BCLK 8
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#define CS48L32_FLL_SRC_ASP2_BCLK 9
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#define CS48L32_FLL_SRC_ASP1_FSYNC 12
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#define CS48L32_FLL_SRC_ASP2_FSYNC 13
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/* clk_id for snd_soc_component_set_sysclk() and snd_soc_dai_set_sysclk() */
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#define CS48L32_CLK_SYSCLK_1 1
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#define CS48L32_CLK_SYSCLK_2 2
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#define CS48L32_CLK_SYSCLK_3 3
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#define CS48L32_CLK_SYSCLK_4 4
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#define CS48L32_CLK_DSPCLK 7
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#define CS48L32_CLK_PDM_FLLCLK 13
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/* source for snd_soc_component_set_sysclk() */
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#define CS48L32_CLK_SRC_MCLK1 0x0
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#define CS48L32_CLK_SRC_FLL1 0x4
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#define CS48L32_CLK_SRC_ASP1_BCLK 0x8
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#define CS48L32_CLK_SRC_ASP2_BCLK 0x9
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struct cs48l32 {
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struct regmap *regmap;
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struct device *dev;
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struct gpio_desc *reset_gpio;
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struct clk *mclk1;
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struct regulator_bulk_data core_supplies[2];
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struct regulator *vdd_d;
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int irq;
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};
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#endif
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