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linux/include/dt-bindings/clock/amlogic,a1-pll-clkc.h

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dt-bindings: clock: meson: add A1 PLL clock controller bindings Add the documentation and dt bindings for Amlogic A1 PLL clock controller. Also include new A1 clock controller dt bindings to MAINTAINERS. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230523135351.19133-4-ddrokosov@sberdevices.ru Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-05-23 16:53:48 +03:00
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
* Author: Jian Hu <jian.hu@amlogic.com>
*
* Copyright (c) 2023, SberDevices. All Rights Reserved.
* Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
*/
#ifndef __A1_PLL_CLKC_H
#define __A1_PLL_CLKC_H
dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every A1 pll ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-13-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-06-12 11:57:30 +02:00
#define CLKID_FIXED_PLL_DCO 0
dt-bindings: clock: meson: add A1 PLL clock controller bindings Add the documentation and dt bindings for Amlogic A1 PLL clock controller. Also include new A1 clock controller dt bindings to MAINTAINERS. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230523135351.19133-4-ddrokosov@sberdevices.ru Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-05-23 16:53:48 +03:00
#define CLKID_FIXED_PLL 1
dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every A1 pll ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-13-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-06-12 11:57:30 +02:00
#define CLKID_FCLK_DIV2_DIV 2
#define CLKID_FCLK_DIV3_DIV 3
#define CLKID_FCLK_DIV5_DIV 4
#define CLKID_FCLK_DIV7_DIV 5
dt-bindings: clock: meson: add A1 PLL clock controller bindings Add the documentation and dt bindings for Amlogic A1 PLL clock controller. Also include new A1 clock controller dt bindings to MAINTAINERS. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230523135351.19133-4-ddrokosov@sberdevices.ru Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-05-23 16:53:48 +03:00
#define CLKID_FCLK_DIV2 6
#define CLKID_FCLK_DIV3 7
#define CLKID_FCLK_DIV5 8
#define CLKID_FCLK_DIV7 9
#define CLKID_HIFI_PLL 10
dt-bindings: clock: meson: a1: pll: introduce new syspll bindings The 'syspll' PLL is a general-purpose PLL designed specifically for the CPU clock. It is capable of producing output frequencies within the range of 768MHz to 1536MHz. The 'syspll_in' source clock is an optional parent connection from the peripherals clock controller. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240515185103.20256-3-ddrokosov@salutedevices.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-05-15 21:47:25 +03:00
#define CLKID_SYS_PLL 11
dt-bindings: clock: meson: add A1 PLL clock controller bindings Add the documentation and dt bindings for Amlogic A1 PLL clock controller. Also include new A1 clock controller dt bindings to MAINTAINERS. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230523135351.19133-4-ddrokosov@sberdevices.ru Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-05-23 16:53:48 +03:00
#endif /* __A1_PLL_CLKC_H */
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