2020-03-02 02:15:21 +05:30
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/* SPDX-License-Identifier: GPL-2.0+ */
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2005-04-16 15:20:36 -07:00
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/*
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* Driver for 8250/16550-type serial ports
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*
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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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*
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* Copyright (C) 2001 Russell King.
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*/
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2021-05-20 11:43:34 +09:30
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#include <linux/bits.h>
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2005-09-01 15:56:26 +01:00
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#include <linux/serial_8250.h>
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2024-05-06 17:00:59 +03:00
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#include <linux/serial_core.h>
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2013-01-10 11:25:11 +02:00
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#include <linux/dmaengine.h>
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2019-06-20 08:24:20 +02:00
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#include "../serial_mctrl_gpio.h"
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2013-01-10 11:25:11 +02:00
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struct uart_8250_dma {
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2014-09-29 20:06:42 +02:00
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int (*tx_dma)(struct uart_8250_port *p);
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2016-04-09 22:14:36 -07:00
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int (*rx_dma)(struct uart_8250_port *p);
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2022-04-22 20:06:11 +02:00
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void (*prepare_tx_dma)(struct uart_8250_port *p);
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void (*prepare_rx_dma)(struct uart_8250_port *p);
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2014-09-29 20:06:42 +02:00
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2014-08-19 20:29:22 +03:00
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/* Filter function */
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2013-01-10 11:25:11 +02:00
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dma_filter_fn fn;
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2014-08-19 20:29:22 +03:00
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/* Parameter to the filter function */
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2013-01-10 11:25:11 +02:00
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void *rx_param;
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void *tx_param;
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struct dma_slave_config rxconf;
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struct dma_slave_config txconf;
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struct dma_chan *rxchan;
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struct dma_chan *txchan;
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2016-08-17 19:20:25 +03:00
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/* Device address base for DMA operations */
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phys_addr_t rx_dma_addr;
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phys_addr_t tx_dma_addr;
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/* DMA address of the buffer in memory */
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2013-01-10 11:25:11 +02:00
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dma_addr_t rx_addr;
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dma_addr_t tx_addr;
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dma_cookie_t rx_cookie;
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dma_cookie_t tx_cookie;
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void *rx_buf;
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size_t rx_size;
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size_t tx_size;
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2015-08-14 18:01:02 +02:00
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unsigned char tx_running;
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unsigned char tx_err;
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unsigned char rx_running;
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2013-01-10 11:25:11 +02:00
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};
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2005-04-16 15:20:36 -07:00
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struct old_serial_port {
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unsigned int uart;
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unsigned int baud_base;
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unsigned int port;
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unsigned int irq;
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2015-03-11 13:52:53 +02:00
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upf_t flags;
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2005-04-16 15:20:36 -07:00
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unsigned char io_type;
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2014-10-16 14:16:22 +05:30
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unsigned char __iomem *iomem_base;
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2005-04-16 15:20:36 -07:00
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unsigned short iomem_reg_shift;
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};
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struct serial8250_config {
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const char *name;
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unsigned short fifo_size;
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unsigned short tx_loadsz;
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unsigned char fcr;
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serial/uart/8250: Add tunable RX interrupt trigger I/F of FIFO buffers
Add tunable RX interrupt trigger I/F of FIFO buffers.
Serial devices are used as not only message communication devices but control
or sending communication devices. For the latter uses, normally small data
will be exchanged, so user applications want to receive data unit as soon as
possible for real-time tendency. If we have a sensor which sends a 1 byte data
each time and must control a device based on the sensor feedback, the RX
interrupt should be triggered for each data.
According to HW specification of serial UART devices, RX interrupt trigger
can be changed, but the trigger is hard-coded. For example, RX interrupt trigger
in 16550A can be set to 1, 4, 8, or 14 bytes for HW, but current driver sets
the trigger to only 8bytes.
This patch makes some devices change RX interrupt trigger from userland.
<How to use>
- Read current setting
# cat /sys/class/tty/ttyS0/rx_trig_bytes
8
- Write user setting
# echo 1 > /sys/class/tty/ttyS0/rx_trig_bytes
# cat /sys/class/tty/ttyS0/rx_trig_bytes
1
<Support uart devices>
- 16550A and Tegra (1, 4, 8, or 14 bytes)
- 16650V2 (8, 16, 24, or 28 bytes)
- 16654 (8, 16, 56, or 60 bytes)
- 16750 (1, 16, 32, or 56 bytes)
<Change log>
Changes in V9:
- Use attr_group instead of dev_spec_attr_group of uart_port structure
Changes in V8:
- Divide this patch from V7's patch based on Greg's comment
Changes in V7:
- Add Documentation
- Change I/F name from rx_int_trig to rx_trig_bytes because the name
rx_int_trig is hard to understand how users specify the value
Changes in V6:
- Move FCR_RX_TRIG_* definition in 8250.h to include/uapi/linux/serial_reg.h,
rename those to UART_FCR_R_TRIG_*, and use UART_FCR_TRIGGER_MASK to
UART_FCR_R_TRIG_BITS()
- Change following function names:
convert_fcr2val() => fcr_get_rxtrig_bytes()
convert_val2rxtrig() => bytes_to_fcr_rxtrig()
- Fix typo in serial8250_do_set_termios()
- Delete the verbose error message pr_info() in bytes_to_fcr_rxtrig()
- Rename *rx_int_trig/rx_trig* to *rxtrig* for several functions or variables
(but UI remains rx_int_trig)
- Change the meaningless variable name 'val' to 'bytes' following functions:
fcr_get_rxtrig_bytes(), bytes_to_fcr_rxtrig(), do_set_rxtrig(),
do_serial8250_set_rxtrig(), and serial8250_set_attr_rxtrig()
- Use up->fcr in order to get rxtrig_bytes instead of rx_trig_raw in
fcr_get_rxtrig_bytes()
- Use conf_type->rxtrig_bytes[0] instead of switch statement for support check
in register_dev_spec_attr_grp()
- Delete the checking whether a user changed FCR or not when minimum buffer
is needed in serial8250_do_set_termios()
Changes in V5.1:
- Fix FCR_RX_TRIG_MAX_STATE definition
Changes in V5:
- Support Tegra, 16650V2, 16654, and 16750
- Store default FCR value to up->fcr when the port is first created
- Add rx_trig_byte[] in uart_config[] for each device and use rx_trig_byte[]
in convert_fcr2val() and convert_val2rxtrig()
Changes in V4:
- Introduce fifo_bug flag in uart_8250_port structure
This is enabled only when parity is enabled and UART_BUG_PARITY is enabled
for up->bugs. If this flag is enabled, user cannot set RX trigger.
- Return -EOPNOTSUPP when it does not support device at convert_fcr2val() and
at convert_val2rxtrig()
- Set the nearest lower RX trigger when users input a meaningless value at
convert_val2rxtrig()
- Check whether p->fcr is existing at serial8250_clear_and_reinit_fifos()
- Set fcr = up->fcr in the begging of serial8250_do_set_termios()
Changes in V3:
- Change I/F from ioctl(2) to sysfs(rx_int_trig)
Changed in V2:
- Use _IOW for TIOCSFIFORTRIG definition
- Pass the interrupt trigger value itself
Signed-off-by: Yoshihiro YUNOMAE <yoshihiro.yunomae.ez@hitachi.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-07-16 01:19:36 +00:00
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unsigned char rxtrig_bytes[UART_FCR_R_TRIG_MAX_STATE];
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2005-04-16 15:20:36 -07:00
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unsigned int flags;
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};
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2021-05-20 11:43:34 +09:30
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#define UART_CAP_FIFO BIT(8) /* UART has FIFO */
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#define UART_CAP_EFR BIT(9) /* UART has EFR */
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#define UART_CAP_SLEEP BIT(10) /* UART has IER sleep */
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#define UART_CAP_AFE BIT(11) /* MCR-based hw flow control */
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#define UART_CAP_UUE BIT(12) /* UART needs IER bit 6 set (Xscale) */
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#define UART_CAP_RTOIE BIT(13) /* UART needs IER bit 4 set (Xscale, Tegra) */
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#define UART_CAP_HFIFO BIT(14) /* UART has a "hidden" FIFO */
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#define UART_CAP_RPM BIT(15) /* Runtime PM is active while idle */
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#define UART_CAP_IRDA BIT(16) /* UART supports IrDA line discipline */
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#define UART_CAP_MINI BIT(17) /* Mini UART on BCM283X family lacks:
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2017-05-19 16:07:23 +01:00
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* STOP PARITY EPAR SPAR WLEN5 WLEN6
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*/
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2022-03-30 12:46:40 +02:00
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#define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */
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2005-04-16 15:20:36 -07:00
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2021-05-20 11:43:34 +09:30
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#define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */
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#define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */
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#define UART_BUG_NOMSR BIT(2) /* UART has buggy MSR status bits (Au1x00) */
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#define UART_BUG_THRE BIT(3) /* UART has buggy THRE reassertion */
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#define UART_BUG_TXRACE BIT(5) /* UART Tx fails to set remote DR */
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2005-06-23 10:43:04 +01:00
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2024-05-06 17:00:59 +03:00
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/* Module parameters */
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#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
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extern unsigned int nr_uarts;
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2005-04-16 15:20:36 -07:00
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#ifdef CONFIG_SERIAL_8250_SHARE_IRQ
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#define SERIAL8250_SHARE_IRQS 1
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#else
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#define SERIAL8250_SHARE_IRQS 0
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#endif
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2024-05-06 17:00:59 +03:00
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extern unsigned int share_irqs;
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extern unsigned int skip_txen_test;
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2016-01-14 16:08:24 +01:00
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#define SERIAL8250_PORT_FLAGS(_base, _irq, _flags) \
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{ \
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.iobase = _base, \
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.irq = _irq, \
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.uartclk = 1843200, \
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.iotype = UPIO_PORT, \
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.flags = UPF_BOOT_AUTOCONF | (_flags), \
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}
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#define SERIAL8250_PORT(_base, _irq) SERIAL8250_PORT_FLAGS(_base, _irq, 0)
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2024-05-06 17:00:59 +03:00
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extern struct uart_driver serial8250_reg;
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void serial8250_register_ports(struct uart_driver *drv, struct device *dev);
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/* Legacy ISA bus related APIs */
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typedef void (*serial8250_isa_config_fn)(int, struct uart_port *, u32 *);
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extern serial8250_isa_config_fn serial8250_isa_config;
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void serial8250_isa_init_ports(void);
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extern struct platform_device *serial8250_isa_devs;
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2024-05-06 17:00:58 +03:00
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extern const struct uart_ops *univ8250_port_base_ops;
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2024-05-06 17:00:59 +03:00
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extern struct uart_ops univ8250_port_ops;
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2016-01-14 16:08:24 +01:00
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2012-03-08 19:12:09 -05:00
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static inline int serial_in(struct uart_8250_port *up, int offset)
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{
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return up->port.serial_in(&up->port, offset);
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}
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static inline void serial_out(struct uart_8250_port *up, int offset, int value)
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{
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up->port.serial_out(&up->port, offset, value);
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}
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2022-06-08 12:54:27 +03:00
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/**
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* serial_lsr_in - Read LSR register and preserve flags across reads
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* @up: uart 8250 port
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*
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* Read LSR register and handle saving non-preserved flags across reads.
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* The flags that are not preserved across reads are stored into
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* up->lsr_saved_flags.
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*
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* Returns LSR value or'ed with the preserved flags (if any).
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*/
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2022-06-24 23:42:05 +03:00
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static inline u16 serial_lsr_in(struct uart_8250_port *up)
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2022-06-08 12:54:27 +03:00
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{
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2022-06-24 23:42:05 +03:00
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u16 lsr = up->lsr_saved_flags;
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2022-06-08 12:54:27 +03:00
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lsr |= serial_in(up, UART_LSR);
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2022-06-24 23:42:06 +03:00
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up->lsr_saved_flags = lsr & up->lsr_save_mask;
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2022-06-08 12:54:27 +03:00
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return lsr;
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}
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2022-04-18 16:27:27 +01:00
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/*
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* For the 16C950
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*/
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static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
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{
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serial_out(up, UART_SCR, offset);
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serial_out(up, UART_ICR, value);
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}
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static unsigned int __maybe_unused serial_icr_read(struct uart_8250_port *up,
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int offset)
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{
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unsigned int value;
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serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
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serial_out(up, UART_SCR, offset);
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value = serial_in(up, UART_ICR);
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serial_icr_write(up, UART_ACR, up->acr);
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return value;
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}
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2012-04-10 14:10:58 -07:00
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void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p);
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2023-05-11 15:10:24 +03:00
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static inline u32 serial_dl_read(struct uart_8250_port *up)
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2012-05-02 21:46:51 +09:00
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{
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return up->dl_read(up);
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}
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2023-05-11 15:10:24 +03:00
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static inline void serial_dl_write(struct uart_8250_port *up, u32 value)
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2012-05-02 21:46:51 +09:00
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{
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up->dl_write(up, value);
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}
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2019-06-17 16:53:20 +03:00
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static inline bool serial8250_set_THRI(struct uart_8250_port *up)
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{
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2023-05-25 11:37:59 +02:06
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/* Port locked to synchronize UART_IER access against the console. */
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lockdep_assert_held_once(&up->port.lock);
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2019-06-17 16:53:20 +03:00
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if (up->ier & UART_IER_THRI)
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return false;
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up->ier |= UART_IER_THRI;
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serial_out(up, UART_IER, up->ier);
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return true;
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}
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static inline bool serial8250_clear_THRI(struct uart_8250_port *up)
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{
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2023-05-25 11:37:59 +02:06
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/* Port locked to synchronize UART_IER access against the console. */
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lockdep_assert_held_once(&up->port.lock);
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2019-06-17 16:53:20 +03:00
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if (!(up->ier & UART_IER_THRI))
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return false;
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up->ier &= ~UART_IER_THRI;
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serial_out(up, UART_IER, up->ier);
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return true;
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}
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2024-05-06 17:00:59 +03:00
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struct uart_8250_port *serial8250_setup_port(int index);
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2014-09-05 21:02:36 +02:00
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struct uart_8250_port *serial8250_get_port(int line);
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2016-11-14 12:26:51 +02:00
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2022-06-24 23:42:08 +03:00
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int serial8250_em485_config(struct uart_port *port, struct ktermios *termios,
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struct serial_rs485 *rs485);
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2025-01-07 22:33:00 +01:06
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void serial8250_em485_start_tx(struct uart_8250_port *p, bool toggle_ier);
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void serial8250_em485_stop_tx(struct uart_8250_port *p, bool toggle_ier);
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2016-02-01 21:09:21 +03:00
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void serial8250_em485_destroy(struct uart_8250_port *p);
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2022-06-06 13:04:01 +03:00
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extern struct serial_rs485 serial8250_em485_supported;
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2014-09-05 21:02:36 +02:00
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2019-06-13 17:45:41 +02:00
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/* MCR <-> TIOCM conversion */
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static inline int serial8250_TIOCM_to_MCR(int tiocm)
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{
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int mcr = 0;
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if (tiocm & TIOCM_RTS)
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mcr |= UART_MCR_RTS;
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if (tiocm & TIOCM_DTR)
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mcr |= UART_MCR_DTR;
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if (tiocm & TIOCM_OUT1)
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mcr |= UART_MCR_OUT1;
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if (tiocm & TIOCM_OUT2)
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mcr |= UART_MCR_OUT2;
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if (tiocm & TIOCM_LOOP)
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mcr |= UART_MCR_LOOP;
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return mcr;
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}
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static inline int serial8250_MCR_to_TIOCM(int mcr)
|
|
|
|
{
|
|
|
|
int tiocm = 0;
|
|
|
|
|
|
|
|
if (mcr & UART_MCR_RTS)
|
|
|
|
tiocm |= TIOCM_RTS;
|
|
|
|
if (mcr & UART_MCR_DTR)
|
|
|
|
tiocm |= TIOCM_DTR;
|
|
|
|
if (mcr & UART_MCR_OUT1)
|
|
|
|
tiocm |= TIOCM_OUT1;
|
|
|
|
if (mcr & UART_MCR_OUT2)
|
|
|
|
tiocm |= TIOCM_OUT2;
|
|
|
|
if (mcr & UART_MCR_LOOP)
|
|
|
|
tiocm |= TIOCM_LOOP;
|
|
|
|
|
|
|
|
return tiocm;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* MSR <-> TIOCM conversion */
|
|
|
|
static inline int serial8250_MSR_to_TIOCM(int msr)
|
|
|
|
{
|
|
|
|
int tiocm = 0;
|
|
|
|
|
|
|
|
if (msr & UART_MSR_DCD)
|
|
|
|
tiocm |= TIOCM_CAR;
|
|
|
|
if (msr & UART_MSR_RI)
|
|
|
|
tiocm |= TIOCM_RNG;
|
|
|
|
if (msr & UART_MSR_DSR)
|
|
|
|
tiocm |= TIOCM_DSR;
|
|
|
|
if (msr & UART_MSR_CTS)
|
|
|
|
tiocm |= TIOCM_CTS;
|
|
|
|
|
|
|
|
return tiocm;
|
|
|
|
}
|
|
|
|
|
2016-05-31 10:59:15 +02:00
|
|
|
static inline void serial8250_out_MCR(struct uart_8250_port *up, int value)
|
|
|
|
{
|
|
|
|
serial_out(up, UART_MCR, value);
|
2019-06-20 08:24:20 +02:00
|
|
|
|
|
|
|
if (up->gpios)
|
|
|
|
mctrl_gpio_set(up->gpios, serial8250_MCR_to_TIOCM(value));
|
2016-05-31 10:59:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline int serial8250_in_MCR(struct uart_8250_port *up)
|
|
|
|
{
|
2019-06-20 08:24:20 +02:00
|
|
|
int mctrl;
|
|
|
|
|
|
|
|
mctrl = serial_in(up, UART_MCR);
|
|
|
|
|
|
|
|
if (up->gpios) {
|
|
|
|
unsigned int mctrl_gpio = 0;
|
|
|
|
|
|
|
|
mctrl_gpio = mctrl_gpio_get_outputs(up->gpios, &mctrl_gpio);
|
|
|
|
mctrl |= serial8250_TIOCM_to_MCR(mctrl_gpio);
|
|
|
|
}
|
|
|
|
|
|
|
|
return mctrl;
|
2016-05-31 10:59:15 +02:00
|
|
|
}
|
|
|
|
|
2012-09-07 19:06:23 +01:00
|
|
|
#ifdef CONFIG_SERIAL_8250_PNP
|
|
|
|
int serial8250_pnp_init(void);
|
|
|
|
void serial8250_pnp_exit(void);
|
|
|
|
#else
|
|
|
|
static inline int serial8250_pnp_init(void) { return 0; }
|
|
|
|
static inline void serial8250_pnp_exit(void) { }
|
|
|
|
#endif
|
|
|
|
|
2024-05-06 17:00:58 +03:00
|
|
|
#ifdef CONFIG_SERIAL_8250_RSA
|
|
|
|
void univ8250_rsa_support(struct uart_ops *ops);
|
2025-06-11 12:02:58 +02:00
|
|
|
void rsa_enable(struct uart_8250_port *up);
|
|
|
|
void rsa_disable(struct uart_8250_port *up);
|
|
|
|
void rsa_autoconfig(struct uart_8250_port *up);
|
|
|
|
void rsa_reset(struct uart_8250_port *up);
|
2024-05-06 17:00:58 +03:00
|
|
|
#else
|
|
|
|
static inline void univ8250_rsa_support(struct uart_ops *ops) { }
|
2025-06-11 12:02:58 +02:00
|
|
|
static inline void rsa_enable(struct uart_8250_port *up) {}
|
|
|
|
static inline void rsa_disable(struct uart_8250_port *up) {}
|
|
|
|
static inline void rsa_autoconfig(struct uart_8250_port *up) {}
|
|
|
|
static inline void rsa_reset(struct uart_8250_port *up) {}
|
2024-05-06 17:00:58 +03:00
|
|
|
#endif
|
|
|
|
|
2016-04-27 10:40:10 +02:00
|
|
|
#ifdef CONFIG_SERIAL_8250_FINTEK
|
|
|
|
int fintek_8250_probe(struct uart_8250_port *uart);
|
|
|
|
#else
|
|
|
|
static inline int fintek_8250_probe(struct uart_8250_port *uart) { return 0; }
|
|
|
|
#endif
|
|
|
|
|
2012-10-03 15:31:58 -07:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
2019-08-06 16:25:42 +02:00
|
|
|
#include <linux/soc/ti/omap1-soc.h>
|
2012-10-03 15:31:58 -07:00
|
|
|
static inline int is_omap1_8250(struct uart_8250_port *pt)
|
|
|
|
{
|
|
|
|
int res;
|
|
|
|
|
|
|
|
switch (pt->port.mapbase) {
|
|
|
|
case OMAP1_UART1_BASE:
|
|
|
|
case OMAP1_UART2_BASE:
|
|
|
|
case OMAP1_UART3_BASE:
|
|
|
|
res = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
res = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int is_omap1510_8250(struct uart_8250_port *pt)
|
|
|
|
{
|
|
|
|
if (!cpu_is_omap1510())
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return is_omap1_8250(pt);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline int is_omap1_8250(struct uart_8250_port *pt)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static inline int is_omap1510_8250(struct uart_8250_port *pt)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
2013-01-10 11:25:11 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_SERIAL_8250_DMA
|
|
|
|
extern int serial8250_tx_dma(struct uart_8250_port *);
|
2025-02-08 12:41:44 +00:00
|
|
|
extern void serial8250_tx_dma_flush(struct uart_8250_port *);
|
2016-04-09 22:14:36 -07:00
|
|
|
extern int serial8250_rx_dma(struct uart_8250_port *);
|
|
|
|
extern void serial8250_rx_dma_flush(struct uart_8250_port *);
|
2013-01-10 11:25:11 +02:00
|
|
|
extern int serial8250_request_dma(struct uart_8250_port *);
|
|
|
|
extern void serial8250_release_dma(struct uart_8250_port *);
|
2022-04-22 20:06:11 +02:00
|
|
|
|
|
|
|
static inline void serial8250_do_prepare_tx_dma(struct uart_8250_port *p)
|
|
|
|
{
|
|
|
|
struct uart_8250_dma *dma = p->dma;
|
|
|
|
|
|
|
|
if (dma->prepare_tx_dma)
|
|
|
|
dma->prepare_tx_dma(p);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void serial8250_do_prepare_rx_dma(struct uart_8250_port *p)
|
|
|
|
{
|
|
|
|
struct uart_8250_dma *dma = p->dma;
|
|
|
|
|
|
|
|
if (dma->prepare_rx_dma)
|
|
|
|
dma->prepare_rx_dma(p);
|
|
|
|
}
|
2023-03-17 13:33:18 +02:00
|
|
|
|
|
|
|
static inline bool serial8250_tx_dma_running(struct uart_8250_port *p)
|
|
|
|
{
|
|
|
|
struct uart_8250_dma *dma = p->dma;
|
|
|
|
|
|
|
|
return dma && dma->tx_running;
|
|
|
|
}
|
2013-01-10 11:25:11 +02:00
|
|
|
#else
|
|
|
|
static inline int serial8250_tx_dma(struct uart_8250_port *p)
|
|
|
|
{
|
|
|
|
return -1;
|
|
|
|
}
|
2025-02-08 12:41:44 +00:00
|
|
|
static inline void serial8250_tx_dma_flush(struct uart_8250_port *p) { }
|
2016-04-09 22:14:36 -07:00
|
|
|
static inline int serial8250_rx_dma(struct uart_8250_port *p)
|
2013-01-10 11:25:11 +02:00
|
|
|
{
|
|
|
|
return -1;
|
|
|
|
}
|
2016-04-09 22:14:36 -07:00
|
|
|
static inline void serial8250_rx_dma_flush(struct uart_8250_port *p) { }
|
2013-01-10 11:25:11 +02:00
|
|
|
static inline int serial8250_request_dma(struct uart_8250_port *p)
|
|
|
|
{
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
static inline void serial8250_release_dma(struct uart_8250_port *p) { }
|
2023-03-17 13:33:18 +02:00
|
|
|
|
|
|
|
static inline bool serial8250_tx_dma_running(struct uart_8250_port *p)
|
|
|
|
{
|
|
|
|
return false;
|
|
|
|
}
|
2013-01-10 11:25:11 +02:00
|
|
|
#endif
|
2015-02-24 14:25:04 -05:00
|
|
|
|
|
|
|
static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
|
|
|
|
{
|
|
|
|
unsigned char status;
|
|
|
|
|
|
|
|
status = serial_in(up, 0x04); /* EXCR2 */
|
|
|
|
#define PRESL(x) ((x) & 0x30)
|
|
|
|
if (PRESL(status) == 0x10) {
|
|
|
|
/* already in high speed mode */
|
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
|
|
|
|
status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
|
|
|
|
serial_out(up, 0x04, status);
|
|
|
|
}
|
|
|
|
return 1;
|
|
|
|
}
|
2015-06-27 09:19:00 -04:00
|
|
|
|
|
|
|
static inline int serial_index(struct uart_port *port)
|
|
|
|
{
|
|
|
|
return port->minor - 64;
|
|
|
|
}
|