2020-04-20 13:50:47 +08:00
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2018-2019 Realtek Corporation
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*/
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#ifndef __RTW8723D_H__
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#define __RTW8723D_H__
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2024-03-11 11:37:05 +01:00
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#include "rtw8723x.h"
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2020-04-20 13:50:54 +08:00
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2022-05-24 10:36:20 -05:00
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extern const struct rtw_chip_info rtw8723d_hw_spec;
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2020-05-04 18:50:04 +08:00
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/* phy status page0 */
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#define GET_PHY_STAT_P0_PWDB(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
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/* phy status page1 */
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#define GET_PHY_STAT_P1_PWDB_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
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#define GET_PHY_STAT_P1_PWDB_B(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
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#define GET_PHY_STAT_P1_RF_MODE(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
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#define GET_PHY_STAT_P1_L_RXSC(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
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#define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
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#define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
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#define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
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#define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
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rtw88: 8723d: Add power tracking
When chip's temperature is changed, RF characters are changed. To keep the
characters to be consistent, 8723d uses thermal meter to assist in
calibrating LCK, IQK, crystal and TX power.
A base thermal value is programmed in efuse, all calibration data in
MP process is based on this thermal value. So we calucate the delta of
thermal value between the base value, and use this delta to reference XTAL
and TX power offset tables to know how much we need to adjust.
For IQK and LCK, driver checks if delta of thermal value is over 8, then
they are triggered.
For crystal adjustment, when delta of thermal value is changed, we check
XTAL tables to get offset of XTAL value. If thermal value is larger than
base value, positive table (_p as suffix) is used. Otherwise, we use
negative table (_n as suffix). Then, we add offset to XTAL default value
programmed in efuse, and write sum value to register.
To compensate TX power, there are two hierarchical tables. First level use
delta of thermal value to access eight tables to yield delta of TX power
index. Then, plus base TX power index to get index of BB swing table
(second level tables) where register value is induced.
BB swing table can't deal with all cases, if index of BB swing table is
over the size of the table. In this case, TX AGC is used to compensate the
remnant part. Assume 'upper' is the upper bound of BB swing table, and
'target' is the desired index. Then, we can illustrate them as
compensation method BB swing TX AGC
------------------- -------- --------------
target > upper upper target - upper
target < 0 0 target
otherwise target 0
For debug purpose, add a column 'rem' to tx_pwr_tbl entry, and it looks
like
path rate pwr base (byr lmt ) rem
A CCK_1M 32(0x20) 34 -2 ( 0 -2) 0
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200512102621.5148-4-yhchuang@realtek.com
2020-05-12 18:26:15 +08:00
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#define RTW_DEF_OFDM_SWING_INDEX 28
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#define RTW_DEF_CCK_SWING_INDEX 28
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2020-05-04 18:50:05 +08:00
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#define CCK_DFIR_NR 3
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2020-04-22 11:46:07 +08:00
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2020-04-20 13:50:47 +08:00
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#endif
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