2025-02-22 09:36:10 +01:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* phylib-internal header
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*/
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#ifndef __PHYLIB_INTERNAL_H
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#define __PHYLIB_INTERNAL_H
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struct phy_device;
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2025-06-12 23:26:04 +02:00
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struct mii_bus;
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2025-02-22 09:36:10 +01:00
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/*
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* phy_supported_speeds - return all speeds currently supported by a PHY device
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*/
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unsigned int phy_supported_speeds(struct phy_device *phy,
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unsigned int *speeds,
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unsigned int size);
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void of_set_phy_supported(struct phy_device *phydev);
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void of_set_phy_eee_broken(struct phy_device *phydev);
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void of_set_phy_timing_role(struct phy_device *phydev);
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int phy_speed_down_core(struct phy_device *phydev);
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void phy_check_downshift(struct phy_device *phydev);
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2025-06-12 23:26:04 +02:00
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int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45,
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int devad, u32 regnum);
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int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45,
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int devad, u32 regnum, u16 val);
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2025-03-03 21:18:46 +01:00
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2025-02-22 09:36:10 +01:00
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int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv);
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#endif /* __PHYLIB_INTERNAL_H */
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