2020-05-13 09:26:15 -04:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef AM65_CPSW_QOS_H_
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#define AM65_CPSW_QOS_H_
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#include <linux/netdevice.h>
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#include <net/pkt_sched.h>
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2023-03-27 14:27:58 +05:30
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struct am65_cpsw_common;
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net: ethernet: ti: am65-cpsw: add mqprio qdisc offload in channel mode
This patch adds MQPRIO Qdisc offload in full 'channel' mode which allows
not only setting up pri:tc mapping, but also configuring TX shapers
(rate-limiting) on external port FIFOs.
The MQPRIO Qdisc offload is expected to work with or without VLAN/priority
tagged packets.
The CPSW external Port FIFO has 8 Priority queues. The rate-limit can be
set for each of these priority queues. Which Priority queue a packet is
assigned to depends on PN_REG_TX_PRI_MAP register which maps header
priority to switch priority.
The header priority of a packet is assigned via the RX_PRI_MAP_REG which
maps packet priority to header priority.
The packet priority is either the VLAN priority (for VLAN tagged packets)
or the thread/channel offset.
For simplicity, we assign the same priority queue to all queues of a
Traffic Class so it can be rate-limited correctly.
Configuration example:
ethtool -L eth1 tx 5
ethtool --set-priv-flags eth1 p0-rx-ptype-rrobin off
tc qdisc add dev eth1 parent root handle 100: mqprio num_tc 3 \
map 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 \
queues 1@0 1@1 1@2 hw 1 mode channel \
shaper bw_rlimit min_rate 0 100mbit 200mbit max_rate 0 101mbit 202mbit
tc qdisc replace dev eth2 handle 100: parent root mqprio num_tc 1 \
map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 queues 1@0 hw 1
ip link add link eth1 name eth1.100 type vlan id 100
ip link set eth1.100 type vlan egress 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
In the above example two ports share the same TX CPPI queue 0 for low
priority traffic. 3 traffic classes are defined for eth1 and mapped to:
TC0 - low priority, TX CPPI queue 0 -> ext Port 1 fifo0, no rate limit
TC1 - prio 2, TX CPPI queue 1 -> ext Port 1 fifo1, CIR=100Mbit/s, EIR=1Mbit/s
TC2 - prio 3, TX CPPI queue 2 -> ext Port 1 fifo2, CIR=200Mbit/s, EIR=2Mbit/s
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-12-19 12:58:03 +02:00
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struct am65_cpsw_port;
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2023-03-27 14:27:58 +05:30
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2020-05-13 09:26:15 -04:00
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struct am65_cpsw_est {
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int buf;
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/* has to be the last one */
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struct tc_taprio_qopt_offload taprio;
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};
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net: ethernet: ti: am65-cpsw: add mqprio qdisc offload in channel mode
This patch adds MQPRIO Qdisc offload in full 'channel' mode which allows
not only setting up pri:tc mapping, but also configuring TX shapers
(rate-limiting) on external port FIFOs.
The MQPRIO Qdisc offload is expected to work with or without VLAN/priority
tagged packets.
The CPSW external Port FIFO has 8 Priority queues. The rate-limit can be
set for each of these priority queues. Which Priority queue a packet is
assigned to depends on PN_REG_TX_PRI_MAP register which maps header
priority to switch priority.
The header priority of a packet is assigned via the RX_PRI_MAP_REG which
maps packet priority to header priority.
The packet priority is either the VLAN priority (for VLAN tagged packets)
or the thread/channel offset.
For simplicity, we assign the same priority queue to all queues of a
Traffic Class so it can be rate-limited correctly.
Configuration example:
ethtool -L eth1 tx 5
ethtool --set-priv-flags eth1 p0-rx-ptype-rrobin off
tc qdisc add dev eth1 parent root handle 100: mqprio num_tc 3 \
map 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 \
queues 1@0 1@1 1@2 hw 1 mode channel \
shaper bw_rlimit min_rate 0 100mbit 200mbit max_rate 0 101mbit 202mbit
tc qdisc replace dev eth2 handle 100: parent root mqprio num_tc 1 \
map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 queues 1@0 hw 1
ip link add link eth1 name eth1.100 type vlan id 100
ip link set eth1.100 type vlan egress 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
In the above example two ports share the same TX CPPI queue 0 for low
priority traffic. 3 traffic classes are defined for eth1 and mapped to:
TC0 - low priority, TX CPPI queue 0 -> ext Port 1 fifo0, no rate limit
TC1 - prio 2, TX CPPI queue 1 -> ext Port 1 fifo1, CIR=100Mbit/s, EIR=1Mbit/s
TC2 - prio 3, TX CPPI queue 2 -> ext Port 1 fifo2, CIR=200Mbit/s, EIR=2Mbit/s
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-12-19 12:58:03 +02:00
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struct am65_cpsw_mqprio {
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struct tc_mqprio_qopt_offload mqprio_hw;
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u64 max_rate_total;
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bool shaper_en;
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};
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2023-12-19 12:58:04 +02:00
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struct am65_cpsw_iet {
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u8 preemptible_tcs;
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u32 original_max_blks;
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int verify_time_ms;
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};
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2022-04-12 13:29:28 +03:00
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struct am65_cpsw_ale_ratelimit {
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unsigned long cookie;
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u64 rate_packet_ps;
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};
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2020-05-13 09:26:15 -04:00
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struct am65_cpsw_qos {
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struct am65_cpsw_est *est_admin;
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struct am65_cpsw_est *est_oper;
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ktime_t link_down_time;
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int link_speed;
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net: ethernet: ti: am65-cpsw: add mqprio qdisc offload in channel mode
This patch adds MQPRIO Qdisc offload in full 'channel' mode which allows
not only setting up pri:tc mapping, but also configuring TX shapers
(rate-limiting) on external port FIFOs.
The MQPRIO Qdisc offload is expected to work with or without VLAN/priority
tagged packets.
The CPSW external Port FIFO has 8 Priority queues. The rate-limit can be
set for each of these priority queues. Which Priority queue a packet is
assigned to depends on PN_REG_TX_PRI_MAP register which maps header
priority to switch priority.
The header priority of a packet is assigned via the RX_PRI_MAP_REG which
maps packet priority to header priority.
The packet priority is either the VLAN priority (for VLAN tagged packets)
or the thread/channel offset.
For simplicity, we assign the same priority queue to all queues of a
Traffic Class so it can be rate-limited correctly.
Configuration example:
ethtool -L eth1 tx 5
ethtool --set-priv-flags eth1 p0-rx-ptype-rrobin off
tc qdisc add dev eth1 parent root handle 100: mqprio num_tc 3 \
map 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 \
queues 1@0 1@1 1@2 hw 1 mode channel \
shaper bw_rlimit min_rate 0 100mbit 200mbit max_rate 0 101mbit 202mbit
tc qdisc replace dev eth2 handle 100: parent root mqprio num_tc 1 \
map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 queues 1@0 hw 1
ip link add link eth1 name eth1.100 type vlan id 100
ip link set eth1.100 type vlan egress 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
In the above example two ports share the same TX CPPI queue 0 for low
priority traffic. 3 traffic classes are defined for eth1 and mapped to:
TC0 - low priority, TX CPPI queue 0 -> ext Port 1 fifo0, no rate limit
TC1 - prio 2, TX CPPI queue 1 -> ext Port 1 fifo1, CIR=100Mbit/s, EIR=1Mbit/s
TC2 - prio 3, TX CPPI queue 2 -> ext Port 1 fifo2, CIR=200Mbit/s, EIR=2Mbit/s
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-12-19 12:58:03 +02:00
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struct am65_cpsw_mqprio mqprio;
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2023-12-19 12:58:04 +02:00
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struct am65_cpsw_iet iet;
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2022-04-12 13:29:28 +03:00
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struct am65_cpsw_ale_ratelimit ale_bc_ratelimit;
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struct am65_cpsw_ale_ratelimit ale_mc_ratelimit;
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2020-05-13 09:26:15 -04:00
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};
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2023-12-19 12:58:02 +02:00
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#define AM65_CPSW_REG_CTL 0x004
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#define AM65_CPSW_PN_REG_CTL 0x004
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#define AM65_CPSW_PN_REG_FIFO_STATUS 0x050
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#define AM65_CPSW_PN_REG_EST_CTL 0x060
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#define AM65_CPSW_PN_REG_PRI_CIR(pri) (0x140 + 4 * (pri))
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net: ethernet: ti: am65-cpsw: add mqprio qdisc offload in channel mode
This patch adds MQPRIO Qdisc offload in full 'channel' mode which allows
not only setting up pri:tc mapping, but also configuring TX shapers
(rate-limiting) on external port FIFOs.
The MQPRIO Qdisc offload is expected to work with or without VLAN/priority
tagged packets.
The CPSW external Port FIFO has 8 Priority queues. The rate-limit can be
set for each of these priority queues. Which Priority queue a packet is
assigned to depends on PN_REG_TX_PRI_MAP register which maps header
priority to switch priority.
The header priority of a packet is assigned via the RX_PRI_MAP_REG which
maps packet priority to header priority.
The packet priority is either the VLAN priority (for VLAN tagged packets)
or the thread/channel offset.
For simplicity, we assign the same priority queue to all queues of a
Traffic Class so it can be rate-limited correctly.
Configuration example:
ethtool -L eth1 tx 5
ethtool --set-priv-flags eth1 p0-rx-ptype-rrobin off
tc qdisc add dev eth1 parent root handle 100: mqprio num_tc 3 \
map 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 \
queues 1@0 1@1 1@2 hw 1 mode channel \
shaper bw_rlimit min_rate 0 100mbit 200mbit max_rate 0 101mbit 202mbit
tc qdisc replace dev eth2 handle 100: parent root mqprio num_tc 1 \
map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 queues 1@0 hw 1
ip link add link eth1 name eth1.100 type vlan id 100
ip link set eth1.100 type vlan egress 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
In the above example two ports share the same TX CPPI queue 0 for low
priority traffic. 3 traffic classes are defined for eth1 and mapped to:
TC0 - low priority, TX CPPI queue 0 -> ext Port 1 fifo0, no rate limit
TC1 - prio 2, TX CPPI queue 1 -> ext Port 1 fifo1, CIR=100Mbit/s, EIR=1Mbit/s
TC2 - prio 3, TX CPPI queue 2 -> ext Port 1 fifo2, CIR=200Mbit/s, EIR=2Mbit/s
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-12-19 12:58:03 +02:00
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#define AM65_CPSW_P0_REG_PRI_EIR(pri) (0x160 + 4 * (pri))
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#define AM65_CPSW_PN_REG_CTL 0x004
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#define AM65_CPSW_PN_REG_TX_PRI_MAP 0x018
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#define AM65_CPSW_PN_REG_RX_PRI_MAP 0x020
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#define AM65_CPSW_PN_REG_FIFO_STATUS 0x050
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#define AM65_CPSW_PN_REG_EST_CTL 0x060
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#define AM65_CPSW_PN_REG_PRI_CIR(pri) (0x140 + 4 * (pri))
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#define AM65_CPSW_PN_REG_PRI_EIR(pri) (0x160 + 4 * (pri))
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2023-12-19 12:58:02 +02:00
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/* AM65_CPSW_REG_CTL register fields */
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#define AM65_CPSW_CTL_EST_EN BIT(18)
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/* AM65_CPSW_PN_REG_CTL register fields */
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#define AM65_CPSW_PN_CTL_EST_PORT_EN BIT(17)
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/* AM65_CPSW_PN_REG_EST_CTL register fields */
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#define AM65_CPSW_PN_EST_ONEBUF BIT(0)
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#define AM65_CPSW_PN_EST_BUFSEL BIT(1)
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#define AM65_CPSW_PN_EST_TS_EN BIT(2)
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#define AM65_CPSW_PN_EST_TS_FIRST BIT(3)
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#define AM65_CPSW_PN_EST_ONEPRI BIT(4)
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#define AM65_CPSW_PN_EST_TS_PRI_MSK GENMASK(7, 5)
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/* AM65_CPSW_PN_REG_FIFO_STATUS register fields */
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#define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK GENMASK(7, 0)
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#define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK GENMASK(15, 8)
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#define AM65_CPSW_PN_FST_EST_CNT_ERR BIT(16)
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#define AM65_CPSW_PN_FST_EST_ADD_ERR BIT(17)
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#define AM65_CPSW_PN_FST_EST_BUFACT BIT(18)
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/* EST FETCH COMMAND RAM */
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#define AM65_CPSW_FETCH_RAM_CMD_NUM 0x80
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#define AM65_CPSW_FETCH_CNT_MSK GENMASK(21, 8)
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#define AM65_CPSW_FETCH_CNT_MAX (AM65_CPSW_FETCH_CNT_MSK >> 8)
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#define AM65_CPSW_FETCH_CNT_OFFSET 8
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#define AM65_CPSW_FETCH_ALLOW_MSK GENMASK(7, 0)
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#define AM65_CPSW_FETCH_ALLOW_MAX AM65_CPSW_FETCH_ALLOW_MSK
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net: ethernet: ti: am65-cpsw: add mqprio qdisc offload in channel mode
This patch adds MQPRIO Qdisc offload in full 'channel' mode which allows
not only setting up pri:tc mapping, but also configuring TX shapers
(rate-limiting) on external port FIFOs.
The MQPRIO Qdisc offload is expected to work with or without VLAN/priority
tagged packets.
The CPSW external Port FIFO has 8 Priority queues. The rate-limit can be
set for each of these priority queues. Which Priority queue a packet is
assigned to depends on PN_REG_TX_PRI_MAP register which maps header
priority to switch priority.
The header priority of a packet is assigned via the RX_PRI_MAP_REG which
maps packet priority to header priority.
The packet priority is either the VLAN priority (for VLAN tagged packets)
or the thread/channel offset.
For simplicity, we assign the same priority queue to all queues of a
Traffic Class so it can be rate-limited correctly.
Configuration example:
ethtool -L eth1 tx 5
ethtool --set-priv-flags eth1 p0-rx-ptype-rrobin off
tc qdisc add dev eth1 parent root handle 100: mqprio num_tc 3 \
map 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 \
queues 1@0 1@1 1@2 hw 1 mode channel \
shaper bw_rlimit min_rate 0 100mbit 200mbit max_rate 0 101mbit 202mbit
tc qdisc replace dev eth2 handle 100: parent root mqprio num_tc 1 \
map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 queues 1@0 hw 1
ip link add link eth1 name eth1.100 type vlan id 100
ip link set eth1.100 type vlan egress 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
In the above example two ports share the same TX CPPI queue 0 for low
priority traffic. 3 traffic classes are defined for eth1 and mapped to:
TC0 - low priority, TX CPPI queue 0 -> ext Port 1 fifo0, no rate limit
TC1 - prio 2, TX CPPI queue 1 -> ext Port 1 fifo1, CIR=100Mbit/s, EIR=1Mbit/s
TC2 - prio 3, TX CPPI queue 2 -> ext Port 1 fifo2, CIR=200Mbit/s, EIR=2Mbit/s
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-12-19 12:58:03 +02:00
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/* number of priority queues per port FIFO */
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#define AM65_CPSW_PN_FIFO_PRIO_NUM 8
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2023-12-19 12:57:59 +02:00
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#if IS_ENABLED(CONFIG_TI_AM65_CPSW_QOS)
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2020-05-13 09:26:15 -04:00
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int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
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void *type_data);
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void am65_cpsw_qos_link_up(struct net_device *ndev, int link_speed);
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void am65_cpsw_qos_link_down(struct net_device *ndev);
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2023-03-27 14:27:58 +05:30
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int am65_cpsw_qos_ndo_tx_p0_set_maxrate(struct net_device *ndev, int queue, u32 rate_mbps);
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void am65_cpsw_qos_tx_p0_rate_init(struct am65_cpsw_common *common);
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2023-12-19 12:58:04 +02:00
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void am65_cpsw_iet_commit_preemptible_tcs(struct am65_cpsw_port *port);
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void am65_cpsw_iet_common_enable(struct am65_cpsw_common *common);
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2023-12-19 12:57:58 +02:00
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#else
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static inline int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev,
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enum tc_setup_type type,
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void *type_data)
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{
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return -EOPNOTSUPP;
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}
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static inline void am65_cpsw_qos_link_up(struct net_device *ndev,
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int link_speed)
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{ }
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static inline void am65_cpsw_qos_link_down(struct net_device *ndev)
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{ }
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static inline int am65_cpsw_qos_ndo_tx_p0_set_maxrate(struct net_device *ndev,
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int queue,
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u32 rate_mbps)
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{
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return 0;
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}
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static inline void am65_cpsw_qos_tx_p0_rate_init(struct am65_cpsw_common *common)
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{ }
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2023-12-19 12:58:04 +02:00
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static inline void am65_cpsw_iet_commit_preemptible_tcs(struct am65_cpsw_port *port)
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{ }
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static inline void am65_cpsw_iet_common_enable(struct am65_cpsw_common *common)
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{ }
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2023-12-19 12:57:58 +02:00
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#endif
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2020-05-13 09:26:15 -04:00
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2023-12-19 12:58:04 +02:00
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#define AM65_CPSW_REG_CTL 0x004
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#define AM65_CPSW_PN_REG_CTL 0x004
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#define AM65_CPSW_PN_REG_MAX_BLKS 0x008
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#define AM65_CPSW_PN_REG_TX_PRI_MAP 0x018
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#define AM65_CPSW_PN_REG_RX_PRI_MAP 0x020
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#define AM65_CPSW_PN_REG_IET_CTRL 0x040
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#define AM65_CPSW_PN_REG_IET_STATUS 0x044
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#define AM65_CPSW_PN_REG_IET_VERIFY 0x048
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#define AM65_CPSW_PN_REG_FIFO_STATUS 0x050
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#define AM65_CPSW_PN_REG_EST_CTL 0x060
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#define AM65_CPSW_PN_REG_PRI_CIR(pri) (0x140 + 4 * (pri))
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#define AM65_CPSW_PN_REG_PRI_EIR(pri) (0x160 + 4 * (pri))
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/* AM65_CPSW_REG_CTL register fields */
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#define AM65_CPSW_CTL_IET_EN BIT(17)
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#define AM65_CPSW_CTL_EST_EN BIT(18)
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/* AM65_CPSW_PN_REG_CTL register fields */
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#define AM65_CPSW_PN_CTL_IET_PORT_EN BIT(16)
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#define AM65_CPSW_PN_CTL_EST_PORT_EN BIT(17)
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/* AM65_CPSW_PN_REG_EST_CTL register fields */
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#define AM65_CPSW_PN_EST_ONEBUF BIT(0)
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#define AM65_CPSW_PN_EST_BUFSEL BIT(1)
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#define AM65_CPSW_PN_EST_TS_EN BIT(2)
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#define AM65_CPSW_PN_EST_TS_FIRST BIT(3)
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#define AM65_CPSW_PN_EST_ONEPRI BIT(4)
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#define AM65_CPSW_PN_EST_TS_PRI_MSK GENMASK(7, 5)
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/* AM65_CPSW_PN_REG_IET_CTRL register fields */
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#define AM65_CPSW_PN_IET_MAC_PENABLE BIT(0)
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#define AM65_CPSW_PN_IET_MAC_DISABLEVERIFY BIT(2)
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#define AM65_CPSW_PN_IET_MAC_LINKFAIL BIT(3)
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#define AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK GENMASK(10, 8)
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#define AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_OFFSET 8
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#define AM65_CPSW_PN_IET_MAC_PREMPT_MASK GENMASK(23, 16)
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#define AM65_CPSW_PN_IET_MAC_PREMPT_OFFSET 16
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#define AM65_CPSW_PN_IET_MAC_SET_ADDFRAGSIZE(n) (((n) << AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_OFFSET) & \
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AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK)
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#define AM65_CPSW_PN_IET_MAC_GET_ADDFRAGSIZE(n) (((n) & AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK) >> \
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AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_OFFSET)
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#define AM65_CPSW_PN_IET_MAC_SET_PREEMPT(n) (((n) << AM65_CPSW_PN_IET_MAC_PREMPT_OFFSET) & \
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AM65_CPSW_PN_IET_MAC_PREMPT_MASK)
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#define AM65_CPSW_PN_IET_MAC_GET_PREEMPT(n) (((n) & AM65_CPSW_PN_IET_MAC_PREMPT_MASK) >> \
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AM65_CPSW_PN_IET_MAC_PREMPT_OFFSET)
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/* AM65_CPSW_PN_REG_IET_STATUS register fields */
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#define AM65_CPSW_PN_MAC_STATUS GENMASK(3, 0)
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#define AM65_CPSW_PN_MAC_VERIFIED BIT(0)
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#define AM65_CPSW_PN_MAC_VERIFY_FAIL BIT(1)
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#define AM65_CPSW_PN_MAC_RESPOND_ERR BIT(2)
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#define AM65_CPSW_PN_MAC_VERIFY_ERR BIT(3)
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/* AM65_CPSW_PN_REG_IET_VERIFY register fields */
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#define AM65_CPSW_PN_MAC_VERIFY_CNT_MASK GENMASK(23, 0)
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#define AM65_CPSW_PN_MAC_GET_VERIFY_CNT(n) ((n) & AM65_CPSW_PN_MAC_VERIFY_CNT_MASK)
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/* 10 msec converted to NSEC */
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#define AM65_CPSW_IET_VERIFY_CNT_MS (10)
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#define AM65_CPSW_IET_VERIFY_CNT_NS (AM65_CPSW_IET_VERIFY_CNT_MS * \
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NSEC_PER_MSEC)
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/* AM65_CPSW_PN_REG_FIFO_STATUS register fields */
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#define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK GENMASK(7, 0)
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#define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK GENMASK(15, 8)
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#define AM65_CPSW_PN_FST_EST_CNT_ERR BIT(16)
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#define AM65_CPSW_PN_FST_EST_ADD_ERR BIT(17)
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#define AM65_CPSW_PN_FST_EST_BUFACT BIT(18)
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/* EST FETCH COMMAND RAM */
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#define AM65_CPSW_FETCH_RAM_CMD_NUM 0x80
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#define AM65_CPSW_FETCH_CNT_MSK GENMASK(21, 8)
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#define AM65_CPSW_FETCH_CNT_MAX (AM65_CPSW_FETCH_CNT_MSK >> 8)
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#define AM65_CPSW_FETCH_CNT_OFFSET 8
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#define AM65_CPSW_FETCH_ALLOW_MSK GENMASK(7, 0)
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#define AM65_CPSW_FETCH_ALLOW_MAX AM65_CPSW_FETCH_ALLOW_MSK
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/* AM65_CPSW_PN_REG_MAX_BLKS fields for IET and No IET cases */
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/* 7 blocks for pn_rx_max_blks, 13 for pn_tx_max_blks*/
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#define AM65_CPSW_PN_TX_RX_MAX_BLKS_IET 0xD07
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/* Slave IET Stats. register offsets */
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#define AM65_CPSW_STATN_IET_RX_ASSEMBLY_ERROR 0x140
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#define AM65_CPSW_STATN_IET_RX_ASSEMBLY_OK 0x144
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#define AM65_CPSW_STATN_IET_RX_SMD_ERROR 0x148
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#define AM65_CPSW_STATN_IET_RX_FRAG 0x14c
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#define AM65_CPSW_STATN_IET_TX_HOLD 0x150
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#define AM65_CPSW_STATN_IET_TX_FRAG 0x154
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/* number of priority queues per port FIFO */
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#define AM65_CPSW_PN_FIFO_PRIO_NUM 8
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2020-05-13 09:26:15 -04:00
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#endif /* AM65_CPSW_QOS_H_ */
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