enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
|
|
|
/* Copyright 2017-2019 NXP */
|
|
|
|
|
|
2024-10-01 15:35:57 -04:00
|
|
|
#include <linux/unaligned.h>
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
#include <linux/module.h>
|
2024-10-30 17:39:16 +08:00
|
|
|
#include <linux/of.h>
|
net: enetc: add a mini driver for the Integrated Endpoint Register Block
The NXP ENETC is a 4-port Ethernet controller which 'smells' to
operating systems like 4 distinct PCIe PFs with SR-IOV, each PF having
its own driver instance, but in fact there are some hardware resources
which are shared between all ports, like for example the 256 KB SRAM
FIFO between the MACs and the Host Transfer Agent which DMAs frames to
DRAM.
To hide the stuff that cannot be neatly exposed per port, the hardware
designers came up with this idea of having a dedicated register block
which is supposed to be populated by the bootloader, and contains
everything configuration-related: MAC addresses, FIFO partitioning, etc.
When a port is reset using PCIe Function Level Reset, its defaults are
transferred from the IERB configuration. Most of the time, the settings
made through the IERB are read-only in the port's memory space (if they
are even visible), so they cannot be modified at runtime.
Linux doesn't have any advanced FIFO partitioning requirements at all,
but when reading through the hardware manual, it became clear that, even
though there are many good 'recommendations' for default values, many of
them were not actually put in practice on LS1028A. So we end up with a
default configuration that:
(a) does not have enough TX and RX byte credits to support the max MTU
of 9600 (which the Linux driver claims already) properly (at full speed)
(b) allows the FIFO to be overrun with RX traffic, potentially
overwriting internal data structures.
The last part sounds a bit catastrophic, but it isn't. Frames are
supposed to transit the FIFO for a very short time, but they can
actually accumulate there under 2 conditions:
(a) there is very severe congestion on DRAM memory, or
(b) the RX rings visible to the operating system were configured for
lossless operation, and they just ran out of free buffers to copy
the frame to. This is what is used to put backpressure onto the MAC
with flow control.
So since ENETC has not supported flow control thus far, RX FIFO overruns
were never seen with Linux. But with the addition of flow control, we
should configure some registers to prevent this from happening. What we
are trying to protect against are bad actors which continue to send us
traffic despite the fact that we have signaled a PAUSE condition. Of
course we can't be lossless in that case, but it is best to configure
the FIFO to do tail dropping rather than letting it overrun.
So in a nutshell, this driver is a fixup for all the IERB default values
that should have been but aren't.
The IERB configuration needs to be done _before_ the PFs are enabled.
So every PF searches for the presence of the "fsl,ls1028a-enetc-ierb"
node in the device tree, and if it finds it, it "registers" with the
IERB, which means that it requests the IERB to fix up its default
values. This is done through -EPROBE_DEFER. The IERB driver is part of
the fsl_enetc module, but is technically a platform driver, since the
IERB is a good old fashioned MMIO region, as opposed to ENETC ports
which pretend to be PCIe devices.
The driver was already configuring ENETC_PTXMBAR (FIFO allocation for
TX) because due to an omission, TXMBAR is a read/write register in the
PF memory space. But the manual is quite clear that the formula for this
should depend upon the TX byte credits (TXBCR). In turn, the TX byte
credits are only readable/writable through the IERB. So if we want to
ensure that the TXBCR register also has a value that is correct and in
line with TXMBAR, there is simply no way this can be done from the PF
driver, access to the IERB is needed.
I could have modified U-Boot to fix up the IERB values, but that is
quite undesirable, as old U-Boot versions are likely to be floating
around for quite some time from now.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-17 02:42:23 +03:00
|
|
|
#include <linux/of_platform.h>
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
#include <linux/of_net.h>
|
2021-12-28 21:03:06 -08:00
|
|
|
#include <linux/pcs-lynx.h>
|
net: enetc: add a mini driver for the Integrated Endpoint Register Block
The NXP ENETC is a 4-port Ethernet controller which 'smells' to
operating systems like 4 distinct PCIe PFs with SR-IOV, each PF having
its own driver instance, but in fact there are some hardware resources
which are shared between all ports, like for example the 256 KB SRAM
FIFO between the MACs and the Host Transfer Agent which DMAs frames to
DRAM.
To hide the stuff that cannot be neatly exposed per port, the hardware
designers came up with this idea of having a dedicated register block
which is supposed to be populated by the bootloader, and contains
everything configuration-related: MAC addresses, FIFO partitioning, etc.
When a port is reset using PCIe Function Level Reset, its defaults are
transferred from the IERB configuration. Most of the time, the settings
made through the IERB are read-only in the port's memory space (if they
are even visible), so they cannot be modified at runtime.
Linux doesn't have any advanced FIFO partitioning requirements at all,
but when reading through the hardware manual, it became clear that, even
though there are many good 'recommendations' for default values, many of
them were not actually put in practice on LS1028A. So we end up with a
default configuration that:
(a) does not have enough TX and RX byte credits to support the max MTU
of 9600 (which the Linux driver claims already) properly (at full speed)
(b) allows the FIFO to be overrun with RX traffic, potentially
overwriting internal data structures.
The last part sounds a bit catastrophic, but it isn't. Frames are
supposed to transit the FIFO for a very short time, but they can
actually accumulate there under 2 conditions:
(a) there is very severe congestion on DRAM memory, or
(b) the RX rings visible to the operating system were configured for
lossless operation, and they just ran out of free buffers to copy
the frame to. This is what is used to put backpressure onto the MAC
with flow control.
So since ENETC has not supported flow control thus far, RX FIFO overruns
were never seen with Linux. But with the addition of flow control, we
should configure some registers to prevent this from happening. What we
are trying to protect against are bad actors which continue to send us
traffic despite the fact that we have signaled a PAUSE condition. Of
course we can't be lossless in that case, but it is best to configure
the FIFO to do tail dropping rather than letting it overrun.
So in a nutshell, this driver is a fixup for all the IERB default values
that should have been but aren't.
The IERB configuration needs to be done _before_ the PFs are enabled.
So every PF searches for the presence of the "fsl,ls1028a-enetc-ierb"
node in the device tree, and if it finds it, it "registers" with the
IERB, which means that it requests the IERB to fix up its default
values. This is done through -EPROBE_DEFER. The IERB driver is part of
the fsl_enetc module, but is technically a platform driver, since the
IERB is a good old fashioned MMIO region, as opposed to ENETC ports
which pretend to be PCIe devices.
The driver was already configuring ENETC_PTXMBAR (FIFO allocation for
TX) because due to an omission, TXMBAR is a read/write register in the
PF memory space. But the manual is quite clear that the formula for this
should depend upon the TX byte credits (TXBCR). In turn, the TX byte
credits are only readable/writable through the IERB. So if we want to
ensure that the TXBCR register also has a value that is correct and in
line with TXMBAR, there is simply no way this can be done from the PF
driver, access to the IERB is needed.
I could have modified U-Boot to fix up the IERB values, but that is
quite undesirable, as old U-Boot versions are likely to be floating
around for quite some time from now.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-17 02:42:23 +03:00
|
|
|
#include "enetc_ierb.h"
|
2024-10-30 17:39:16 +08:00
|
|
|
#include "enetc_pf_common.h"
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
|
|
|
|
#define ENETC_DRV_NAME_STR "ENETC PF driver"
|
|
|
|
|
|
2024-10-30 17:39:17 +08:00
|
|
|
static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
{
|
|
|
|
|
u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
|
|
|
|
|
u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
|
|
|
|
|
|
2021-06-04 15:42:12 +02:00
|
|
|
put_unaligned_le32(upper, addr);
|
|
|
|
|
put_unaligned_le16(lower, addr + 4);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-30 17:39:17 +08:00
|
|
|
static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
|
|
|
|
|
const u8 *addr)
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
{
|
2021-06-04 15:42:12 +02:00
|
|
|
u32 upper = get_unaligned_le32(addr);
|
|
|
|
|
u16 lower = get_unaligned_le16(addr + 4);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
|
|
|
|
__raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
|
|
|
|
|
__raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
|
|
|
|
|
}
|
|
|
|
|
|
2024-10-30 17:39:17 +08:00
|
|
|
static struct phylink_pcs *enetc_pf_create_pcs(struct enetc_pf *pf,
|
|
|
|
|
struct mii_bus *bus)
|
|
|
|
|
{
|
|
|
|
|
return lynx_pcs_create_mdiodev(bus, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_pf_destroy_pcs(struct phylink_pcs *pcs)
|
|
|
|
|
{
|
|
|
|
|
lynx_pcs_destroy(pcs);
|
|
|
|
|
}
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
|
|
|
|
|
{
|
|
|
|
|
u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
|
|
|
|
|
|
|
|
|
|
val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
|
|
|
|
|
enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
|
|
|
|
|
{
|
|
|
|
|
pf->vlan_promisc_simap |= BIT(si_idx);
|
|
|
|
|
enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
|
|
|
|
|
{
|
|
|
|
|
pf->vlan_promisc_simap &= ~BIT(si_idx);
|
|
|
|
|
enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
|
|
|
|
|
{
|
|
|
|
|
u32 val = 0;
|
|
|
|
|
|
|
|
|
|
if (vlan)
|
|
|
|
|
val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
|
|
|
|
|
|
|
|
|
|
enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
|
|
|
|
|
const unsigned char *addr)
|
|
|
|
|
{
|
|
|
|
|
/* add exact match addr */
|
|
|
|
|
ether_addr_copy(filter->mac_addr, addr);
|
|
|
|
|
filter->mac_addr_cnt++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
|
|
|
|
|
{
|
|
|
|
|
bool err = si->errata & ENETC_ERR_UCMCSWP;
|
|
|
|
|
|
|
|
|
|
if (type == UC) {
|
|
|
|
|
enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
|
|
|
|
|
enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
|
|
|
|
|
} else { /* MC */
|
|
|
|
|
enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
|
|
|
|
|
enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
|
2021-03-24 17:44:55 +02:00
|
|
|
unsigned long hash)
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
{
|
|
|
|
|
bool err = si->errata & ENETC_ERR_UCMCSWP;
|
|
|
|
|
|
|
|
|
|
if (type == UC) {
|
2021-03-24 17:44:55 +02:00
|
|
|
enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),
|
|
|
|
|
lower_32_bits(hash));
|
|
|
|
|
enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),
|
|
|
|
|
upper_32_bits(hash));
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
} else { /* MC */
|
2021-03-24 17:44:55 +02:00
|
|
|
enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),
|
|
|
|
|
lower_32_bits(hash));
|
|
|
|
|
enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),
|
|
|
|
|
upper_32_bits(hash));
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_sync_mac_filters(struct enetc_pf *pf)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_mac_filter *f = pf->mac_filter;
|
|
|
|
|
struct enetc_si *si = pf->si;
|
|
|
|
|
int i, pos;
|
|
|
|
|
|
|
|
|
|
pos = EMETC_MAC_ADDR_FILT_RES;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < MADDR_TYPE; i++, f++) {
|
|
|
|
|
bool em = (f->mac_addr_cnt == 1) && (i == UC);
|
|
|
|
|
bool clear = !f->mac_addr_cnt;
|
|
|
|
|
|
|
|
|
|
if (clear) {
|
|
|
|
|
if (i == UC)
|
|
|
|
|
enetc_clear_mac_flt_entry(si, pos);
|
|
|
|
|
|
|
|
|
|
enetc_clear_mac_ht_flt(si, 0, i);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* exact match filter */
|
|
|
|
|
if (em) {
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
enetc_clear_mac_ht_flt(si, 0, UC);
|
|
|
|
|
|
|
|
|
|
err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
|
|
|
|
|
BIT(0));
|
|
|
|
|
if (!err)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
/* fallback to HT filtering */
|
|
|
|
|
dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
|
|
|
|
|
err);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* hash table filter, clear EM filter for UC entries */
|
|
|
|
|
if (i == UC)
|
|
|
|
|
enetc_clear_mac_flt_entry(si, pos);
|
|
|
|
|
|
2021-03-24 17:44:55 +02:00
|
|
|
enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_pf_set_rx_mode(struct net_device *ndev)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(priv->si);
|
|
|
|
|
struct enetc_hw *hw = &priv->si->hw;
|
|
|
|
|
bool uprom = false, mprom = false;
|
|
|
|
|
struct enetc_mac_filter *filter;
|
|
|
|
|
struct netdev_hw_addr *ha;
|
|
|
|
|
u32 psipmr = 0;
|
|
|
|
|
bool em;
|
|
|
|
|
|
|
|
|
|
if (ndev->flags & IFF_PROMISC) {
|
|
|
|
|
/* enable promisc mode for SI0 (PF) */
|
|
|
|
|
psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
|
|
|
|
|
uprom = true;
|
|
|
|
|
mprom = true;
|
|
|
|
|
} else if (ndev->flags & IFF_ALLMULTI) {
|
|
|
|
|
/* enable multi cast promisc mode for SI0 (PF) */
|
|
|
|
|
psipmr = ENETC_PSIPMR_SET_MP(0);
|
|
|
|
|
mprom = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* first 2 filter entries belong to PF */
|
|
|
|
|
if (!uprom) {
|
|
|
|
|
/* Update unicast filters */
|
|
|
|
|
filter = &pf->mac_filter[UC];
|
|
|
|
|
enetc_reset_mac_addr_filter(filter);
|
|
|
|
|
|
|
|
|
|
em = (netdev_uc_count(ndev) == 1);
|
|
|
|
|
netdev_for_each_uc_addr(ha, ndev) {
|
|
|
|
|
if (em) {
|
|
|
|
|
enetc_add_mac_addr_em_filter(filter, ha->addr);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
enetc_add_mac_addr_ht_filter(filter, ha->addr);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!mprom) {
|
|
|
|
|
/* Update multicast filters */
|
|
|
|
|
filter = &pf->mac_filter[MC];
|
|
|
|
|
enetc_reset_mac_addr_filter(filter);
|
|
|
|
|
|
|
|
|
|
netdev_for_each_mc_addr(ha, ndev) {
|
|
|
|
|
if (!is_multicast_ether_addr(ha->addr))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
enetc_add_mac_addr_ht_filter(filter, ha->addr);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!uprom || !mprom)
|
|
|
|
|
/* update PF entries */
|
|
|
|
|
enetc_sync_mac_filters(pf);
|
|
|
|
|
|
|
|
|
|
psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
|
|
|
|
|
~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
|
|
|
|
|
enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_set_loopback(struct net_device *ndev, bool en)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
2023-01-19 18:04:30 +02:00
|
|
|
struct enetc_si *si = priv->si;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
u32 reg;
|
|
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
reg = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
|
2021-03-01 13:18:16 +02:00
|
|
|
if (reg & ENETC_PM0_IFM_RG) {
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
/* RGMII mode */
|
|
|
|
|
reg = (reg & ~ENETC_PM0_IFM_RLP) |
|
|
|
|
|
(en ? ENETC_PM0_IFM_RLP : 0);
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, reg);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
} else {
|
|
|
|
|
/* assume SGMII mode */
|
2023-01-19 18:04:30 +02:00
|
|
|
reg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
reg = (reg & ~ENETC_PM0_CMD_XGLP) |
|
|
|
|
|
(en ? ENETC_PM0_CMD_XGLP : 0);
|
|
|
|
|
reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
|
|
|
|
|
(en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, reg);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(priv->si);
|
2019-01-22 15:29:56 +02:00
|
|
|
struct enetc_vf_state *vf_state;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
|
|
|
|
if (vf >= pf->total_vfs)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
if (!is_valid_ether_addr(mac))
|
|
|
|
|
return -EADDRNOTAVAIL;
|
|
|
|
|
|
2019-01-22 15:29:56 +02:00
|
|
|
vf_state = &pf->vf_state[vf];
|
|
|
|
|
vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
|
|
|
|
|
u8 qos, __be16 proto)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(priv->si);
|
|
|
|
|
|
|
|
|
|
if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
|
|
|
|
if (vf >= pf->total_vfs)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
if (proto != htons(ETH_P_8021Q))
|
|
|
|
|
/* only C-tags supported for now */
|
|
|
|
|
return -EPROTONOSUPPORT;
|
|
|
|
|
|
|
|
|
|
enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(priv->si);
|
|
|
|
|
u32 cfgr;
|
|
|
|
|
|
|
|
|
|
if (vf >= pf->total_vfs)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
|
|
|
|
|
cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
|
|
|
|
|
enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-01-22 15:29:57 +02:00
|
|
|
static void enetc_port_assign_rfs_entries(struct enetc_si *si)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(si);
|
|
|
|
|
struct enetc_hw *hw = &si->hw;
|
|
|
|
|
int num_entries, vf_entries, i;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
/* split RFS entries between functions */
|
|
|
|
|
val = enetc_port_rd(hw, ENETC_PRFSCAPR);
|
|
|
|
|
num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
|
|
|
|
|
vf_entries = num_entries / (pf->total_vfs + 1);
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < pf->total_vfs; i++)
|
|
|
|
|
enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
|
|
|
|
|
enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
|
|
|
|
|
num_entries - vf_entries * pf->total_vfs);
|
|
|
|
|
|
|
|
|
|
/* enable RFS on port */
|
|
|
|
|
enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
|
|
|
|
|
}
|
|
|
|
|
|
net: enetc: read TSN capabilities from port register, not SI
Configuring TSN (Qbv, Qbu, PSFP) capabilities requires access to port
registers, which are available to the PSI but not the VSI.
Yet, the SI port capability register 0 (PSICAPR0), exposed to both PSIs
and VSIs, presents the same capabilities to the VF as to the PF, thus
leading the VF driver into thinking it can configure these features.
In the case of ENETC_SI_F_QBU, having it set in the VF leads to a crash:
root@ls1028ardb:~# tc qdisc add dev eno0vf0 parent root handle 100: \
mqprio num_tc 4 map 0 0 1 1 2 2 3 3 queues 1@0 1@1 1@2 1@3 hw 1
[ 187.290775] Unable to handle kernel paging request at virtual address 0000000000001f00
[ 187.424831] pc : enetc_mm_commit_preemptible_tcs+0x1c4/0x400
[ 187.430518] lr : enetc_mm_commit_preemptible_tcs+0x30c/0x400
[ 187.511140] Call trace:
[ 187.513588] enetc_mm_commit_preemptible_tcs+0x1c4/0x400
[ 187.518918] enetc_setup_tc_mqprio+0x180/0x214
[ 187.523374] enetc_vf_setup_tc+0x1c/0x30
[ 187.527306] mqprio_enable_offload+0x144/0x178
[ 187.531766] mqprio_init+0x3ec/0x668
[ 187.535351] qdisc_create+0x15c/0x488
[ 187.539023] tc_modify_qdisc+0x398/0x73c
[ 187.542958] rtnetlink_rcv_msg+0x128/0x378
[ 187.547064] netlink_rcv_skb+0x60/0x130
[ 187.550910] rtnetlink_rcv+0x18/0x24
[ 187.554492] netlink_unicast+0x300/0x36c
[ 187.558425] netlink_sendmsg+0x1a8/0x420
[ 187.606759] ---[ end trace 0000000000000000 ]---
while the other TSN features in the VF are harmless, because the
net_device_ops used for the VF driver do not expose entry points for
these other features.
These capability bits are in the process of being defeatured from the SI
registers. We should read them from the port capability register, where
they are also present, and which is naturally only exposed to the PF.
The change to blame (relevant for stable backports) is the one where
this started being a problem, aka when the kernel started to crash due
to the wrong capability seen by the VF driver.
Fixes: 827145392a4a ("net: enetc: only commit preemptible TCs to hardware when MM TX is active")
Reported-by: Wei Fang <wei.fang@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2024-11-25 17:07:18 +08:00
|
|
|
static void enetc_port_get_caps(struct enetc_si *si)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_hw *hw = &si->hw;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
val = enetc_port_rd(hw, ENETC_PCAPR0);
|
|
|
|
|
|
|
|
|
|
if (val & ENETC_PCAPR0_QBV)
|
|
|
|
|
si->hw_features |= ENETC_SI_F_QBV;
|
|
|
|
|
|
|
|
|
|
if (val & ENETC_PCAPR0_QBU)
|
|
|
|
|
si->hw_features |= ENETC_SI_F_QBU;
|
|
|
|
|
|
|
|
|
|
if (val & ENETC_PCAPR0_PSFP)
|
|
|
|
|
si->hw_features |= ENETC_SI_F_PSFP;
|
|
|
|
|
}
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
static void enetc_port_si_configure(struct enetc_si *si)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(si);
|
|
|
|
|
struct enetc_hw *hw = &si->hw;
|
|
|
|
|
int num_rings, i;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
net: enetc: read TSN capabilities from port register, not SI
Configuring TSN (Qbv, Qbu, PSFP) capabilities requires access to port
registers, which are available to the PSI but not the VSI.
Yet, the SI port capability register 0 (PSICAPR0), exposed to both PSIs
and VSIs, presents the same capabilities to the VF as to the PF, thus
leading the VF driver into thinking it can configure these features.
In the case of ENETC_SI_F_QBU, having it set in the VF leads to a crash:
root@ls1028ardb:~# tc qdisc add dev eno0vf0 parent root handle 100: \
mqprio num_tc 4 map 0 0 1 1 2 2 3 3 queues 1@0 1@1 1@2 1@3 hw 1
[ 187.290775] Unable to handle kernel paging request at virtual address 0000000000001f00
[ 187.424831] pc : enetc_mm_commit_preemptible_tcs+0x1c4/0x400
[ 187.430518] lr : enetc_mm_commit_preemptible_tcs+0x30c/0x400
[ 187.511140] Call trace:
[ 187.513588] enetc_mm_commit_preemptible_tcs+0x1c4/0x400
[ 187.518918] enetc_setup_tc_mqprio+0x180/0x214
[ 187.523374] enetc_vf_setup_tc+0x1c/0x30
[ 187.527306] mqprio_enable_offload+0x144/0x178
[ 187.531766] mqprio_init+0x3ec/0x668
[ 187.535351] qdisc_create+0x15c/0x488
[ 187.539023] tc_modify_qdisc+0x398/0x73c
[ 187.542958] rtnetlink_rcv_msg+0x128/0x378
[ 187.547064] netlink_rcv_skb+0x60/0x130
[ 187.550910] rtnetlink_rcv+0x18/0x24
[ 187.554492] netlink_unicast+0x300/0x36c
[ 187.558425] netlink_sendmsg+0x1a8/0x420
[ 187.606759] ---[ end trace 0000000000000000 ]---
while the other TSN features in the VF are harmless, because the
net_device_ops used for the VF driver do not expose entry points for
these other features.
These capability bits are in the process of being defeatured from the SI
registers. We should read them from the port capability register, where
they are also present, and which is naturally only exposed to the PF.
The change to blame (relevant for stable backports) is the one where
this started being a problem, aka when the kernel started to crash due
to the wrong capability seen by the VF driver.
Fixes: 827145392a4a ("net: enetc: only commit preemptible TCs to hardware when MM TX is active")
Reported-by: Wei Fang <wei.fang@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2024-11-25 17:07:18 +08:00
|
|
|
enetc_port_get_caps(si);
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
val = enetc_port_rd(hw, ENETC_PCAPR0);
|
|
|
|
|
num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
|
|
|
|
|
|
|
|
|
|
val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
|
|
|
|
|
val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
|
|
|
|
|
|
|
|
|
|
if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
|
|
|
|
|
val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
|
|
|
|
|
val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
|
|
|
|
|
|
|
|
|
|
dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
|
|
|
|
|
num_rings, ENETC_PF_NUM_RINGS);
|
|
|
|
|
|
|
|
|
|
num_rings = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Add default one-time settings for SI0 (PF) */
|
|
|
|
|
val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
|
|
|
|
|
|
|
|
|
|
enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
|
|
|
|
|
|
|
|
|
|
if (num_rings)
|
|
|
|
|
num_rings -= ENETC_PF_NUM_RINGS;
|
|
|
|
|
|
|
|
|
|
/* Configure the SIs for each available VF */
|
|
|
|
|
val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
|
|
|
|
|
val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
|
|
|
|
|
|
|
|
|
|
if (num_rings) {
|
|
|
|
|
num_rings /= pf->total_vfs;
|
|
|
|
|
val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
|
|
|
|
|
val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < pf->total_vfs; i++)
|
|
|
|
|
enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
|
|
|
|
|
|
|
|
|
|
/* Port level VLAN settings */
|
|
|
|
|
val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
|
|
|
|
|
enetc_port_wr(hw, ENETC_PVCLCTR, val);
|
|
|
|
|
/* use outer tag for VLAN filtering */
|
|
|
|
|
enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
|
|
|
|
|
}
|
|
|
|
|
|
2022-09-28 12:52:04 +03:00
|
|
|
void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *max_sdu)
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
{
|
2021-10-20 20:33:40 +03:00
|
|
|
int tc;
|
|
|
|
|
|
2022-09-28 12:52:04 +03:00
|
|
|
for (tc = 0; tc < 8; tc++) {
|
|
|
|
|
u32 val = ENETC_MAC_MAXFRM_SIZE;
|
|
|
|
|
|
|
|
|
|
if (max_sdu[tc])
|
|
|
|
|
val = max_sdu[tc] + VLAN_ETH_HLEN;
|
|
|
|
|
|
|
|
|
|
enetc_port_wr(hw, ENETC_PTCMSDUR(tc), val);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void enetc_reset_ptcmsdur(struct enetc_hw *hw)
|
|
|
|
|
{
|
|
|
|
|
int tc;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
2021-10-20 20:33:40 +03:00
|
|
|
for (tc = 0; tc < 8; tc++)
|
|
|
|
|
enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
|
2022-09-28 12:52:04 +03:00
|
|
|
}
|
|
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
static void enetc_configure_port_mac(struct enetc_si *si)
|
2022-09-28 12:52:04 +03:00
|
|
|
{
|
2023-01-19 18:04:30 +02:00
|
|
|
struct enetc_hw *hw = &si->hw;
|
2022-09-28 12:52:04 +03:00
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_port_mac_wr(si, ENETC_PM0_MAXFRM,
|
|
|
|
|
ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_reset_ptcmsdur(hw);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
|
|
|
|
|
ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
|
2021-03-07 15:23:38 +02:00
|
|
|
|
|
|
|
|
/* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
|
|
|
|
|
* and may lead to RX lock-up under traffic. Set it to 1 instead,
|
|
|
|
|
* as recommended by the hardware team.
|
|
|
|
|
*/
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_port_mac_wr(si, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
|
2020-10-07 12:48:20 +03:00
|
|
|
}
|
|
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
static void enetc_mac_config(struct enetc_si *si, phy_interface_t phy_mode)
|
2020-10-07 12:48:20 +03:00
|
|
|
{
|
2021-03-01 13:18:16 +02:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
if (phy_interface_mode_is_rgmii(phy_mode)) {
|
2023-01-19 18:04:30 +02:00
|
|
|
val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
|
2021-09-23 16:23:33 +03:00
|
|
|
val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
|
2021-03-01 13:18:16 +02:00
|
|
|
val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
|
2021-03-01 13:18:16 +02:00
|
|
|
}
|
2020-07-20 00:03:36 +02:00
|
|
|
|
2021-03-01 13:18:16 +02:00
|
|
|
if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
|
|
|
|
|
val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
|
2021-03-01 13:18:16 +02:00
|
|
|
}
|
2020-10-07 12:48:23 +03:00
|
|
|
}
|
|
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
static void enetc_mac_enable(struct enetc_si *si, bool en)
|
2020-10-07 12:48:23 +03:00
|
|
|
{
|
2023-01-19 18:04:30 +02:00
|
|
|
u32 val = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
|
2020-10-07 12:48:20 +03:00
|
|
|
|
2020-10-07 12:48:23 +03:00
|
|
|
val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
|
|
|
|
|
val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
|
2020-10-07 12:48:20 +03:00
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, val);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_configure_port(struct enetc_pf *pf)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_hw *hw = &pf->si->hw;
|
|
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_configure_port_mac(pf->si);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
|
|
|
|
enetc_port_si_configure(pf->si);
|
|
|
|
|
|
2019-01-22 15:29:57 +02:00
|
|
|
/* set up hash key */
|
2025-05-06 16:07:28 +08:00
|
|
|
enetc_set_default_rss_key(pf);
|
2019-01-22 15:29:57 +02:00
|
|
|
|
|
|
|
|
/* split up RFS entries */
|
|
|
|
|
enetc_port_assign_rfs_entries(pf->si);
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
/* enforce VLAN promisc mode for all SIs */
|
|
|
|
|
pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
|
|
|
|
|
enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
|
|
|
|
|
|
|
|
|
|
enetc_port_wr(hw, ENETC_PSIPMR, 0);
|
|
|
|
|
|
|
|
|
|
/* enable port */
|
|
|
|
|
enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
|
|
|
|
|
}
|
|
|
|
|
|
2019-01-22 15:29:56 +02:00
|
|
|
/* Messaging */
|
|
|
|
|
static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
|
|
|
|
|
int vf_id)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
|
|
|
|
|
struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
|
|
|
|
|
struct enetc_msg_cmd_set_primary_mac *cmd;
|
|
|
|
|
struct device *dev = &pf->si->pdev->dev;
|
|
|
|
|
u16 cmd_id;
|
|
|
|
|
char *addr;
|
|
|
|
|
|
|
|
|
|
cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;
|
|
|
|
|
cmd_id = cmd->header.id;
|
|
|
|
|
if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
|
|
|
|
|
return ENETC_MSG_CMD_STATUS_FAIL;
|
|
|
|
|
|
|
|
|
|
addr = cmd->mac.sa_data;
|
|
|
|
|
if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)
|
|
|
|
|
dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",
|
|
|
|
|
vf_id);
|
|
|
|
|
else
|
|
|
|
|
enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
|
|
|
|
|
|
|
|
|
|
return ENETC_MSG_CMD_STATUS_OK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
|
|
|
|
|
struct device *dev = &pf->si->pdev->dev;
|
|
|
|
|
struct enetc_msg_cmd_header *cmd_hdr;
|
|
|
|
|
u16 cmd_type;
|
|
|
|
|
|
|
|
|
|
*status = ENETC_MSG_CMD_STATUS_OK;
|
|
|
|
|
cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;
|
|
|
|
|
cmd_type = cmd_hdr->type;
|
|
|
|
|
|
|
|
|
|
switch (cmd_type) {
|
|
|
|
|
case ENETC_MSG_CMD_MNG_MAC:
|
|
|
|
|
*status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
dev_err(dev, "command not supported (cmd_type: 0x%x)\n",
|
|
|
|
|
cmd_type);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
|
|
|
static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_si *si = pci_get_drvdata(pdev);
|
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(si);
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (!num_vfs) {
|
2019-01-22 15:29:56 +02:00
|
|
|
enetc_msg_psi_free(pf);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
pf->num_vfs = 0;
|
|
|
|
|
pci_disable_sriov(pdev);
|
|
|
|
|
} else {
|
|
|
|
|
pf->num_vfs = num_vfs;
|
|
|
|
|
|
2019-01-22 15:29:56 +02:00
|
|
|
err = enetc_msg_psi_init(pf);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
|
|
|
|
|
goto err_msg_psi;
|
|
|
|
|
}
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
err = pci_enable_sriov(pdev, num_vfs);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
|
|
|
|
|
goto err_en_sriov;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return num_vfs;
|
|
|
|
|
|
|
|
|
|
err_en_sriov:
|
2019-01-22 15:29:56 +02:00
|
|
|
enetc_msg_psi_free(pf);
|
|
|
|
|
err_msg_psi:
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
pf->num_vfs = 0;
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
#define enetc_sriov_configure(pdev, num_vfs) (void)0
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
static int enetc_pf_set_features(struct net_device *ndev,
|
|
|
|
|
netdev_features_t features)
|
|
|
|
|
{
|
|
|
|
|
netdev_features_t changed = ndev->features ^ features;
|
|
|
|
|
struct enetc_ndev_priv *priv = netdev_priv(ndev);
|
2022-09-16 16:32:08 +03:00
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (changed & NETIF_F_HW_TC) {
|
|
|
|
|
err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC));
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
}
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
enetc: permit configuration of rx-vlan-filter with ethtool
Each ENETC station interface (SI) has a VLAN filter list and a port
flag (PSIPVMR) by which it can be put in "VLAN promiscuous" mode, which
enables the reception of VLAN-tagged traffic even if it is not in the
VLAN filtering list.
Currently the handling of this setting works like this: the port starts
off as VLAN promiscuous, then it switches to enabling VLAN filtering as
soon as the first VLAN is installed in its filter via
.ndo_vlan_rx_add_vid. In practice that does not work out very well,
because more often than not, the first VLAN to be installed is out of
the control of the user: the 8021q module, if loaded, adds its rule for
802.1p (VID 0) traffic upon bringing the interface up.
What the user is currently seeing in ethtool is this:
ethtool -k eno2
rx-vlan-filter: on [fixed]
which doesn't match the intention of the code, but the practical reality
of having the 8021q module install its VID which has the side-effect of
turning on VLAN filtering in this driver. All in all, a slightly
confusing experience.
So instead of letting this driver switch the VLAN filtering state by
itself, just wire it up with the rx-vlan-filter feature from ethtool,
and let it be user-configurable just through that knob, except for one
case, see below.
In promiscuous mode, it is more intuitive that all traffic is received,
including VLAN tagged traffic. It appears that it is necessary to set
the flag in PSIPVMR for that to be the case, so VLAN promiscuous mode is
also temporarily enabled. On exit from promiscuous mode, the setting
made by ethtool is restored.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-17 22:07:55 +03:00
|
|
|
if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
|
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(priv->si);
|
|
|
|
|
|
|
|
|
|
if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
|
|
|
|
|
enetc_disable_si_vlan_promisc(pf, 0);
|
|
|
|
|
else
|
|
|
|
|
enetc_enable_si_vlan_promisc(pf, 0);
|
|
|
|
|
}
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
if (changed & NETIF_F_LOOPBACK)
|
|
|
|
|
enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
|
|
|
|
|
|
2022-09-16 16:32:08 +03:00
|
|
|
enetc_set_features(ndev, features);
|
|
|
|
|
|
|
|
|
|
return 0;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
}
|
|
|
|
|
|
2022-09-16 16:32:09 +03:00
|
|
|
static int enetc_pf_setup_tc(struct net_device *ndev, enum tc_setup_type type,
|
|
|
|
|
void *type_data)
|
|
|
|
|
{
|
|
|
|
|
switch (type) {
|
2022-09-28 12:52:04 +03:00
|
|
|
case TC_QUERY_CAPS:
|
|
|
|
|
return enetc_qos_query_caps(ndev, type_data);
|
2022-09-16 16:32:09 +03:00
|
|
|
case TC_SETUP_QDISC_MQPRIO:
|
|
|
|
|
return enetc_setup_tc_mqprio(ndev, type_data);
|
|
|
|
|
case TC_SETUP_QDISC_TAPRIO:
|
|
|
|
|
return enetc_setup_tc_taprio(ndev, type_data);
|
|
|
|
|
case TC_SETUP_QDISC_CBS:
|
|
|
|
|
return enetc_setup_tc_cbs(ndev, type_data);
|
|
|
|
|
case TC_SETUP_QDISC_ETF:
|
|
|
|
|
return enetc_setup_tc_txtime(ndev, type_data);
|
|
|
|
|
case TC_SETUP_BLOCK:
|
|
|
|
|
return enetc_setup_tc_psfp(ndev, type_data);
|
|
|
|
|
default:
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
static const struct net_device_ops enetc_ndev_ops = {
|
|
|
|
|
.ndo_open = enetc_open,
|
|
|
|
|
.ndo_stop = enetc_close,
|
|
|
|
|
.ndo_start_xmit = enetc_xmit,
|
|
|
|
|
.ndo_get_stats = enetc_get_stats,
|
|
|
|
|
.ndo_set_mac_address = enetc_pf_set_mac_addr,
|
|
|
|
|
.ndo_set_rx_mode = enetc_pf_set_rx_mode,
|
|
|
|
|
.ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
|
|
|
|
|
.ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
|
|
|
|
|
.ndo_set_vf_mac = enetc_pf_set_vf_mac,
|
|
|
|
|
.ndo_set_vf_vlan = enetc_pf_set_vf_vlan,
|
|
|
|
|
.ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,
|
|
|
|
|
.ndo_set_features = enetc_pf_set_features,
|
2021-07-27 15:45:13 +02:00
|
|
|
.ndo_eth_ioctl = enetc_ioctl,
|
2022-09-16 16:32:09 +03:00
|
|
|
.ndo_setup_tc = enetc_pf_setup_tc,
|
net: enetc: add support for XDP_DROP and XDP_PASS
For the RX ring, enetc uses an allocation scheme based on pages split
into two buffers, which is already very efficient in terms of preventing
reallocations / maximizing reuse, so I see no reason why I would change
that.
+--------+--------+--------+--------+--------+--------+--------+
| | | | | | | |
| half B | half B | half B | half B | half B | half B | half B |
| | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+
| | | | | | | |
| half A | half A | half A | half A | half A | half A | half A | RX ring
| | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+
^ ^
| |
next_to_clean next_to_alloc
next_to_use
+--------+--------+--------+--------+--------+
| | | | | |
| half B | half B | half B | half B | half B |
| | | | | |
+--------+--------+--------+--------+--------+--------+--------+
| | | | | | | |
| half B | half B | half A | half A | half A | half A | half A | RX ring
| | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+
| | | ^ ^
| half A | half A | | |
| | | next_to_clean next_to_use
+--------+--------+
^
|
next_to_alloc
then when enetc_refill_rx_ring is called, whose purpose is to advance
next_to_use, it sees that it can take buffers up to next_to_alloc, and
it says "oh, hey, rx_swbd->page isn't NULL, I don't need to allocate
one!".
The only problem is that for default PAGE_SIZE values of 4096, buffer
sizes are 2048 bytes. While this is enough for normal skb allocations at
an MTU of 1500 bytes, for XDP it isn't, because the XDP headroom is 256
bytes, and including skb_shared_info and alignment, we end up being able
to make use of only 1472 bytes, which is insufficient for the default
MTU.
To solve that problem, we implement scatter/gather processing in the
driver, because we would really like to keep the existing allocation
scheme. A packet of 1500 bytes is received in a buffer of 1472 bytes and
another one of 28 bytes.
Because the headroom required by XDP is different (and much larger) than
the one required by the network stack, whenever a BPF program is added
or deleted on the port, we drain the existing RX buffers and seed new
ones with the required headroom. We also keep the required headroom in
rx_ring->buffer_offset.
The simplest way to implement XDP_PASS, where an skb must be created, is
to create an xdp_buff based on the next_to_clean RX BDs, but not clear
those BDs from the RX ring yet, just keep the original index at which
the BDs for this frame started. Then, if the verdict is XDP_PASS,
instead of converting the xdb_buff to an skb, we replay a call to
enetc_build_skb (just as in the normal enetc_clean_rx_ring case),
starting from the original BD index.
We would also like to be minimally invasive to the regular RX data path,
and not check whether there is a BPF program attached to the ring on
every packet. So we create a separate RX ring processing function for
XDP.
Because we only install/remove the BPF program while the interface is
down, we forgo the rcu_read_lock() in enetc_clean_rx_ring, since there
shouldn't be any circumstance in which we are processing packets and
there is a potentially freed BPF program attached to the RX ring.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-31 23:08:54 +03:00
|
|
|
.ndo_bpf = enetc_setup_bpf,
|
2021-03-31 23:08:57 +03:00
|
|
|
.ndo_xdp_xmit = enetc_xdp_xmit,
|
2025-05-12 14:24:02 +03:00
|
|
|
.ndo_hwtstamp_get = enetc_hwtstamp_get,
|
|
|
|
|
.ndo_hwtstamp_set = enetc_hwtstamp_set,
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
};
|
|
|
|
|
|
2022-01-25 16:31:10 +00:00
|
|
|
static struct phylink_pcs *
|
|
|
|
|
enetc_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_pf *pf = phylink_to_enetc_pf(config);
|
|
|
|
|
|
|
|
|
|
return pf->pcs;
|
|
|
|
|
}
|
|
|
|
|
|
2020-10-07 12:48:23 +03:00
|
|
|
static void enetc_pl_mac_config(struct phylink_config *config,
|
|
|
|
|
unsigned int mode,
|
|
|
|
|
const struct phylink_link_state *state)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_pf *pf = phylink_to_enetc_pf(config);
|
2020-07-20 00:03:35 +02:00
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_mac_config(pf->si, state->interface);
|
2020-07-20 00:03:35 +02:00
|
|
|
}
|
|
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
static void enetc_force_rgmii_mac(struct enetc_si *si, int speed, int duplex)
|
2021-03-01 13:18:16 +02:00
|
|
|
{
|
|
|
|
|
u32 old_val, val;
|
|
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
old_val = val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
|
2021-03-01 13:18:16 +02:00
|
|
|
|
|
|
|
|
if (speed == SPEED_1000) {
|
|
|
|
|
val &= ~ENETC_PM0_IFM_SSP_MASK;
|
|
|
|
|
val |= ENETC_PM0_IFM_SSP_1000;
|
|
|
|
|
} else if (speed == SPEED_100) {
|
|
|
|
|
val &= ~ENETC_PM0_IFM_SSP_MASK;
|
|
|
|
|
val |= ENETC_PM0_IFM_SSP_100;
|
|
|
|
|
} else if (speed == SPEED_10) {
|
|
|
|
|
val &= ~ENETC_PM0_IFM_SSP_MASK;
|
|
|
|
|
val |= ENETC_PM0_IFM_SSP_10;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (duplex == DUPLEX_FULL)
|
|
|
|
|
val |= ENETC_PM0_IFM_FULL_DPX;
|
|
|
|
|
else
|
|
|
|
|
val &= ~ENETC_PM0_IFM_FULL_DPX;
|
|
|
|
|
|
|
|
|
|
if (val == old_val)
|
|
|
|
|
return;
|
|
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
|
2021-03-01 13:18:16 +02:00
|
|
|
}
|
|
|
|
|
|
2020-10-07 12:48:23 +03:00
|
|
|
static void enetc_pl_mac_link_up(struct phylink_config *config,
|
|
|
|
|
struct phy_device *phy, unsigned int mode,
|
|
|
|
|
phy_interface_t interface, int speed,
|
|
|
|
|
int duplex, bool tx_pause, bool rx_pause)
|
2020-07-20 00:03:35 +02:00
|
|
|
{
|
2020-10-07 12:48:23 +03:00
|
|
|
struct enetc_pf *pf = phylink_to_enetc_pf(config);
|
2021-04-17 02:42:25 +03:00
|
|
|
u32 pause_off_thresh = 0, pause_on_thresh = 0;
|
|
|
|
|
u32 init_quanta = 0, refresh_quanta = 0;
|
|
|
|
|
struct enetc_hw *hw = &pf->si->hw;
|
2023-01-19 18:04:30 +02:00
|
|
|
struct enetc_si *si = pf->si;
|
2020-10-07 12:48:23 +03:00
|
|
|
struct enetc_ndev_priv *priv;
|
2021-04-17 02:42:25 +03:00
|
|
|
u32 rbmr, cmd_cfg;
|
|
|
|
|
int idx;
|
2020-10-07 12:48:23 +03:00
|
|
|
|
|
|
|
|
priv = netdev_priv(pf->si->ndev);
|
2022-05-10 19:36:14 +03:00
|
|
|
|
|
|
|
|
if (pf->si->hw_features & ENETC_SI_F_QBV)
|
2020-10-07 12:48:23 +03:00
|
|
|
enetc_sched_speed_set(priv, speed);
|
2020-07-20 00:03:35 +02:00
|
|
|
|
2021-03-01 13:18:16 +02:00
|
|
|
if (!phylink_autoneg_inband(mode) &&
|
|
|
|
|
phy_interface_mode_is_rgmii(interface))
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_force_rgmii_mac(si, speed, duplex);
|
2021-04-17 02:42:25 +03:00
|
|
|
|
|
|
|
|
/* Flow control */
|
|
|
|
|
for (idx = 0; idx < priv->num_rx_rings; idx++) {
|
|
|
|
|
rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
|
|
|
|
|
|
|
|
|
|
if (tx_pause)
|
|
|
|
|
rbmr |= ENETC_RBMR_CM;
|
|
|
|
|
else
|
|
|
|
|
rbmr &= ~ENETC_RBMR_CM;
|
|
|
|
|
|
|
|
|
|
enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (tx_pause) {
|
|
|
|
|
/* When the port first enters congestion, send a PAUSE request
|
|
|
|
|
* with the maximum number of quanta. When the port exits
|
|
|
|
|
* congestion, it will automatically send a PAUSE frame with
|
|
|
|
|
* zero quanta.
|
|
|
|
|
*/
|
|
|
|
|
init_quanta = 0xffff;
|
|
|
|
|
|
|
|
|
|
/* Also, set up the refresh timer to send follow-up PAUSE
|
|
|
|
|
* frames at half the quanta value, in case the congestion
|
|
|
|
|
* condition persists.
|
|
|
|
|
*/
|
|
|
|
|
refresh_quanta = 0xffff / 2;
|
|
|
|
|
|
|
|
|
|
/* Start emitting PAUSE frames when 3 large frames (or more
|
|
|
|
|
* smaller frames) have accumulated in the FIFO waiting to be
|
|
|
|
|
* DMAed to the RX ring.
|
|
|
|
|
*/
|
|
|
|
|
pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;
|
|
|
|
|
pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
|
|
|
|
|
}
|
|
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_port_mac_wr(si, ENETC_PM0_PAUSE_QUANTA, init_quanta);
|
|
|
|
|
enetc_port_mac_wr(si, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
|
2021-04-17 02:42:25 +03:00
|
|
|
enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
|
|
|
|
|
enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
|
|
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
cmd_cfg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
|
2021-04-17 02:42:25 +03:00
|
|
|
|
|
|
|
|
if (rx_pause)
|
|
|
|
|
cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
|
|
|
|
|
else
|
|
|
|
|
cmd_cfg |= ENETC_PM0_PAUSE_IGN;
|
|
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, cmd_cfg);
|
2021-03-01 13:18:16 +02:00
|
|
|
|
2023-01-19 18:04:30 +02:00
|
|
|
enetc_mac_enable(si, true);
|
2023-02-06 11:45:30 +02:00
|
|
|
|
|
|
|
|
if (si->hw_features & ENETC_SI_F_QBU)
|
|
|
|
|
enetc_mm_link_state_update(priv, true);
|
2020-07-20 00:03:35 +02:00
|
|
|
}
|
|
|
|
|
|
2020-10-07 12:48:23 +03:00
|
|
|
static void enetc_pl_mac_link_down(struct phylink_config *config,
|
|
|
|
|
unsigned int mode,
|
|
|
|
|
phy_interface_t interface)
|
2020-07-20 00:03:35 +02:00
|
|
|
{
|
2020-10-07 12:48:23 +03:00
|
|
|
struct enetc_pf *pf = phylink_to_enetc_pf(config);
|
2023-02-06 11:45:30 +02:00
|
|
|
struct enetc_si *si = pf->si;
|
|
|
|
|
struct enetc_ndev_priv *priv;
|
2020-10-07 12:48:23 +03:00
|
|
|
|
2023-02-06 11:45:30 +02:00
|
|
|
priv = netdev_priv(si->ndev);
|
|
|
|
|
|
|
|
|
|
if (si->hw_features & ENETC_SI_F_QBU)
|
|
|
|
|
enetc_mm_link_state_update(priv, false);
|
|
|
|
|
|
|
|
|
|
enetc_mac_enable(si, false);
|
2020-07-20 00:03:35 +02:00
|
|
|
}
|
|
|
|
|
|
2020-10-07 12:48:23 +03:00
|
|
|
static const struct phylink_mac_ops enetc_mac_phylink_ops = {
|
2022-01-25 16:31:10 +00:00
|
|
|
.mac_select_pcs = enetc_pl_mac_select_pcs,
|
2020-10-07 12:48:23 +03:00
|
|
|
.mac_config = enetc_pl_mac_config,
|
|
|
|
|
.mac_link_up = enetc_pl_mac_link_up,
|
|
|
|
|
.mac_link_down = enetc_pl_mac_link_down,
|
|
|
|
|
};
|
|
|
|
|
|
net: enetc: initialize the RFS and RSS memories
Michael tried to enable Advanced Error Reporting through the ENETC's
Root Complex Event Collector, and the system started spitting out single
bit correctable ECC errors coming from the ENETC interfaces:
pcieport 0000:00:1f.0: AER: Multiple Corrected error received: 0000:00:00.0
fsl_enetc 0000:00:00.0: PCIe Bus Error: severity=Corrected, type=Transaction Layer, (Receiver ID)
fsl_enetc 0000:00:00.0: device [1957:e100] error status/mask=00004000/00000000
fsl_enetc 0000:00:00.0: [14] CorrIntErr
fsl_enetc 0000:00:00.1: PCIe Bus Error: severity=Corrected, type=Transaction Layer, (Receiver ID)
fsl_enetc 0000:00:00.1: device [1957:e100] error status/mask=00004000/00000000
fsl_enetc 0000:00:00.1: [14] CorrIntErr
Further investigating the port correctable memory error detect register
(PCMEDR) shows that these AER errors have an associated SOURCE_ID of 6
(RFS/RSS):
$ devmem 0x1f8010e10 32
0xC0000006
$ devmem 0x1f8050e10 32
0xC0000006
Discussion with the hardware design engineers reveals that on LS1028A,
the hardware does not do initialization of that RFS/RSS memory, and that
software should clear/initialize the entire table before starting to
operate. That comes as a bit of a surprise, since the driver does not do
initialization of the RFS memory. Also, the initialization of the
Receive Side Scaling is done only partially.
Even though the entire ENETC IP has a single shared flow steering
memory, the flow steering service should returns matches only for TCAM
entries that are within the range of the Station Interface that is doing
the search. Therefore, it should be sufficient for a Station Interface
to initialize all of its own entries in order to avoid any ECC errors,
and only the Station Interfaces in use should need initialization.
There are Physical Station Interfaces associated with PCIe PFs and
Virtual Station Interfaces associated with PCIe VFs. We let the PF
driver initialize the entire port's memory, which includes the RFS
entries which are going to be used by the VF.
Reported-by: Michael Walle <michael@walle.cc>
Fixes: d4fd0404c1c9 ("enetc: Introduce basic PF and VF ENETC ethernet drivers")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Link: https://lore.kernel.org/r/20210204134511.2640309-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-02-04 15:45:11 +02:00
|
|
|
/* Initialize the entire shared memory for the flow steering entries
|
|
|
|
|
* of this port (PF + VFs)
|
|
|
|
|
*/
|
|
|
|
|
static int enetc_init_port_rfs_memory(struct enetc_si *si)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_cmd_rfse rfse = {0};
|
|
|
|
|
struct enetc_hw *hw = &si->hw;
|
|
|
|
|
int num_rfs, i, err = 0;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
val = enetc_port_rd(hw, ENETC_PRFSCAPR);
|
|
|
|
|
num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < num_rfs; i++) {
|
|
|
|
|
err = enetc_set_fs_entry(si, &rfse, i);
|
|
|
|
|
if (err)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int enetc_init_port_rss_memory(struct enetc_si *si)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_hw *hw = &si->hw;
|
|
|
|
|
int num_rss, err;
|
|
|
|
|
int *rss_table;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
val = enetc_port_rd(hw, ENETC_PRSSCAPR);
|
|
|
|
|
num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
|
|
|
|
|
if (!num_rss)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
|
|
|
|
|
if (!rss_table)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
err = enetc_set_rss_table(si, rss_table, num_rss);
|
|
|
|
|
|
|
|
|
|
kfree(rss_table);
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
net: enetc: add a mini driver for the Integrated Endpoint Register Block
The NXP ENETC is a 4-port Ethernet controller which 'smells' to
operating systems like 4 distinct PCIe PFs with SR-IOV, each PF having
its own driver instance, but in fact there are some hardware resources
which are shared between all ports, like for example the 256 KB SRAM
FIFO between the MACs and the Host Transfer Agent which DMAs frames to
DRAM.
To hide the stuff that cannot be neatly exposed per port, the hardware
designers came up with this idea of having a dedicated register block
which is supposed to be populated by the bootloader, and contains
everything configuration-related: MAC addresses, FIFO partitioning, etc.
When a port is reset using PCIe Function Level Reset, its defaults are
transferred from the IERB configuration. Most of the time, the settings
made through the IERB are read-only in the port's memory space (if they
are even visible), so they cannot be modified at runtime.
Linux doesn't have any advanced FIFO partitioning requirements at all,
but when reading through the hardware manual, it became clear that, even
though there are many good 'recommendations' for default values, many of
them were not actually put in practice on LS1028A. So we end up with a
default configuration that:
(a) does not have enough TX and RX byte credits to support the max MTU
of 9600 (which the Linux driver claims already) properly (at full speed)
(b) allows the FIFO to be overrun with RX traffic, potentially
overwriting internal data structures.
The last part sounds a bit catastrophic, but it isn't. Frames are
supposed to transit the FIFO for a very short time, but they can
actually accumulate there under 2 conditions:
(a) there is very severe congestion on DRAM memory, or
(b) the RX rings visible to the operating system were configured for
lossless operation, and they just ran out of free buffers to copy
the frame to. This is what is used to put backpressure onto the MAC
with flow control.
So since ENETC has not supported flow control thus far, RX FIFO overruns
were never seen with Linux. But with the addition of flow control, we
should configure some registers to prevent this from happening. What we
are trying to protect against are bad actors which continue to send us
traffic despite the fact that we have signaled a PAUSE condition. Of
course we can't be lossless in that case, but it is best to configure
the FIFO to do tail dropping rather than letting it overrun.
So in a nutshell, this driver is a fixup for all the IERB default values
that should have been but aren't.
The IERB configuration needs to be done _before_ the PFs are enabled.
So every PF searches for the presence of the "fsl,ls1028a-enetc-ierb"
node in the device tree, and if it finds it, it "registers" with the
IERB, which means that it requests the IERB to fix up its default
values. This is done through -EPROBE_DEFER. The IERB driver is part of
the fsl_enetc module, but is technically a platform driver, since the
IERB is a good old fashioned MMIO region, as opposed to ENETC ports
which pretend to be PCIe devices.
The driver was already configuring ENETC_PTXMBAR (FIFO allocation for
TX) because due to an omission, TXMBAR is a read/write register in the
PF memory space. But the manual is quite clear that the formula for this
should depend upon the TX byte credits (TXBCR). In turn, the TX byte
credits are only readable/writable through the IERB. So if we want to
ensure that the TXBCR register also has a value that is correct and in
line with TXMBAR, there is simply no way this can be done from the PF
driver, access to the IERB is needed.
I could have modified U-Boot to fix up the IERB values, but that is
quite undesirable, as old U-Boot versions are likely to be floating
around for quite some time from now.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-17 02:42:23 +03:00
|
|
|
static int enetc_pf_register_with_ierb(struct pci_dev *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct platform_device *ierb_pdev;
|
|
|
|
|
struct device_node *ierb_node;
|
|
|
|
|
|
|
|
|
|
ierb_node = of_find_compatible_node(NULL, NULL,
|
|
|
|
|
"fsl,ls1028a-enetc-ierb");
|
|
|
|
|
if (!ierb_node || !of_device_is_available(ierb_node))
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
|
|
ierb_pdev = of_find_device_by_node(ierb_node);
|
|
|
|
|
of_node_put(ierb_node);
|
|
|
|
|
|
|
|
|
|
if (!ierb_pdev)
|
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
|
|
|
|
|
|
return enetc_ierb_register_pf(ierb_pdev, pdev);
|
|
|
|
|
}
|
|
|
|
|
|
2025-05-06 16:07:27 +08:00
|
|
|
static const struct enetc_si_ops enetc_psi_ops = {
|
|
|
|
|
.get_rss_table = enetc_get_rss_table,
|
|
|
|
|
.set_rss_table = enetc_set_rss_table,
|
|
|
|
|
};
|
|
|
|
|
|
2023-08-03 16:58:57 +03:00
|
|
|
static struct enetc_si *enetc_psi_create(struct pci_dev *pdev)
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
{
|
|
|
|
|
struct enetc_si *si;
|
|
|
|
|
int err;
|
|
|
|
|
|
2023-08-03 16:58:57 +03:00
|
|
|
err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(struct enetc_pf));
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err_probe(&pdev->dev, err, "PCI probing failed\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
|
|
|
|
si = pci_get_drvdata(pdev);
|
|
|
|
|
if (!si->hw.port || !si->hw.global) {
|
|
|
|
|
err = -ENODEV;
|
|
|
|
|
dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
|
2023-08-03 16:58:57 +03:00
|
|
|
goto out_pci_remove;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-30 17:39:22 +08:00
|
|
|
si->revision = enetc_get_ip_revision(&si->hw);
|
2025-05-06 16:07:27 +08:00
|
|
|
si->ops = &enetc_psi_ops;
|
2024-10-30 17:39:22 +08:00
|
|
|
err = enetc_get_driver_data(si);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "Could not get PF driver data\n");
|
|
|
|
|
goto out_pci_remove;
|
|
|
|
|
}
|
|
|
|
|
|
2021-03-10 14:03:46 +02:00
|
|
|
err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,
|
|
|
|
|
&si->cbd_ring);
|
|
|
|
|
if (err)
|
2023-08-03 16:58:57 +03:00
|
|
|
goto out_pci_remove;
|
2021-03-10 14:03:46 +02:00
|
|
|
|
|
|
|
|
err = enetc_init_port_rfs_memory(si);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
|
2023-08-03 16:58:57 +03:00
|
|
|
goto out_teardown_cbdr;
|
2021-03-10 14:03:46 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
err = enetc_init_port_rss_memory(si);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
|
2023-08-03 16:58:57 +03:00
|
|
|
goto out_teardown_cbdr;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return si;
|
|
|
|
|
|
|
|
|
|
out_teardown_cbdr:
|
|
|
|
|
enetc_teardown_cbdr(&si->cbd_ring);
|
|
|
|
|
out_pci_remove:
|
|
|
|
|
enetc_pci_remove(pdev);
|
|
|
|
|
out:
|
|
|
|
|
return ERR_PTR(err);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_psi_destroy(struct pci_dev *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_si *si = pci_get_drvdata(pdev);
|
|
|
|
|
|
|
|
|
|
enetc_teardown_cbdr(&si->cbd_ring);
|
|
|
|
|
enetc_pci_remove(pdev);
|
|
|
|
|
}
|
|
|
|
|
|
2024-10-30 17:39:17 +08:00
|
|
|
static const struct enetc_pf_ops enetc_pf_ops = {
|
|
|
|
|
.set_si_primary_mac = enetc_pf_set_primary_mac_addr,
|
|
|
|
|
.get_si_primary_mac = enetc_pf_get_primary_mac_addr,
|
|
|
|
|
.create_pcs = enetc_pf_create_pcs,
|
|
|
|
|
.destroy_pcs = enetc_pf_destroy_pcs,
|
|
|
|
|
.enable_psfp = enetc_psfp_enable,
|
|
|
|
|
};
|
|
|
|
|
|
2023-08-03 16:58:57 +03:00
|
|
|
static int enetc_pf_probe(struct pci_dev *pdev,
|
|
|
|
|
const struct pci_device_id *ent)
|
|
|
|
|
{
|
|
|
|
|
struct device_node *node = pdev->dev.of_node;
|
|
|
|
|
struct enetc_ndev_priv *priv;
|
|
|
|
|
struct net_device *ndev;
|
|
|
|
|
struct enetc_si *si;
|
|
|
|
|
struct enetc_pf *pf;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = enetc_pf_register_with_ierb(pdev);
|
|
|
|
|
if (err == -EPROBE_DEFER)
|
|
|
|
|
return err;
|
|
|
|
|
if (err)
|
|
|
|
|
dev_warn(&pdev->dev,
|
|
|
|
|
"Could not register with IERB driver: %pe, please update the device tree\n",
|
|
|
|
|
ERR_PTR(err));
|
|
|
|
|
|
|
|
|
|
si = enetc_psi_create(pdev);
|
|
|
|
|
if (IS_ERR(si)) {
|
|
|
|
|
err = PTR_ERR(si);
|
|
|
|
|
goto err_psi_create;
|
2021-03-10 14:03:46 +02:00
|
|
|
}
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
pf = enetc_si_priv(si);
|
|
|
|
|
pf->si = si;
|
2024-10-30 17:39:17 +08:00
|
|
|
pf->ops = &enetc_pf_ops;
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
|
|
|
|
pf->total_vfs = pci_sriov_get_totalvfs(pdev);
|
2024-10-31 14:02:46 +08:00
|
|
|
if (pf->total_vfs) {
|
|
|
|
|
pf->vf_state = kcalloc(pf->total_vfs, sizeof(struct enetc_vf_state),
|
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
if (!pf->vf_state)
|
|
|
|
|
goto err_alloc_vf_state;
|
|
|
|
|
}
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
2021-04-14 16:48:14 +02:00
|
|
|
err = enetc_setup_mac_addresses(node, pf);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_setup_mac_addresses;
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
enetc_configure_port(pf);
|
|
|
|
|
|
|
|
|
|
enetc_get_si_caps(si);
|
|
|
|
|
|
|
|
|
|
ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
|
|
|
|
|
if (!ndev) {
|
|
|
|
|
err = -ENOMEM;
|
|
|
|
|
dev_err(&pdev->dev, "netdev creation failed\n");
|
|
|
|
|
goto err_alloc_netdev;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
|
|
|
|
|
|
|
|
|
|
priv = netdev_priv(ndev);
|
|
|
|
|
|
2023-02-06 11:45:30 +02:00
|
|
|
mutex_init(&priv->mm_lock);
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
enetc_init_si_rings_params(priv);
|
|
|
|
|
|
|
|
|
|
err = enetc_alloc_si_resources(priv);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "SI resource alloc failed\n");
|
|
|
|
|
goto err_alloc_si_res;
|
|
|
|
|
}
|
|
|
|
|
|
2021-03-01 13:18:11 +02:00
|
|
|
err = enetc_configure_si(priv);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "Failed to configure SI\n");
|
|
|
|
|
goto err_config_si;
|
|
|
|
|
}
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
err = enetc_alloc_msix(priv);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "MSIX alloc failed\n");
|
|
|
|
|
goto err_alloc_msix;
|
|
|
|
|
}
|
|
|
|
|
|
net: enetc: kill PHY-less mode for PFs
Right now, a PHY-less port (no phy-mode, no fixed-link, no phy-handle)
doesn't register with phylink, but calls netif_carrier_on() from
enetc_start().
This makes sense for a VF, but for a PF, this is braindead, because we
never call enetc_mac_enable() so the MAC is left inoperational.
Furthermore, commit 71b77a7a27a3 ("enetc: Migrate to PHYLINK and
PCS_LYNX") put the nail in the coffin because it removed the initial
netif_carrier_off() call done right after register_netdev().
Without that call, netif_carrier_on() does not call
linkwatch_fire_event(), so the operstate remains IF_OPER_UNKNOWN.
Just deny the broken configuration by requiring that a phy-mode is
present, and always register a PF with phylink.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Link: https://lore.kernel.org/r/20220511094200.558502-1-vladimir.oltean@nxp.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-05-11 12:42:00 +03:00
|
|
|
err = of_get_phy_mode(node, &pf->if_mode);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "Failed to read PHY mode\n");
|
|
|
|
|
goto err_phy_mode;
|
2020-10-07 12:48:20 +03:00
|
|
|
}
|
2020-07-20 00:03:35 +02:00
|
|
|
|
net: enetc: kill PHY-less mode for PFs
Right now, a PHY-less port (no phy-mode, no fixed-link, no phy-handle)
doesn't register with phylink, but calls netif_carrier_on() from
enetc_start().
This makes sense for a VF, but for a PF, this is braindead, because we
never call enetc_mac_enable() so the MAC is left inoperational.
Furthermore, commit 71b77a7a27a3 ("enetc: Migrate to PHYLINK and
PCS_LYNX") put the nail in the coffin because it removed the initial
netif_carrier_off() call done right after register_netdev().
Without that call, netif_carrier_on() does not call
linkwatch_fire_event(), so the operstate remains IF_OPER_UNKNOWN.
Just deny the broken configuration by requiring that a phy-mode is
present, and always register a PF with phylink.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Link: https://lore.kernel.org/r/20220511094200.558502-1-vladimir.oltean@nxp.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-05-11 12:42:00 +03:00
|
|
|
err = enetc_mdiobus_create(pf, node);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_mdiobus_create;
|
|
|
|
|
|
2024-10-30 17:39:16 +08:00
|
|
|
err = enetc_phylink_create(priv, node, &enetc_mac_phylink_ops);
|
net: enetc: kill PHY-less mode for PFs
Right now, a PHY-less port (no phy-mode, no fixed-link, no phy-handle)
doesn't register with phylink, but calls netif_carrier_on() from
enetc_start().
This makes sense for a VF, but for a PF, this is braindead, because we
never call enetc_mac_enable() so the MAC is left inoperational.
Furthermore, commit 71b77a7a27a3 ("enetc: Migrate to PHYLINK and
PCS_LYNX") put the nail in the coffin because it removed the initial
netif_carrier_off() call done right after register_netdev().
Without that call, netif_carrier_on() does not call
linkwatch_fire_event(), so the operstate remains IF_OPER_UNKNOWN.
Just deny the broken configuration by requiring that a phy-mode is
present, and always register a PF with phylink.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Link: https://lore.kernel.org/r/20220511094200.558502-1-vladimir.oltean@nxp.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-05-11 12:42:00 +03:00
|
|
|
if (err)
|
|
|
|
|
goto err_phylink_create;
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
err = register_netdev(ndev);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_reg_netdev;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_reg_netdev:
|
2020-10-07 12:48:23 +03:00
|
|
|
enetc_phylink_destroy(priv);
|
|
|
|
|
err_phylink_create:
|
2020-10-07 12:48:20 +03:00
|
|
|
enetc_mdiobus_destroy(pf);
|
|
|
|
|
err_mdiobus_create:
|
net: enetc: kill PHY-less mode for PFs
Right now, a PHY-less port (no phy-mode, no fixed-link, no phy-handle)
doesn't register with phylink, but calls netif_carrier_on() from
enetc_start().
This makes sense for a VF, but for a PF, this is braindead, because we
never call enetc_mac_enable() so the MAC is left inoperational.
Furthermore, commit 71b77a7a27a3 ("enetc: Migrate to PHYLINK and
PCS_LYNX") put the nail in the coffin because it removed the initial
netif_carrier_off() call done right after register_netdev().
Without that call, netif_carrier_on() does not call
linkwatch_fire_event(), so the operstate remains IF_OPER_UNKNOWN.
Just deny the broken configuration by requiring that a phy-mode is
present, and always register a PF with phylink.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Link: https://lore.kernel.org/r/20220511094200.558502-1-vladimir.oltean@nxp.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-05-11 12:42:00 +03:00
|
|
|
err_phy_mode:
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
enetc_free_msix(priv);
|
2021-03-01 13:18:11 +02:00
|
|
|
err_config_si:
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
err_alloc_msix:
|
|
|
|
|
enetc_free_si_resources(priv);
|
|
|
|
|
err_alloc_si_res:
|
|
|
|
|
si->ndev = NULL;
|
|
|
|
|
free_netdev(ndev);
|
|
|
|
|
err_alloc_netdev:
|
2021-04-14 16:48:14 +02:00
|
|
|
err_setup_mac_addresses:
|
2024-10-31 14:02:46 +08:00
|
|
|
kfree(pf->vf_state);
|
|
|
|
|
err_alloc_vf_state:
|
2023-08-03 16:58:57 +03:00
|
|
|
enetc_psi_destroy(pdev);
|
|
|
|
|
err_psi_create:
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_pf_remove(struct pci_dev *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct enetc_si *si = pci_get_drvdata(pdev);
|
|
|
|
|
struct enetc_pf *pf = enetc_si_priv(si);
|
|
|
|
|
struct enetc_ndev_priv *priv;
|
|
|
|
|
|
2020-10-07 12:48:20 +03:00
|
|
|
priv = netdev_priv(si->ndev);
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
if (pf->num_vfs)
|
|
|
|
|
enetc_sriov_configure(pdev, 0);
|
|
|
|
|
|
|
|
|
|
unregister_netdev(si->ndev);
|
|
|
|
|
|
2021-02-16 12:16:28 +02:00
|
|
|
enetc_phylink_destroy(priv);
|
|
|
|
|
enetc_mdiobus_destroy(pf);
|
|
|
|
|
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
enetc_free_msix(priv);
|
|
|
|
|
|
|
|
|
|
enetc_free_si_resources(priv);
|
|
|
|
|
|
|
|
|
|
free_netdev(si->ndev);
|
2024-10-31 14:02:46 +08:00
|
|
|
kfree(pf->vf_state);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
2023-08-03 16:58:57 +03:00
|
|
|
enetc_psi_destroy(pdev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enetc_fixup_clear_rss_rfs(struct pci_dev *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct device_node *node = pdev->dev.of_node;
|
|
|
|
|
struct enetc_si *si;
|
|
|
|
|
|
|
|
|
|
/* Only apply quirk for disabled functions. For the ones
|
|
|
|
|
* that are enabled, enetc_pf_probe() will apply it.
|
|
|
|
|
*/
|
|
|
|
|
if (node && of_device_is_available(node))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
si = enetc_psi_create(pdev);
|
2023-09-06 17:16:09 +03:00
|
|
|
if (!IS_ERR(si))
|
2023-08-03 16:58:57 +03:00
|
|
|
enetc_psi_destroy(pdev);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
}
|
2023-08-03 16:58:57 +03:00
|
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF,
|
|
|
|
|
enetc_fixup_clear_rss_rfs);
|
enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
|
|
|
|
|
|
|
|
static const struct pci_device_id enetc_pf_id_table[] = {
|
|
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
|
|
|
|
|
{ 0, } /* End of table. */
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
|
|
|
|
|
|
|
|
|
|
static struct pci_driver enetc_pf_driver = {
|
|
|
|
|
.name = KBUILD_MODNAME,
|
|
|
|
|
.id_table = enetc_pf_id_table,
|
|
|
|
|
.probe = enetc_pf_probe,
|
|
|
|
|
.remove = enetc_pf_remove,
|
|
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
|
|
|
.sriov_configure = enetc_sriov_configure,
|
|
|
|
|
#endif
|
|
|
|
|
};
|
|
|
|
|
module_pci_driver(enetc_pf_driver);
|
|
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
|
|
|
|
|
MODULE_LICENSE("Dual BSD/GPL");
|