enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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# SPDX-License-Identifier: GPL-2.0
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2023-01-19 18:04:26 +02:00
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config FSL_ENETC_CORE
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tristate
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2025-06-05 14:08:36 +08:00
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select NXP_NETC_LIB if NXP_NTMP
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2023-01-19 18:04:26 +02:00
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help
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This module supports common functionality between the PF and VF
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drivers for the NXP ENETC controller.
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If compiled as module (M), the module name is fsl-enetc-core.
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2024-10-30 17:39:17 +08:00
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config NXP_ENETC_PF_COMMON
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tristate
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help
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This module supports common functionality between drivers of
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different versions of NXP ENETC PF controllers.
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If compiled as module (M), the module name is nxp-enetc-pf-common.
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2025-05-06 16:07:22 +08:00
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config NXP_NETC_LIB
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tristate
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help
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This module provides common functionalities for both ENETC and NETC
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Switch, such as NETC Table Management Protocol (NTMP) 2.0, common tc
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flower and debugfs interfaces and so on.
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2025-06-05 14:08:36 +08:00
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config NXP_NTMP
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bool
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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config FSL_ENETC
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tristate "ENETC PF driver"
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2023-01-11 13:58:55 +01:00
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depends on PCI_MSI
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2023-01-19 18:04:26 +02:00
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select FSL_ENETC_CORE
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2021-04-20 16:28:21 +02:00
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select FSL_ENETC_IERB
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2020-01-06 03:34:13 +02:00
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select FSL_ENETC_MDIO
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2024-10-30 17:39:17 +08:00
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select NXP_ENETC_PF_COMMON
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2020-10-07 12:48:23 +03:00
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select PHYLINK
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select PCS_LYNX
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2020-07-21 10:55:22 +03:00
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select DIMLIB
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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help
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This driver supports NXP ENETC gigabit ethernet controller PCIe
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physical function (PF) devices, managing ENETC Ports at a privileged
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level.
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If compiled as module (M), the module name is fsl-enetc.
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2024-10-30 17:39:22 +08:00
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config NXP_ENETC4
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tristate "ENETC4 PF driver"
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depends on PCI_MSI
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select FSL_ENETC_CORE
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select FSL_ENETC_MDIO
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select NXP_ENETC_PF_COMMON
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2025-06-05 14:08:36 +08:00
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select NXP_NTMP
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2024-10-30 17:39:22 +08:00
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select PHYLINK
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select DIMLIB
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help
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This driver supports NXP ENETC devices with major revision 4. ENETC is
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as the NIC functionality in NETC, it supports virtualization/isolation
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based on PCIe Single Root IO Virtualization (SR-IOV) and a full range
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of TSN standards and NIC offload capabilities.
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If compiled as module (M), the module name is nxp-enetc4.
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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config FSL_ENETC_VF
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tristate "ENETC VF driver"
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2023-01-11 13:58:55 +01:00
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depends on PCI_MSI
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2023-01-19 18:04:26 +02:00
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select FSL_ENETC_CORE
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2020-11-12 20:26:08 +02:00
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select FSL_ENETC_MDIO
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2020-10-07 12:48:23 +03:00
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select PHYLINK
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2020-07-21 10:55:22 +03:00
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select DIMLIB
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enetc: Introduce basic PF and VF ENETC ethernet drivers
ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE). As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.
Introduce basic PF and VF ENETC ethernet drivers. The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices. Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each. Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).
Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 15:29:54 +02:00
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help
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This driver supports NXP ENETC gigabit ethernet controller PCIe
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virtual function (VF) devices enabled by the ENETC PF driver.
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If compiled as module (M), the module name is fsl-enetc-vf.
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2019-02-12 12:24:03 +08:00
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net: enetc: add a mini driver for the Integrated Endpoint Register Block
The NXP ENETC is a 4-port Ethernet controller which 'smells' to
operating systems like 4 distinct PCIe PFs with SR-IOV, each PF having
its own driver instance, but in fact there are some hardware resources
which are shared between all ports, like for example the 256 KB SRAM
FIFO between the MACs and the Host Transfer Agent which DMAs frames to
DRAM.
To hide the stuff that cannot be neatly exposed per port, the hardware
designers came up with this idea of having a dedicated register block
which is supposed to be populated by the bootloader, and contains
everything configuration-related: MAC addresses, FIFO partitioning, etc.
When a port is reset using PCIe Function Level Reset, its defaults are
transferred from the IERB configuration. Most of the time, the settings
made through the IERB are read-only in the port's memory space (if they
are even visible), so they cannot be modified at runtime.
Linux doesn't have any advanced FIFO partitioning requirements at all,
but when reading through the hardware manual, it became clear that, even
though there are many good 'recommendations' for default values, many of
them were not actually put in practice on LS1028A. So we end up with a
default configuration that:
(a) does not have enough TX and RX byte credits to support the max MTU
of 9600 (which the Linux driver claims already) properly (at full speed)
(b) allows the FIFO to be overrun with RX traffic, potentially
overwriting internal data structures.
The last part sounds a bit catastrophic, but it isn't. Frames are
supposed to transit the FIFO for a very short time, but they can
actually accumulate there under 2 conditions:
(a) there is very severe congestion on DRAM memory, or
(b) the RX rings visible to the operating system were configured for
lossless operation, and they just ran out of free buffers to copy
the frame to. This is what is used to put backpressure onto the MAC
with flow control.
So since ENETC has not supported flow control thus far, RX FIFO overruns
were never seen with Linux. But with the addition of flow control, we
should configure some registers to prevent this from happening. What we
are trying to protect against are bad actors which continue to send us
traffic despite the fact that we have signaled a PAUSE condition. Of
course we can't be lossless in that case, but it is best to configure
the FIFO to do tail dropping rather than letting it overrun.
So in a nutshell, this driver is a fixup for all the IERB default values
that should have been but aren't.
The IERB configuration needs to be done _before_ the PFs are enabled.
So every PF searches for the presence of the "fsl,ls1028a-enetc-ierb"
node in the device tree, and if it finds it, it "registers" with the
IERB, which means that it requests the IERB to fix up its default
values. This is done through -EPROBE_DEFER. The IERB driver is part of
the fsl_enetc module, but is technically a platform driver, since the
IERB is a good old fashioned MMIO region, as opposed to ENETC ports
which pretend to be PCIe devices.
The driver was already configuring ENETC_PTXMBAR (FIFO allocation for
TX) because due to an omission, TXMBAR is a read/write register in the
PF memory space. But the manual is quite clear that the formula for this
should depend upon the TX byte credits (TXBCR). In turn, the TX byte
credits are only readable/writable through the IERB. So if we want to
ensure that the TXBCR register also has a value that is correct and in
line with TXMBAR, there is simply no way this can be done from the PF
driver, access to the IERB is needed.
I could have modified U-Boot to fix up the IERB values, but that is
quite undesirable, as old U-Boot versions are likely to be floating
around for quite some time from now.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-17 02:42:23 +03:00
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config FSL_ENETC_IERB
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tristate "ENETC IERB driver"
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help
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This driver configures the Integrated Endpoint Register Block on NXP
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LS1028A.
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If compiled as module (M), the module name is fsl-enetc-ierb.
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2019-08-01 14:52:51 +03:00
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config FSL_ENETC_MDIO
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tristate "ENETC MDIO driver"
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2025-04-29 08:04:46 +02:00
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depends on PCI && PHYLIB
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2019-08-01 14:52:51 +03:00
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help
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This driver supports NXP ENETC Central MDIO controller as a PCIe
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physical function (PF) device.
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If compiled as module (M), the module name is fsl-enetc-mdio.
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2019-02-12 12:24:03 +08:00
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config FSL_ENETC_PTP_CLOCK
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tristate "ENETC PTP clock driver"
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depends on PTP_1588_CLOCK_QORIQ && (FSL_ENETC || FSL_ENETC_VF)
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default y
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help
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This driver adds support for using the ENETC 1588 timer
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as a PTP clock. This clock is only useful if your PTP
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programs are getting hardware time stamps on the PTP Ethernet
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packets using the SO_TIMESTAMPING API.
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If compiled as module (M), the module name is fsl-enetc-ptp.
|
2019-05-23 02:33:29 +00:00
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2019-11-15 03:33:33 +00:00
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config FSL_ENETC_QOS
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bool "ENETC hardware Time-sensitive Network support"
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2019-11-25 05:56:56 +00:00
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depends on (FSL_ENETC || FSL_ENETC_VF) && (NET_SCH_TAPRIO || NET_SCH_CBS)
|
2019-11-15 03:33:33 +00:00
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help
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There are Time-Sensitive Network(TSN) capabilities(802.1Qbv/802.1Qci
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/802.1Qbu etc.) supported by ENETC. These TSN capabilities can be set
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enable/disable from user space via Qos commands(tc). In the kernel
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side, it can be loaded by Qos driver. Currently, it is only support
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2019-11-25 05:56:56 +00:00
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taprio(802.1Qbv) and Credit Based Shaper(802.1Qbu).
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2024-10-30 17:39:15 +08:00
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config NXP_NETC_BLK_CTRL
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tristate "NETC blocks control driver"
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help
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This driver configures Integrated Endpoint Register Block (IERB) and
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Privileged Register Block (PRB) of NETC. For i.MX platforms, it also
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includes the configuration of NETCMIX block.
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The IERB contains registers that are used for pre-boot initialization,
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debug, and non-customer configuration. The PRB controls global reset
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and global error handling for NETC. The NETCMIX block is mainly used
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to set MII protocol and PCS protocol of the links, it also contains
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settings for some other functions.
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If compiled as module (M), the module name is nxp-netc-blk-ctrl.
|