2022-05-27 16:37:47 -04:00
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// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
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/*
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* Copyright 2008 - 2016 Freescale Semiconductor Inc.
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dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
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* Copyright 2020 NXP
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2016-11-15 10:41:02 +02:00
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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2023-07-26 19:49:39 -06:00
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#include <linux/mod_devicetable.h>
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2016-11-15 10:41:02 +02:00
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#include <linux/module.h>
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#include <linux/of_mdio.h>
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#include <linux/of_net.h>
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#include <linux/io.h>
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#include <linux/if_arp.h>
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#include <linux/if_vlan.h>
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#include <linux/icmp.h>
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#include <linux/ip.h>
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#include <linux/ipv6.h>
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2023-07-26 19:49:39 -06:00
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#include <linux/platform_device.h>
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2016-11-15 10:41:02 +02:00
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#include <linux/udp.h>
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#include <linux/tcp.h>
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#include <linux/net.h>
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#include <linux/skbuff.h>
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#include <linux/etherdevice.h>
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#include <linux/if_ether.h>
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#include <linux/highmem.h>
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#include <linux/percpu.h>
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#include <linux/dma-mapping.h>
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#include <linux/sort.h>
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2020-11-25 18:53:31 +02:00
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#include <linux/bpf.h>
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#include <linux/bpf_trace.h>
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2016-11-15 10:41:02 +02:00
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#include <soc/fsl/bman.h>
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#include <soc/fsl/qman.h>
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#include "fman.h"
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#include "fman_port.h"
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#include "mac.h"
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#include "dpaa_eth.h"
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2016-11-15 10:41:06 +02:00
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/* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files
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* using trace events only need to #include <trace/events/sched.h>
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*/
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#define CREATE_TRACE_POINTS
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#include "dpaa_eth_trace.h"
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2016-11-15 10:41:02 +02:00
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static int debug = -1;
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module_param(debug, int, 0444);
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MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)");
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static u16 tx_timeout = 1000;
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module_param(tx_timeout, ushort, 0444);
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MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms");
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#define FM_FD_STAT_RX_ERRORS \
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(FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL | \
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FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \
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FM_FD_ERR_EXTRACTION | FM_FD_ERR_NO_SCHEME | \
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FM_FD_ERR_PRS_TIMEOUT | FM_FD_ERR_PRS_ILL_INSTRUCT | \
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FM_FD_ERR_PRS_HDR_ERR)
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#define FM_FD_STAT_TX_ERRORS \
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(FM_FD_ERR_UNSUPPORTED_FORMAT | \
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FM_FD_ERR_LENGTH | FM_FD_ERR_DMA)
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#define DPAA_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
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NETIF_MSG_LINK | NETIF_MSG_IFUP | \
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2020-10-08 15:03:12 +03:00
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NETIF_MSG_IFDOWN | NETIF_MSG_HW)
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2016-11-15 10:41:02 +02:00
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#define DPAA_INGRESS_CS_THRESHOLD 0x10000000
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/* Ingress congestion threshold on FMan ports
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* The size in bytes of the ingress tail-drop threshold on FMan ports.
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* Traffic piling up above this value will be rejected by QMan and discarded
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* by FMan.
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*/
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/* Size in bytes of the FQ taildrop threshold */
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#define DPAA_FQ_TD 0x200000
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#define DPAA_CS_THRESHOLD_1G 0x06000000
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/* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000
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* The size in bytes of the egress Congestion State notification threshold on
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* 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a
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* tight loop (e.g. by sending UDP datagrams at "while(1) speed"),
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* and the larger the frame size, the more acute the problem.
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* So we have to find a balance between these factors:
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* - avoiding the device staying congested for a prolonged time (risking
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* the netdev watchdog to fire - see also the tx_timeout module param);
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* - affecting performance of protocols such as TCP, which otherwise
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* behave well under the congestion notification mechanism;
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* - preventing the Tx cores from tightly-looping (as if the congestion
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* threshold was too low to be effective);
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* - running out of memory if the CS threshold is set too high.
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*/
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#define DPAA_CS_THRESHOLD_10G 0x10000000
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/* The size in bytes of the egress Congestion State notification threshold on
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* 10G ports, range 0x1000 .. 0x10000000
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*/
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/* Largest value that the FQD's OAL field can hold */
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#define FSL_QMAN_MAX_OAL 127
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/* Default alignment for start of data in an Rx FD */
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dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
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#ifdef CONFIG_DPAA_ERRATUM_A050385
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/* aligning data start to 64 avoids DMA transaction splits, unless the buffer
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* is crossing a 4k page boundary
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*/
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#define DPAA_FD_DATA_ALIGNMENT (fman_has_errata_a050385() ? 64 : 16)
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/* aligning to 256 avoids DMA transaction splits caused by 4k page boundary
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* crossings; also, all SG fragments except the last must have a size multiple
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* of 256 to avoid DMA transaction splits
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*/
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#define DPAA_A050385_ALIGN 256
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#define DPAA_FD_RX_DATA_ALIGNMENT (fman_has_errata_a050385() ? \
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DPAA_A050385_ALIGN : 16)
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#else
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2016-11-15 10:41:02 +02:00
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#define DPAA_FD_DATA_ALIGNMENT 16
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dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
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#define DPAA_FD_RX_DATA_ALIGNMENT DPAA_FD_DATA_ALIGNMENT
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#endif
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2016-11-15 10:41:02 +02:00
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2018-06-28 15:26:51 +03:00
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/* The DPAA requires 256 bytes reserved and mapped for the SGT */
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#define DPAA_SGT_SIZE 256
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2016-11-15 10:41:02 +02:00
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/* Values for the L3R field of the FM Parse Results
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*/
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/* L3 Type field: First IP Present IPv4 */
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#define FM_L3_PARSE_RESULT_IPV4 0x8000
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/* L3 Type field: First IP Present IPv6 */
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#define FM_L3_PARSE_RESULT_IPV6 0x4000
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/* Values for the L4R field of the FM Parse Results */
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/* L4 Type field: UDP */
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#define FM_L4_PARSE_RESULT_UDP 0x40
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/* L4 Type field: TCP */
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#define FM_L4_PARSE_RESULT_TCP 0x20
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2017-01-26 14:34:02 +02:00
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/* FD status field indicating whether the FM Parser has attempted to validate
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* the L4 csum of the frame.
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* Note that having this bit set doesn't necessarily imply that the checksum
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* is valid. One would have to check the parse results to find that out.
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*/
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#define FM_FD_STAT_L4CV 0x00000004
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2016-11-15 10:41:02 +02:00
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#define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
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#define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */
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#define FSL_DPAA_BPID_INV 0xff
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#define FSL_DPAA_ETH_MAX_BUF_COUNT 128
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#define FSL_DPAA_ETH_REFILL_THRESHOLD 80
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#define DPAA_TX_PRIV_DATA_SIZE 16
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#define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result)
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#define DPAA_TIME_STAMP_SIZE 8
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#define DPAA_HASH_RESULTS_SIZE 8
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2020-11-02 20:34:35 +02:00
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#define DPAA_HWA_SIZE (DPAA_PARSE_RESULTS_SIZE + DPAA_TIME_STAMP_SIZE \
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+ DPAA_HASH_RESULTS_SIZE)
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#define DPAA_RX_PRIV_DATA_DEFAULT_SIZE (DPAA_TX_PRIV_DATA_SIZE + \
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2020-11-25 18:53:31 +02:00
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XDP_PACKET_HEADROOM - DPAA_HWA_SIZE)
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dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
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#ifdef CONFIG_DPAA_ERRATUM_A050385
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2020-11-02 20:34:35 +02:00
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#define DPAA_RX_PRIV_DATA_A050385_SIZE (DPAA_A050385_ALIGN - DPAA_HWA_SIZE)
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#define DPAA_RX_PRIV_DATA_SIZE (fman_has_errata_a050385() ? \
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DPAA_RX_PRIV_DATA_A050385_SIZE : \
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DPAA_RX_PRIV_DATA_DEFAULT_SIZE)
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dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
#else
|
2020-11-02 20:34:35 +02:00
|
|
|
#define DPAA_RX_PRIV_DATA_SIZE DPAA_RX_PRIV_DATA_DEFAULT_SIZE
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
#endif
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2017-08-27 16:13:39 +03:00
|
|
|
#define DPAA_ETH_PCD_RXQ_NUM 128
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
#define DPAA_ENQUEUE_RETRIES 100000
|
|
|
|
|
|
|
|
|
|
enum port_type {RX, TX};
|
|
|
|
|
|
|
|
|
|
struct fm_port_fqs {
|
|
|
|
|
struct dpaa_fq *tx_defq;
|
|
|
|
|
struct dpaa_fq *tx_errq;
|
|
|
|
|
struct dpaa_fq *rx_defq;
|
|
|
|
|
struct dpaa_fq *rx_errq;
|
2017-08-27 16:13:39 +03:00
|
|
|
struct dpaa_fq *rx_pcdq;
|
2016-11-15 10:41:02 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* All the dpa bps in use at any moment */
|
|
|
|
|
static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS];
|
|
|
|
|
|
|
|
|
|
#define DPAA_BP_RAW_SIZE 4096
|
|
|
|
|
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
#ifdef CONFIG_DPAA_ERRATUM_A050385
|
|
|
|
|
#define dpaa_bp_size(raw_size) (SKB_WITH_OVERHEAD(raw_size) & \
|
|
|
|
|
~(DPAA_A050385_ALIGN - 1))
|
|
|
|
|
#else
|
2019-10-31 16:37:48 +02:00
|
|
|
#define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD(raw_size)
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
#endif
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
static int dpaa_max_frm;
|
|
|
|
|
|
|
|
|
|
static int dpaa_rx_extra_headroom;
|
|
|
|
|
|
|
|
|
|
#define dpaa_get_max_mtu() \
|
|
|
|
|
(dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN))
|
|
|
|
|
|
2022-09-02 17:57:36 -04:00
|
|
|
static void dpaa_eth_cgr_set_speed(struct mac_device *mac_dev, int speed);
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
static int dpaa_netdev_init(struct net_device *net_dev,
|
|
|
|
|
const struct net_device_ops *dpaa_ops,
|
|
|
|
|
u16 tx_timeout)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_priv *priv = netdev_priv(net_dev);
|
|
|
|
|
struct device *dev = net_dev->dev.parent;
|
2022-09-02 17:57:33 -04:00
|
|
|
struct mac_device *mac_dev = priv->mac_dev;
|
2016-11-15 10:41:02 +02:00
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
const u8 *mac_addr;
|
|
|
|
|
int i, err;
|
|
|
|
|
|
|
|
|
|
/* Although we access another CPU's private data here
|
|
|
|
|
* we do it at initialization so it is safe
|
|
|
|
|
*/
|
|
|
|
|
for_each_possible_cpu(i) {
|
|
|
|
|
percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
|
|
|
|
|
percpu_priv->net_dev = net_dev;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
net_dev->netdev_ops = dpaa_ops;
|
2022-09-02 17:57:33 -04:00
|
|
|
mac_addr = mac_dev->addr;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2022-10-20 11:50:41 -04:00
|
|
|
net_dev->mem_start = (unsigned long)priv->mac_dev->res->start;
|
|
|
|
|
net_dev->mem_end = (unsigned long)priv->mac_dev->res->end;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
net_dev->min_mtu = ETH_MIN_MTU;
|
|
|
|
|
net_dev->max_mtu = dpaa_get_max_mtu();
|
|
|
|
|
|
|
|
|
|
net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
|
2024-08-29 14:33:37 +02:00
|
|
|
NETIF_F_RXHASH);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA;
|
|
|
|
|
/* The kernels enables GSO automatically, if we declare NETIF_F_SG.
|
|
|
|
|
* For conformity, we'll still declare GSO explicitly.
|
|
|
|
|
*/
|
|
|
|
|
net_dev->features |= NETIF_F_GSO;
|
2017-01-26 14:34:02 +02:00
|
|
|
net_dev->features |= NETIF_F_RXCSUM;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
|
2024-08-29 14:33:37 +02:00
|
|
|
net_dev->lltx = true;
|
2016-11-15 10:41:02 +02:00
|
|
|
/* we do not want shared skbs on TX */
|
|
|
|
|
net_dev->priv_flags &= ~IFF_TX_SKB_SHARING;
|
|
|
|
|
|
|
|
|
|
net_dev->features |= net_dev->hw_features;
|
|
|
|
|
net_dev->vlan_features = net_dev->features;
|
|
|
|
|
|
drivers: net: turn on XDP features
A summary of the flags being set for various drivers is given below.
Note that XDP_F_REDIRECT_TARGET and XDP_F_FRAG_TARGET are features
that can be turned off and on at runtime. This means that these flags
may be set and unset under RTNL lock protection by the driver. Hence,
READ_ONCE must be used by code loading the flag value.
Also, these flags are not used for synchronization against the availability
of XDP resources on a device. It is merely a hint, and hence the read
may race with the actual teardown of XDP resources on the device. This
may change in the future, e.g. operations taking a reference on the XDP
resources of the driver, and in turn inhibiting turning off this flag.
However, for now, it can only be used as a hint to check whether device
supports becoming a redirection target.
Turn 'hw-offload' feature flag on for:
- netronome (nfp)
- netdevsim.
Turn 'native' and 'zerocopy' features flags on for:
- intel (i40e, ice, ixgbe, igc)
- mellanox (mlx5).
- stmmac
- netronome (nfp)
Turn 'native' features flags on for:
- amazon (ena)
- broadcom (bnxt)
- freescale (dpaa, dpaa2, enetc)
- funeth
- intel (igb)
- marvell (mvneta, mvpp2, octeontx2)
- mellanox (mlx4)
- mtk_eth_soc
- qlogic (qede)
- sfc
- socionext (netsec)
- ti (cpsw)
- tap
- tsnep
- veth
- xen
- virtio_net.
Turn 'basic' (tx, pass, aborted and drop) features flags on for:
- netronome (nfp)
- cavium (thunder)
- hyperv.
Turn 'redirect_target' feature flag on for:
- amanzon (ena)
- broadcom (bnxt)
- freescale (dpaa, dpaa2)
- intel (i40e, ice, igb, ixgbe)
- ti (cpsw)
- marvell (mvneta, mvpp2)
- sfc
- socionext (netsec)
- qlogic (qede)
- mellanox (mlx5)
- tap
- veth
- virtio_net
- xen
Reviewed-by: Gerhard Engleder <gerhard@engleder-embedded.com>
Reviewed-by: Simon Horman <simon.horman@corigine.com>
Acked-by: Stanislav Fomichev <sdf@google.com>
Acked-by: Jakub Kicinski <kuba@kernel.org>
Co-developed-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Marek Majtyka <alardam@gmail.com>
Link: https://lore.kernel.org/r/3eca9fafb308462f7edb1f58e451d59209aa07eb.1675245258.git.lorenzo@kernel.org
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2023-02-01 11:24:18 +01:00
|
|
|
net_dev->xdp_features = NETDEV_XDP_ACT_BASIC |
|
|
|
|
|
NETDEV_XDP_ACT_REDIRECT |
|
|
|
|
|
NETDEV_XDP_ACT_NDO_XMIT;
|
|
|
|
|
|
2020-03-05 19:08:58 +02:00
|
|
|
if (is_valid_ether_addr(mac_addr)) {
|
|
|
|
|
memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len);
|
2021-10-04 09:05:21 -07:00
|
|
|
eth_hw_addr_set(net_dev, mac_addr);
|
2020-03-05 19:08:58 +02:00
|
|
|
} else {
|
|
|
|
|
eth_hw_addr_random(net_dev);
|
2022-09-02 17:57:33 -04:00
|
|
|
err = mac_dev->change_addr(mac_dev->fman_mac,
|
2021-10-14 07:24:31 -07:00
|
|
|
(const enet_addr_t *)net_dev->dev_addr);
|
2020-03-05 19:08:58 +02:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(dev, "Failed to set random MAC address\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
dev_info(dev, "Using random MAC address: %pM\n",
|
|
|
|
|
net_dev->dev_addr);
|
|
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2016-11-15 10:41:03 +02:00
|
|
|
net_dev->ethtool_ops = &dpaa_ethtool_ops;
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
net_dev->needed_headroom = priv->tx_headroom;
|
|
|
|
|
net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
|
|
|
|
|
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
/* The rest of the config is filled in by the mac device already */
|
|
|
|
|
mac_dev->phylink_config.dev = &net_dev->dev;
|
|
|
|
|
mac_dev->phylink_config.type = PHYLINK_NETDEV;
|
2022-09-02 17:57:36 -04:00
|
|
|
mac_dev->update_speed = dpaa_eth_cgr_set_speed;
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
mac_dev->phylink = phylink_create(&mac_dev->phylink_config,
|
|
|
|
|
dev_fwnode(mac_dev->dev),
|
|
|
|
|
mac_dev->phy_if,
|
|
|
|
|
mac_dev->phylink_ops);
|
|
|
|
|
if (IS_ERR(mac_dev->phylink)) {
|
|
|
|
|
err = PTR_ERR(mac_dev->phylink);
|
|
|
|
|
dev_err_probe(dev, err, "Could not create phylink\n");
|
|
|
|
|
return err;
|
|
|
|
|
}
|
2022-09-02 17:57:36 -04:00
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
/* start without the RUNNING flag, phylib controls it later */
|
|
|
|
|
netif_carrier_off(net_dev);
|
|
|
|
|
|
|
|
|
|
err = register_netdev(net_dev);
|
|
|
|
|
if (err < 0) {
|
|
|
|
|
dev_err(dev, "register_netdev() = %d\n", err);
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
phylink_destroy(mac_dev->phylink);
|
2016-11-15 10:41:02 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_stop(struct net_device *net_dev)
|
|
|
|
|
{
|
|
|
|
|
struct mac_device *mac_dev;
|
|
|
|
|
struct dpaa_priv *priv;
|
2023-04-20 15:36:07 +03:00
|
|
|
int i, error;
|
|
|
|
|
int err = 0;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
mac_dev = priv->mac_dev;
|
|
|
|
|
|
|
|
|
|
netif_tx_stop_all_queues(net_dev);
|
|
|
|
|
/* Allow the Fman (Tx) port to process in-flight frames before we
|
|
|
|
|
* try switching it off.
|
|
|
|
|
*/
|
2019-10-31 16:37:57 +02:00
|
|
|
msleep(200);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
phylink_stop(mac_dev->phylink);
|
2022-09-02 17:57:32 -04:00
|
|
|
mac_dev->disable(mac_dev->fman_mac);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
|
|
|
|
|
error = fman_port_disable(mac_dev->port[i]);
|
|
|
|
|
if (error)
|
|
|
|
|
err = error;
|
|
|
|
|
}
|
|
|
|
|
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
phylink_disconnect_phy(mac_dev->phylink);
|
2016-11-15 10:41:02 +02:00
|
|
|
net_dev->phydev = NULL;
|
|
|
|
|
|
2019-10-31 16:37:57 +02:00
|
|
|
msleep(200);
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
netdev: pass the stuck queue to the timeout handler
This allows incrementing the correct timeout statistic without any mess.
Down the road, devices can learn to reset just the specific queue.
The patch was generated with the following script:
use strict;
use warnings;
our $^I = '.bak';
my @work = (
["arch/m68k/emu/nfeth.c", "nfeth_tx_timeout"],
["arch/um/drivers/net_kern.c", "uml_net_tx_timeout"],
["arch/um/drivers/vector_kern.c", "vector_net_tx_timeout"],
["arch/xtensa/platforms/iss/network.c", "iss_net_tx_timeout"],
["drivers/char/pcmcia/synclink_cs.c", "hdlcdev_tx_timeout"],
["drivers/infiniband/ulp/ipoib/ipoib_main.c", "ipoib_timeout"],
["drivers/infiniband/ulp/ipoib/ipoib_main.c", "ipoib_timeout"],
["drivers/message/fusion/mptlan.c", "mpt_lan_tx_timeout"],
["drivers/misc/sgi-xp/xpnet.c", "xpnet_dev_tx_timeout"],
["drivers/net/appletalk/cops.c", "cops_timeout"],
["drivers/net/arcnet/arcdevice.h", "arcnet_timeout"],
["drivers/net/arcnet/arcnet.c", "arcnet_timeout"],
["drivers/net/arcnet/com20020.c", "arcnet_timeout"],
["drivers/net/ethernet/3com/3c509.c", "el3_tx_timeout"],
["drivers/net/ethernet/3com/3c515.c", "corkscrew_timeout"],
["drivers/net/ethernet/3com/3c574_cs.c", "el3_tx_timeout"],
["drivers/net/ethernet/3com/3c589_cs.c", "el3_tx_timeout"],
["drivers/net/ethernet/3com/3c59x.c", "vortex_tx_timeout"],
["drivers/net/ethernet/3com/3c59x.c", "vortex_tx_timeout"],
["drivers/net/ethernet/3com/typhoon.c", "typhoon_tx_timeout"],
["drivers/net/ethernet/8390/8390.h", "ei_tx_timeout"],
["drivers/net/ethernet/8390/8390.h", "eip_tx_timeout"],
["drivers/net/ethernet/8390/8390.c", "ei_tx_timeout"],
["drivers/net/ethernet/8390/8390p.c", "eip_tx_timeout"],
["drivers/net/ethernet/8390/ax88796.c", "ax_ei_tx_timeout"],
["drivers/net/ethernet/8390/axnet_cs.c", "axnet_tx_timeout"],
["drivers/net/ethernet/8390/etherh.c", "__ei_tx_timeout"],
["drivers/net/ethernet/8390/hydra.c", "__ei_tx_timeout"],
["drivers/net/ethernet/8390/mac8390.c", "__ei_tx_timeout"],
["drivers/net/ethernet/8390/mcf8390.c", "__ei_tx_timeout"],
["drivers/net/ethernet/8390/lib8390.c", "__ei_tx_timeout"],
["drivers/net/ethernet/8390/ne2k-pci.c", "ei_tx_timeout"],
["drivers/net/ethernet/8390/pcnet_cs.c", "ei_tx_timeout"],
["drivers/net/ethernet/8390/smc-ultra.c", "ei_tx_timeout"],
["drivers/net/ethernet/8390/wd.c", "ei_tx_timeout"],
["drivers/net/ethernet/8390/zorro8390.c", "__ei_tx_timeout"],
["drivers/net/ethernet/adaptec/starfire.c", "tx_timeout"],
["drivers/net/ethernet/agere/et131x.c", "et131x_tx_timeout"],
["drivers/net/ethernet/allwinner/sun4i-emac.c", "emac_timeout"],
["drivers/net/ethernet/alteon/acenic.c", "ace_watchdog"],
["drivers/net/ethernet/amazon/ena/ena_netdev.c", "ena_tx_timeout"],
["drivers/net/ethernet/amd/7990.h", "lance_tx_timeout"],
["drivers/net/ethernet/amd/7990.c", "lance_tx_timeout"],
["drivers/net/ethernet/amd/a2065.c", "lance_tx_timeout"],
["drivers/net/ethernet/amd/am79c961a.c", "am79c961_timeout"],
["drivers/net/ethernet/amd/amd8111e.c", "amd8111e_tx_timeout"],
["drivers/net/ethernet/amd/ariadne.c", "ariadne_tx_timeout"],
["drivers/net/ethernet/amd/atarilance.c", "lance_tx_timeout"],
["drivers/net/ethernet/amd/au1000_eth.c", "au1000_tx_timeout"],
["drivers/net/ethernet/amd/declance.c", "lance_tx_timeout"],
["drivers/net/ethernet/amd/lance.c", "lance_tx_timeout"],
["drivers/net/ethernet/amd/mvme147.c", "lance_tx_timeout"],
["drivers/net/ethernet/amd/ni65.c", "ni65_timeout"],
["drivers/net/ethernet/amd/nmclan_cs.c", "mace_tx_timeout"],
["drivers/net/ethernet/amd/pcnet32.c", "pcnet32_tx_timeout"],
["drivers/net/ethernet/amd/sunlance.c", "lance_tx_timeout"],
["drivers/net/ethernet/amd/xgbe/xgbe-drv.c", "xgbe_tx_timeout"],
["drivers/net/ethernet/apm/xgene-v2/main.c", "xge_timeout"],
["drivers/net/ethernet/apm/xgene/xgene_enet_main.c", "xgene_enet_timeout"],
["drivers/net/ethernet/apple/macmace.c", "mace_tx_timeout"],
["drivers/net/ethernet/atheros/ag71xx.c", "ag71xx_tx_timeout"],
["drivers/net/ethernet/atheros/alx/main.c", "alx_tx_timeout"],
["drivers/net/ethernet/atheros/atl1c/atl1c_main.c", "atl1c_tx_timeout"],
["drivers/net/ethernet/atheros/atl1e/atl1e_main.c", "atl1e_tx_timeout"],
["drivers/net/ethernet/atheros/atlx/atl.c", "atlx_tx_timeout"],
["drivers/net/ethernet/atheros/atlx/atl1.c", "atlx_tx_timeout"],
["drivers/net/ethernet/atheros/atlx/atl2.c", "atl2_tx_timeout"],
["drivers/net/ethernet/broadcom/b44.c", "b44_tx_timeout"],
["drivers/net/ethernet/broadcom/bcmsysport.c", "bcm_sysport_tx_timeout"],
["drivers/net/ethernet/broadcom/bnx2.c", "bnx2_tx_timeout"],
["drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h", "bnx2x_tx_timeout"],
["drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c", "bnx2x_tx_timeout"],
["drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c", "bnx2x_tx_timeout"],
["drivers/net/ethernet/broadcom/bnxt/bnxt.c", "bnxt_tx_timeout"],
["drivers/net/ethernet/broadcom/genet/bcmgenet.c", "bcmgenet_timeout"],
["drivers/net/ethernet/broadcom/sb1250-mac.c", "sbmac_tx_timeout"],
["drivers/net/ethernet/broadcom/tg3.c", "tg3_tx_timeout"],
["drivers/net/ethernet/calxeda/xgmac.c", "xgmac_tx_timeout"],
["drivers/net/ethernet/cavium/liquidio/lio_main.c", "liquidio_tx_timeout"],
["drivers/net/ethernet/cavium/liquidio/lio_vf_main.c", "liquidio_tx_timeout"],
["drivers/net/ethernet/cavium/liquidio/lio_vf_rep.c", "lio_vf_rep_tx_timeout"],
["drivers/net/ethernet/cavium/thunder/nicvf_main.c", "nicvf_tx_timeout"],
["drivers/net/ethernet/cirrus/cs89x0.c", "net_timeout"],
["drivers/net/ethernet/cisco/enic/enic_main.c", "enic_tx_timeout"],
["drivers/net/ethernet/cisco/enic/enic_main.c", "enic_tx_timeout"],
["drivers/net/ethernet/cortina/gemini.c", "gmac_tx_timeout"],
["drivers/net/ethernet/davicom/dm9000.c", "dm9000_timeout"],
["drivers/net/ethernet/dec/tulip/de2104x.c", "de_tx_timeout"],
["drivers/net/ethernet/dec/tulip/tulip_core.c", "tulip_tx_timeout"],
["drivers/net/ethernet/dec/tulip/winbond-840.c", "tx_timeout"],
["drivers/net/ethernet/dlink/dl2k.c", "rio_tx_timeout"],
["drivers/net/ethernet/dlink/sundance.c", "tx_timeout"],
["drivers/net/ethernet/emulex/benet/be_main.c", "be_tx_timeout"],
["drivers/net/ethernet/ethoc.c", "ethoc_tx_timeout"],
["drivers/net/ethernet/faraday/ftgmac100.c", "ftgmac100_tx_timeout"],
["drivers/net/ethernet/fealnx.c", "fealnx_tx_timeout"],
["drivers/net/ethernet/freescale/dpaa/dpaa_eth.c", "dpaa_tx_timeout"],
["drivers/net/ethernet/freescale/fec_main.c", "fec_timeout"],
["drivers/net/ethernet/freescale/fec_mpc52xx.c", "mpc52xx_fec_tx_timeout"],
["drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c", "fs_timeout"],
["drivers/net/ethernet/freescale/gianfar.c", "gfar_timeout"],
["drivers/net/ethernet/freescale/ucc_geth.c", "ucc_geth_timeout"],
["drivers/net/ethernet/fujitsu/fmvj18x_cs.c", "fjn_tx_timeout"],
["drivers/net/ethernet/google/gve/gve_main.c", "gve_tx_timeout"],
["drivers/net/ethernet/hisilicon/hip04_eth.c", "hip04_timeout"],
["drivers/net/ethernet/hisilicon/hix5hd2_gmac.c", "hix5hd2_net_timeout"],
["drivers/net/ethernet/hisilicon/hns/hns_enet.c", "hns_nic_net_timeout"],
["drivers/net/ethernet/hisilicon/hns3/hns3_enet.c", "hns3_nic_net_timeout"],
["drivers/net/ethernet/huawei/hinic/hinic_main.c", "hinic_tx_timeout"],
["drivers/net/ethernet/i825xx/82596.c", "i596_tx_timeout"],
["drivers/net/ethernet/i825xx/ether1.c", "ether1_timeout"],
["drivers/net/ethernet/i825xx/lib82596.c", "i596_tx_timeout"],
["drivers/net/ethernet/i825xx/sun3_82586.c", "sun3_82586_timeout"],
["drivers/net/ethernet/ibm/ehea/ehea_main.c", "ehea_tx_watchdog"],
["drivers/net/ethernet/ibm/emac/core.c", "emac_tx_timeout"],
["drivers/net/ethernet/ibm/emac/core.c", "emac_tx_timeout"],
["drivers/net/ethernet/ibm/ibmvnic.c", "ibmvnic_tx_timeout"],
["drivers/net/ethernet/intel/e100.c", "e100_tx_timeout"],
["drivers/net/ethernet/intel/e1000/e1000_main.c", "e1000_tx_timeout"],
["drivers/net/ethernet/intel/e1000e/netdev.c", "e1000_tx_timeout"],
["drivers/net/ethernet/intel/fm10k/fm10k_netdev.c", "fm10k_tx_timeout"],
["drivers/net/ethernet/intel/i40e/i40e_main.c", "i40e_tx_timeout"],
["drivers/net/ethernet/intel/iavf/iavf_main.c", "iavf_tx_timeout"],
["drivers/net/ethernet/intel/ice/ice_main.c", "ice_tx_timeout"],
["drivers/net/ethernet/intel/ice/ice_main.c", "ice_tx_timeout"],
["drivers/net/ethernet/intel/igb/igb_main.c", "igb_tx_timeout"],
["drivers/net/ethernet/intel/igbvf/netdev.c", "igbvf_tx_timeout"],
["drivers/net/ethernet/intel/ixgb/ixgb_main.c", "ixgb_tx_timeout"],
["drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c", "adapter->netdev->netdev_ops->ndo_tx_timeout(adapter->netdev);"],
["drivers/net/ethernet/intel/ixgbe/ixgbe_main.c", "ixgbe_tx_timeout"],
["drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c", "ixgbevf_tx_timeout"],
["drivers/net/ethernet/jme.c", "jme_tx_timeout"],
["drivers/net/ethernet/korina.c", "korina_tx_timeout"],
["drivers/net/ethernet/lantiq_etop.c", "ltq_etop_tx_timeout"],
["drivers/net/ethernet/marvell/mv643xx_eth.c", "mv643xx_eth_tx_timeout"],
["drivers/net/ethernet/marvell/pxa168_eth.c", "pxa168_eth_tx_timeout"],
["drivers/net/ethernet/marvell/skge.c", "skge_tx_timeout"],
["drivers/net/ethernet/marvell/sky2.c", "sky2_tx_timeout"],
["drivers/net/ethernet/marvell/sky2.c", "sky2_tx_timeout"],
["drivers/net/ethernet/mediatek/mtk_eth_soc.c", "mtk_tx_timeout"],
["drivers/net/ethernet/mellanox/mlx4/en_netdev.c", "mlx4_en_tx_timeout"],
["drivers/net/ethernet/mellanox/mlx4/en_netdev.c", "mlx4_en_tx_timeout"],
["drivers/net/ethernet/mellanox/mlx5/core/en_main.c", "mlx5e_tx_timeout"],
["drivers/net/ethernet/micrel/ks8842.c", "ks8842_tx_timeout"],
["drivers/net/ethernet/micrel/ksz884x.c", "netdev_tx_timeout"],
["drivers/net/ethernet/microchip/enc28j60.c", "enc28j60_tx_timeout"],
["drivers/net/ethernet/microchip/encx24j600.c", "encx24j600_tx_timeout"],
["drivers/net/ethernet/natsemi/sonic.h", "sonic_tx_timeout"],
["drivers/net/ethernet/natsemi/sonic.c", "sonic_tx_timeout"],
["drivers/net/ethernet/natsemi/jazzsonic.c", "sonic_tx_timeout"],
["drivers/net/ethernet/natsemi/macsonic.c", "sonic_tx_timeout"],
["drivers/net/ethernet/natsemi/natsemi.c", "ns_tx_timeout"],
["drivers/net/ethernet/natsemi/ns83820.c", "ns83820_tx_timeout"],
["drivers/net/ethernet/natsemi/xtsonic.c", "sonic_tx_timeout"],
["drivers/net/ethernet/neterion/s2io.h", "s2io_tx_watchdog"],
["drivers/net/ethernet/neterion/s2io.c", "s2io_tx_watchdog"],
["drivers/net/ethernet/neterion/vxge/vxge-main.c", "vxge_tx_watchdog"],
["drivers/net/ethernet/netronome/nfp/nfp_net_common.c", "nfp_net_tx_timeout"],
["drivers/net/ethernet/nvidia/forcedeth.c", "nv_tx_timeout"],
["drivers/net/ethernet/nvidia/forcedeth.c", "nv_tx_timeout"],
["drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c", "pch_gbe_tx_timeout"],
["drivers/net/ethernet/packetengines/hamachi.c", "hamachi_tx_timeout"],
["drivers/net/ethernet/packetengines/yellowfin.c", "yellowfin_tx_timeout"],
["drivers/net/ethernet/pensando/ionic/ionic_lif.c", "ionic_tx_timeout"],
["drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c", "netxen_tx_timeout"],
["drivers/net/ethernet/qlogic/qla3xxx.c", "ql3xxx_tx_timeout"],
["drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c", "qlcnic_tx_timeout"],
["drivers/net/ethernet/qualcomm/emac/emac.c", "emac_tx_timeout"],
["drivers/net/ethernet/qualcomm/qca_spi.c", "qcaspi_netdev_tx_timeout"],
["drivers/net/ethernet/qualcomm/qca_uart.c", "qcauart_netdev_tx_timeout"],
["drivers/net/ethernet/rdc/r6040.c", "r6040_tx_timeout"],
["drivers/net/ethernet/realtek/8139cp.c", "cp_tx_timeout"],
["drivers/net/ethernet/realtek/8139too.c", "rtl8139_tx_timeout"],
["drivers/net/ethernet/realtek/atp.c", "tx_timeout"],
["drivers/net/ethernet/realtek/r8169_main.c", "rtl8169_tx_timeout"],
["drivers/net/ethernet/renesas/ravb_main.c", "ravb_tx_timeout"],
["drivers/net/ethernet/renesas/sh_eth.c", "sh_eth_tx_timeout"],
["drivers/net/ethernet/renesas/sh_eth.c", "sh_eth_tx_timeout"],
["drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c", "sxgbe_tx_timeout"],
["drivers/net/ethernet/seeq/ether3.c", "ether3_timeout"],
["drivers/net/ethernet/seeq/sgiseeq.c", "timeout"],
["drivers/net/ethernet/sfc/efx.c", "efx_watchdog"],
["drivers/net/ethernet/sfc/falcon/efx.c", "ef4_watchdog"],
["drivers/net/ethernet/sgi/ioc3-eth.c", "ioc3_timeout"],
["drivers/net/ethernet/sgi/meth.c", "meth_tx_timeout"],
["drivers/net/ethernet/silan/sc92031.c", "sc92031_tx_timeout"],
["drivers/net/ethernet/sis/sis190.c", "sis190_tx_timeout"],
["drivers/net/ethernet/sis/sis900.c", "sis900_tx_timeout"],
["drivers/net/ethernet/smsc/epic100.c", "epic_tx_timeout"],
["drivers/net/ethernet/smsc/smc911x.c", "smc911x_timeout"],
["drivers/net/ethernet/smsc/smc9194.c", "smc_timeout"],
["drivers/net/ethernet/smsc/smc91c92_cs.c", "smc_tx_timeout"],
["drivers/net/ethernet/smsc/smc91x.c", "smc_timeout"],
["drivers/net/ethernet/stmicro/stmmac/stmmac_main.c", "stmmac_tx_timeout"],
["drivers/net/ethernet/sun/cassini.c", "cas_tx_timeout"],
["drivers/net/ethernet/sun/ldmvsw.c", "sunvnet_tx_timeout_common"],
["drivers/net/ethernet/sun/niu.c", "niu_tx_timeout"],
["drivers/net/ethernet/sun/sunbmac.c", "bigmac_tx_timeout"],
["drivers/net/ethernet/sun/sungem.c", "gem_tx_timeout"],
["drivers/net/ethernet/sun/sunhme.c", "happy_meal_tx_timeout"],
["drivers/net/ethernet/sun/sunqe.c", "qe_tx_timeout"],
["drivers/net/ethernet/sun/sunvnet.c", "sunvnet_tx_timeout_common"],
["drivers/net/ethernet/sun/sunvnet_common.c", "sunvnet_tx_timeout_common"],
["drivers/net/ethernet/sun/sunvnet_common.h", "sunvnet_tx_timeout_common"],
["drivers/net/ethernet/synopsys/dwc-xlgmac-net.c", "xlgmac_tx_timeout"],
["drivers/net/ethernet/ti/cpmac.c", "cpmac_tx_timeout"],
["drivers/net/ethernet/ti/cpsw.c", "cpsw_ndo_tx_timeout"],
["drivers/net/ethernet/ti/cpsw_priv.c", "cpsw_ndo_tx_timeout"],
["drivers/net/ethernet/ti/cpsw_priv.h", "cpsw_ndo_tx_timeout"],
["drivers/net/ethernet/ti/davinci_emac.c", "emac_dev_tx_timeout"],
["drivers/net/ethernet/ti/netcp_core.c", "netcp_ndo_tx_timeout"],
["drivers/net/ethernet/ti/tlan.c", "tlan_tx_timeout"],
["drivers/net/ethernet/toshiba/ps3_gelic_net.h", "gelic_net_tx_timeout"],
["drivers/net/ethernet/toshiba/ps3_gelic_net.c", "gelic_net_tx_timeout"],
["drivers/net/ethernet/toshiba/ps3_gelic_wireless.c", "gelic_net_tx_timeout"],
["drivers/net/ethernet/toshiba/spider_net.c", "spider_net_tx_timeout"],
["drivers/net/ethernet/toshiba/tc35815.c", "tc35815_tx_timeout"],
["drivers/net/ethernet/via/via-rhine.c", "rhine_tx_timeout"],
["drivers/net/ethernet/wiznet/w5100.c", "w5100_tx_timeout"],
["drivers/net/ethernet/wiznet/w5300.c", "w5300_tx_timeout"],
["drivers/net/ethernet/xilinx/xilinx_emaclite.c", "xemaclite_tx_timeout"],
["drivers/net/ethernet/xircom/xirc2ps_cs.c", "xirc_tx_timeout"],
["drivers/net/fjes/fjes_main.c", "fjes_tx_retry"],
["drivers/net/slip/slip.c", "sl_tx_timeout"],
["include/linux/usb/usbnet.h", "usbnet_tx_timeout"],
["drivers/net/usb/aqc111.c", "usbnet_tx_timeout"],
["drivers/net/usb/asix_devices.c", "usbnet_tx_timeout"],
["drivers/net/usb/asix_devices.c", "usbnet_tx_timeout"],
["drivers/net/usb/asix_devices.c", "usbnet_tx_timeout"],
["drivers/net/usb/ax88172a.c", "usbnet_tx_timeout"],
["drivers/net/usb/ax88179_178a.c", "usbnet_tx_timeout"],
["drivers/net/usb/catc.c", "catc_tx_timeout"],
["drivers/net/usb/cdc_mbim.c", "usbnet_tx_timeout"],
["drivers/net/usb/cdc_ncm.c", "usbnet_tx_timeout"],
["drivers/net/usb/dm9601.c", "usbnet_tx_timeout"],
["drivers/net/usb/hso.c", "hso_net_tx_timeout"],
["drivers/net/usb/int51x1.c", "usbnet_tx_timeout"],
["drivers/net/usb/ipheth.c", "ipheth_tx_timeout"],
["drivers/net/usb/kaweth.c", "kaweth_tx_timeout"],
["drivers/net/usb/lan78xx.c", "lan78xx_tx_timeout"],
["drivers/net/usb/mcs7830.c", "usbnet_tx_timeout"],
["drivers/net/usb/pegasus.c", "pegasus_tx_timeout"],
["drivers/net/usb/qmi_wwan.c", "usbnet_tx_timeout"],
["drivers/net/usb/r8152.c", "rtl8152_tx_timeout"],
["drivers/net/usb/rndis_host.c", "usbnet_tx_timeout"],
["drivers/net/usb/rtl8150.c", "rtl8150_tx_timeout"],
["drivers/net/usb/sierra_net.c", "usbnet_tx_timeout"],
["drivers/net/usb/smsc75xx.c", "usbnet_tx_timeout"],
["drivers/net/usb/smsc95xx.c", "usbnet_tx_timeout"],
["drivers/net/usb/sr9700.c", "usbnet_tx_timeout"],
["drivers/net/usb/sr9800.c", "usbnet_tx_timeout"],
["drivers/net/usb/usbnet.c", "usbnet_tx_timeout"],
["drivers/net/vmxnet3/vmxnet3_drv.c", "vmxnet3_tx_timeout"],
["drivers/net/wan/cosa.c", "cosa_net_timeout"],
["drivers/net/wan/farsync.c", "fst_tx_timeout"],
["drivers/net/wan/fsl_ucc_hdlc.c", "uhdlc_tx_timeout"],
["drivers/net/wan/lmc/lmc_main.c", "lmc_driver_timeout"],
["drivers/net/wan/x25_asy.c", "x25_asy_timeout"],
["drivers/net/wimax/i2400m/netdev.c", "i2400m_tx_timeout"],
["drivers/net/wireless/intel/ipw2x00/ipw2100.c", "ipw2100_tx_timeout"],
["drivers/net/wireless/intersil/hostap/hostap_main.c", "prism2_tx_timeout"],
["drivers/net/wireless/intersil/hostap/hostap_main.c", "prism2_tx_timeout"],
["drivers/net/wireless/intersil/hostap/hostap_main.c", "prism2_tx_timeout"],
["drivers/net/wireless/intersil/orinoco/main.c", "orinoco_tx_timeout"],
["drivers/net/wireless/intersil/orinoco/orinoco_usb.c", "orinoco_tx_timeout"],
["drivers/net/wireless/intersil/orinoco/orinoco.h", "orinoco_tx_timeout"],
["drivers/net/wireless/intersil/prism54/islpci_dev.c", "islpci_eth_tx_timeout"],
["drivers/net/wireless/intersil/prism54/islpci_eth.c", "islpci_eth_tx_timeout"],
["drivers/net/wireless/intersil/prism54/islpci_eth.h", "islpci_eth_tx_timeout"],
["drivers/net/wireless/marvell/mwifiex/main.c", "mwifiex_tx_timeout"],
["drivers/net/wireless/quantenna/qtnfmac/core.c", "qtnf_netdev_tx_timeout"],
["drivers/net/wireless/quantenna/qtnfmac/core.h", "qtnf_netdev_tx_timeout"],
["drivers/net/wireless/rndis_wlan.c", "usbnet_tx_timeout"],
["drivers/net/wireless/wl3501_cs.c", "wl3501_tx_timeout"],
["drivers/net/wireless/zydas/zd1201.c", "zd1201_tx_timeout"],
["drivers/s390/net/qeth_core.h", "qeth_tx_timeout"],
["drivers/s390/net/qeth_core_main.c", "qeth_tx_timeout"],
["drivers/s390/net/qeth_l2_main.c", "qeth_tx_timeout"],
["drivers/s390/net/qeth_l2_main.c", "qeth_tx_timeout"],
["drivers/s390/net/qeth_l3_main.c", "qeth_tx_timeout"],
["drivers/s390/net/qeth_l3_main.c", "qeth_tx_timeout"],
["drivers/staging/ks7010/ks_wlan_net.c", "ks_wlan_tx_timeout"],
["drivers/staging/qlge/qlge_main.c", "qlge_tx_timeout"],
["drivers/staging/rtl8192e/rtl8192e/rtl_core.c", "_rtl92e_tx_timeout"],
["drivers/staging/rtl8192u/r8192U_core.c", "tx_timeout"],
["drivers/staging/unisys/visornic/visornic_main.c", "visornic_xmit_timeout"],
["drivers/staging/wlan-ng/p80211netdev.c", "p80211knetdev_tx_timeout"],
["drivers/tty/n_gsm.c", "gsm_mux_net_tx_timeout"],
["drivers/tty/synclink.c", "hdlcdev_tx_timeout"],
["drivers/tty/synclink_gt.c", "hdlcdev_tx_timeout"],
["drivers/tty/synclinkmp.c", "hdlcdev_tx_timeout"],
["net/atm/lec.c", "lec_tx_timeout"],
["net/bluetooth/bnep/netdev.c", "bnep_net_timeout"]
);
for my $p (@work) {
my @pair = @$p;
my $file = $pair[0];
my $func = $pair[1];
print STDERR $file , ": ", $func,"\n";
our @ARGV = ($file);
while (<ARGV>) {
if (m/($func\s*\(struct\s+net_device\s+\*[A-Za-z_]?[A-Za-z-0-9_]*)(\))/) {
print STDERR "found $1+$2 in $file\n";
}
if (s/($func\s*\(struct\s+net_device\s+\*[A-Za-z_]?[A-Za-z-0-9_]*)(\))/$1, unsigned int txqueue$2/) {
print STDERR "$func found in $file\n";
}
print;
}
}
where the list of files and functions is simply from:
git grep ndo_tx_timeout, with manual addition of headers
in the rare cases where the function is from a header,
then manually changing the few places which actually
call ndo_tx_timeout.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Heiner Kallweit <hkallweit1@gmail.com>
Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Acked-by: Shannon Nelson <snelson@pensando.io>
Reviewed-by: Martin Habets <mhabets@solarflare.com>
changes from v9:
fixup a forward declaration
changes from v9:
more leftovers from v3 change
changes from v8:
fix up a missing direct call to timeout
rebased on net-next
changes from v7:
fixup leftovers from v3 change
changes from v6:
fix typo in rtl driver
changes from v5:
add missing files (allow any net device argument name)
changes from v4:
add a missing driver header
changes from v3:
change queue # to unsigned
Changes from v2:
added headers
Changes from v1:
Fix errors found by kbuild:
generalize the pattern a bit, to pick up
a couple of instances missed by the previous
version.
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-12-10 09:23:51 -05:00
|
|
|
static void dpaa_tx_timeout(struct net_device *net_dev, unsigned int txqueue)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
const struct dpaa_priv *priv;
|
|
|
|
|
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
percpu_priv = this_cpu_ptr(priv->percpu_priv);
|
|
|
|
|
|
|
|
|
|
netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n",
|
|
|
|
|
jiffies_to_msecs(jiffies - dev_trans_start(net_dev)));
|
|
|
|
|
|
|
|
|
|
percpu_priv->stats.tx_errors++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Calculates the statistics for the given device by adding the statistics
|
|
|
|
|
* collected by each CPU.
|
|
|
|
|
*/
|
2017-01-06 19:12:52 -08:00
|
|
|
static void dpaa_get_stats64(struct net_device *net_dev,
|
|
|
|
|
struct rtnl_link_stats64 *s)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64);
|
|
|
|
|
struct dpaa_priv *priv = netdev_priv(net_dev);
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
u64 *netstats = (u64 *)s;
|
|
|
|
|
u64 *cpustats;
|
|
|
|
|
int i, j;
|
|
|
|
|
|
|
|
|
|
for_each_possible_cpu(i) {
|
|
|
|
|
percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
|
|
|
|
|
|
|
|
|
|
cpustats = (u64 *)&percpu_priv->stats;
|
|
|
|
|
|
|
|
|
|
/* add stats from all CPUs */
|
|
|
|
|
for (j = 0; j < numstats; j++)
|
|
|
|
|
netstats[j] += cpustats[j];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-07 10:15:17 +02:00
|
|
|
static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
|
2017-08-07 10:15:32 +02:00
|
|
|
void *type_data)
|
2016-07-25 16:54:56 +03:00
|
|
|
{
|
|
|
|
|
struct dpaa_priv *priv = netdev_priv(net_dev);
|
2024-07-14 01:53:33 +03:00
|
|
|
int num_txqs_per_tc = dpaa_num_txqs_per_tc();
|
2017-08-07 10:15:32 +02:00
|
|
|
struct tc_mqprio_qopt *mqprio = type_data;
|
2017-03-15 10:39:25 -07:00
|
|
|
u8 num_tc;
|
2016-07-25 16:54:56 +03:00
|
|
|
int i;
|
|
|
|
|
|
2017-11-06 07:23:42 +01:00
|
|
|
if (type != TC_SETUP_QDISC_MQPRIO)
|
2017-08-07 10:15:31 +02:00
|
|
|
return -EOPNOTSUPP;
|
2016-07-25 16:54:56 +03:00
|
|
|
|
2017-08-07 10:15:32 +02:00
|
|
|
mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
|
|
|
|
|
num_tc = mqprio->num_tc;
|
2017-03-15 10:39:25 -07:00
|
|
|
|
|
|
|
|
if (num_tc == priv->num_tc)
|
2016-07-25 16:54:56 +03:00
|
|
|
return 0;
|
|
|
|
|
|
2017-03-15 10:39:25 -07:00
|
|
|
if (!num_tc) {
|
2016-07-25 16:54:56 +03:00
|
|
|
netdev_reset_tc(net_dev);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-15 10:39:25 -07:00
|
|
|
if (num_tc > DPAA_TC_NUM) {
|
2016-07-25 16:54:56 +03:00
|
|
|
netdev_err(net_dev, "Too many traffic classes: max %d supported.\n",
|
|
|
|
|
DPAA_TC_NUM);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-15 10:39:25 -07:00
|
|
|
netdev_set_num_tc(net_dev, num_tc);
|
2016-07-25 16:54:56 +03:00
|
|
|
|
2017-03-15 10:39:25 -07:00
|
|
|
for (i = 0; i < num_tc; i++)
|
2024-07-14 01:53:33 +03:00
|
|
|
netdev_set_tc_queue(net_dev, i, num_txqs_per_tc,
|
|
|
|
|
i * num_txqs_per_tc);
|
2016-07-25 16:54:56 +03:00
|
|
|
|
|
|
|
|
out:
|
2017-03-15 10:39:25 -07:00
|
|
|
priv->num_tc = num_tc ? : 1;
|
2024-07-14 01:53:33 +03:00
|
|
|
netif_set_real_num_tx_queues(net_dev, priv->num_tc * num_txqs_per_tc);
|
2016-07-25 16:54:56 +03:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_eth_data *eth_data;
|
2017-10-16 21:36:07 +03:00
|
|
|
struct device *dpaa_dev;
|
2016-11-15 10:41:02 +02:00
|
|
|
struct mac_device *mac_dev;
|
|
|
|
|
|
|
|
|
|
dpaa_dev = &pdev->dev;
|
|
|
|
|
eth_data = dpaa_dev->platform_data;
|
2017-10-16 21:36:07 +03:00
|
|
|
if (!eth_data) {
|
|
|
|
|
dev_err(dpaa_dev, "eth_data missing\n");
|
2016-11-15 10:41:02 +02:00
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
|
}
|
2017-10-16 21:36:07 +03:00
|
|
|
mac_dev = eth_data->mac_dev;
|
2016-11-15 10:41:02 +02:00
|
|
|
if (!mac_dev) {
|
2017-10-16 21:36:07 +03:00
|
|
|
dev_err(dpaa_dev, "mac_dev missing\n");
|
2016-11-15 10:41:02 +02:00
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return mac_dev;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_set_mac_address(struct net_device *net_dev, void *addr)
|
|
|
|
|
{
|
|
|
|
|
const struct dpaa_priv *priv;
|
|
|
|
|
struct mac_device *mac_dev;
|
|
|
|
|
struct sockaddr old_addr;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
|
|
|
|
|
memcpy(old_addr.sa_data, net_dev->dev_addr, ETH_ALEN);
|
|
|
|
|
|
|
|
|
|
err = eth_mac_addr(net_dev, addr);
|
|
|
|
|
if (err < 0) {
|
|
|
|
|
netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mac_dev = priv->mac_dev;
|
|
|
|
|
|
|
|
|
|
err = mac_dev->change_addr(mac_dev->fman_mac,
|
2021-10-14 07:24:31 -07:00
|
|
|
(const enet_addr_t *)net_dev->dev_addr);
|
2016-11-15 10:41:02 +02:00
|
|
|
if (err < 0) {
|
|
|
|
|
netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n",
|
|
|
|
|
err);
|
|
|
|
|
/* reverting to previous address */
|
|
|
|
|
eth_mac_addr(net_dev, &old_addr);
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2024-10-07 16:17:12 +02:00
|
|
|
static int dpaa_addr_sync(struct net_device *net_dev, const u8 *addr)
|
|
|
|
|
{
|
|
|
|
|
const struct dpaa_priv *priv = netdev_priv(net_dev);
|
|
|
|
|
|
|
|
|
|
return priv->mac_dev->add_hash_mac_addr(priv->mac_dev->fman_mac,
|
|
|
|
|
(enet_addr_t *)addr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_addr_unsync(struct net_device *net_dev, const u8 *addr)
|
|
|
|
|
{
|
|
|
|
|
const struct dpaa_priv *priv = netdev_priv(net_dev);
|
|
|
|
|
|
|
|
|
|
return priv->mac_dev->remove_hash_mac_addr(priv->mac_dev->fman_mac,
|
|
|
|
|
(enet_addr_t *)addr);
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
static void dpaa_set_rx_mode(struct net_device *net_dev)
|
|
|
|
|
{
|
|
|
|
|
const struct dpaa_priv *priv;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
|
|
|
|
|
if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) {
|
|
|
|
|
priv->mac_dev->promisc = !priv->mac_dev->promisc;
|
|
|
|
|
err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac,
|
|
|
|
|
priv->mac_dev->promisc);
|
|
|
|
|
if (err < 0)
|
|
|
|
|
netif_err(priv, drv, net_dev,
|
|
|
|
|
"mac_dev->set_promisc() = %d\n",
|
|
|
|
|
err);
|
|
|
|
|
}
|
|
|
|
|
|
2018-02-26 11:24:04 -06:00
|
|
|
if (!!(net_dev->flags & IFF_ALLMULTI) != priv->mac_dev->allmulti) {
|
|
|
|
|
priv->mac_dev->allmulti = !priv->mac_dev->allmulti;
|
|
|
|
|
err = priv->mac_dev->set_allmulti(priv->mac_dev->fman_mac,
|
|
|
|
|
priv->mac_dev->allmulti);
|
|
|
|
|
if (err < 0)
|
|
|
|
|
netif_err(priv, drv, net_dev,
|
|
|
|
|
"mac_dev->set_allmulti() = %d\n",
|
|
|
|
|
err);
|
|
|
|
|
}
|
|
|
|
|
|
2024-10-07 16:17:12 +02:00
|
|
|
err = __dev_mc_sync(net_dev, dpaa_addr_sync, dpaa_addr_unsync);
|
2016-11-15 10:41:02 +02:00
|
|
|
if (err < 0)
|
2024-10-07 16:17:12 +02:00
|
|
|
netif_err(priv, drv, net_dev, "dpaa_addr_sync() = %d\n",
|
2016-11-15 10:41:02 +02:00
|
|
|
err);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct dpaa_bp *dpaa_bpid2pool(int bpid)
|
|
|
|
|
{
|
|
|
|
|
if (WARN_ON(bpid < 0 || bpid >= BM_MAX_NUM_OF_POOLS))
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
return dpaa_bp_array[bpid];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* checks if this bpool is already allocated */
|
|
|
|
|
static bool dpaa_bpid2pool_use(int bpid)
|
|
|
|
|
{
|
|
|
|
|
if (dpaa_bpid2pool(bpid)) {
|
2019-08-03 00:47:59 +08:00
|
|
|
refcount_inc(&dpaa_bp_array[bpid]->refs);
|
2016-11-15 10:41:02 +02:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* called only once per bpid by dpaa_bp_alloc_pool() */
|
|
|
|
|
static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp)
|
|
|
|
|
{
|
|
|
|
|
dpaa_bp_array[bpid] = dpaa_bp;
|
2019-08-03 00:47:59 +08:00
|
|
|
refcount_set(&dpaa_bp->refs, 1);
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp)
|
|
|
|
|
{
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (dpaa_bp->size == 0 || dpaa_bp->config_count == 0) {
|
|
|
|
|
pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n",
|
|
|
|
|
__func__);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If the pool is already specified, we only create one per bpid */
|
|
|
|
|
if (dpaa_bp->bpid != FSL_DPAA_BPID_INV &&
|
|
|
|
|
dpaa_bpid2pool_use(dpaa_bp->bpid))
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) {
|
|
|
|
|
dpaa_bp->pool = bman_new_pool();
|
|
|
|
|
if (!dpaa_bp->pool) {
|
|
|
|
|
pr_err("%s: bman_new_pool() failed\n",
|
|
|
|
|
__func__);
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dpaa_bp->seed_cb) {
|
|
|
|
|
err = dpaa_bp->seed_cb(dpaa_bp);
|
|
|
|
|
if (err)
|
|
|
|
|
goto pool_seed_failed;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
pool_seed_failed:
|
|
|
|
|
pr_err("%s: pool seeding failed\n", __func__);
|
|
|
|
|
bman_free_pool(dpaa_bp->pool);
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* remove and free all the buffers from the given buffer pool */
|
|
|
|
|
static void dpaa_bp_drain(struct dpaa_bp *bp)
|
|
|
|
|
{
|
|
|
|
|
u8 num = 8;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
struct bm_buffer bmb[8];
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
ret = bman_acquire(bp->pool, bmb, num);
|
|
|
|
|
if (ret < 0) {
|
|
|
|
|
if (num == 8) {
|
|
|
|
|
/* we have less than 8 buffers left;
|
|
|
|
|
* drain them one by one
|
|
|
|
|
*/
|
|
|
|
|
num = 1;
|
|
|
|
|
ret = 1;
|
|
|
|
|
continue;
|
|
|
|
|
} else {
|
|
|
|
|
/* Pool is fully drained */
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (bp->free_buf_cb)
|
|
|
|
|
for (i = 0; i < num; i++)
|
|
|
|
|
bp->free_buf_cb(bp, &bmb[i]);
|
|
|
|
|
} while (ret > 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dpaa_bp_free(struct dpaa_bp *dpaa_bp)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid);
|
|
|
|
|
|
|
|
|
|
/* the mapping between bpid and dpaa_bp is done very late in the
|
|
|
|
|
* allocation procedure; if something failed before the mapping, the bp
|
|
|
|
|
* was not configured, therefore we don't need the below instructions
|
|
|
|
|
*/
|
|
|
|
|
if (!bp)
|
|
|
|
|
return;
|
|
|
|
|
|
2019-08-03 00:47:59 +08:00
|
|
|
if (!refcount_dec_and_test(&bp->refs))
|
2016-11-15 10:41:02 +02:00
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
if (bp->free_buf_cb)
|
|
|
|
|
dpaa_bp_drain(bp);
|
|
|
|
|
|
|
|
|
|
dpaa_bp_array[bp->bpid] = NULL;
|
|
|
|
|
bman_free_pool(bp->pool);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dpaa_bps_free(struct dpaa_priv *priv)
|
|
|
|
|
{
|
2019-10-31 16:37:47 +02:00
|
|
|
dpaa_bp_free(priv->dpaa_bp);
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Use multiple WQs for FQ assignment:
|
|
|
|
|
* - Tx Confirmation queues go to WQ1.
|
2016-07-25 16:38:21 +03:00
|
|
|
* - Rx Error and Tx Error queues go to WQ5 (giving them a better chance
|
|
|
|
|
* to be scheduled, in case there are many more FQs in WQ6).
|
|
|
|
|
* - Rx Default goes to WQ6.
|
|
|
|
|
* - Tx queues go to different WQs depending on their priority. Equal
|
|
|
|
|
* chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and
|
|
|
|
|
* WQ0 (highest priority).
|
2016-11-15 10:41:02 +02:00
|
|
|
* This ensures that Tx-confirmed buffers are timely released. In particular,
|
|
|
|
|
* it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they
|
|
|
|
|
* are greatly outnumbered by other FQs in the system, while
|
|
|
|
|
* dequeue scheduling is round-robin.
|
|
|
|
|
*/
|
2016-07-25 16:38:21 +03:00
|
|
|
static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
switch (fq->fq_type) {
|
|
|
|
|
case FQ_TYPE_TX_CONFIRM:
|
|
|
|
|
case FQ_TYPE_TX_CONF_MQ:
|
|
|
|
|
fq->wq = 1;
|
|
|
|
|
break;
|
|
|
|
|
case FQ_TYPE_RX_ERROR:
|
|
|
|
|
case FQ_TYPE_TX_ERROR:
|
2016-07-25 16:38:21 +03:00
|
|
|
fq->wq = 5;
|
2016-11-15 10:41:02 +02:00
|
|
|
break;
|
|
|
|
|
case FQ_TYPE_RX_DEFAULT:
|
2017-08-27 16:13:39 +03:00
|
|
|
case FQ_TYPE_RX_PCD:
|
2016-07-25 16:38:21 +03:00
|
|
|
fq->wq = 6;
|
|
|
|
|
break;
|
2016-11-15 10:41:02 +02:00
|
|
|
case FQ_TYPE_TX:
|
2024-07-14 01:53:33 +03:00
|
|
|
switch (idx / dpaa_num_txqs_per_tc()) {
|
2016-07-25 16:38:21 +03:00
|
|
|
case 0:
|
|
|
|
|
/* Low priority (best effort) */
|
|
|
|
|
fq->wq = 6;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
/* Medium priority */
|
|
|
|
|
fq->wq = 2;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
/* High priority */
|
|
|
|
|
fq->wq = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
/* Very high priority */
|
|
|
|
|
fq->wq = 0;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2024-07-14 01:53:33 +03:00
|
|
|
WARN(1, "Too many TX FQs: more than %zu!\n",
|
|
|
|
|
dpaa_max_num_txqs());
|
2016-07-25 16:38:21 +03:00
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
WARN(1, "Invalid FQ type %d for FQID %d!\n",
|
|
|
|
|
fq->fq_type, fq->fqid);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct dpaa_fq *dpaa_fq_alloc(struct device *dev,
|
|
|
|
|
u32 start, u32 count,
|
|
|
|
|
struct list_head *list,
|
|
|
|
|
enum dpaa_fq_type fq_type)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_fq *dpaa_fq;
|
|
|
|
|
int i;
|
|
|
|
|
|
treewide: devm_kzalloc() -> devm_kcalloc()
The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc().
This patch replaces cases of:
devm_kzalloc(handle, a * b, gfp)
with:
devm_kcalloc(handle, a * b, gfp)
as well as handling cases of:
devm_kzalloc(handle, a * b * c, gfp)
with:
devm_kzalloc(handle, array3_size(a, b, c), gfp)
as it's slightly less ugly than:
devm_kcalloc(handle, array_size(a, b), c, gfp)
This does, however, attempt to ignore constant size factors like:
devm_kzalloc(handle, 4 * 1024, gfp)
though any constants defined via macros get caught up in the conversion.
Any factors with a sizeof() of "unsigned char", "char", and "u8" were
dropped, since they're redundant.
Some manual whitespace fixes were needed in this patch, as Coccinelle
really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...".
The Coccinelle script used for this was:
// Fix redundant parens around sizeof().
@@
expression HANDLE;
type TYPE;
expression THING, E;
@@
(
devm_kzalloc(HANDLE,
- (sizeof(TYPE)) * E
+ sizeof(TYPE) * E
, ...)
|
devm_kzalloc(HANDLE,
- (sizeof(THING)) * E
+ sizeof(THING) * E
, ...)
)
// Drop single-byte sizes and redundant parens.
@@
expression HANDLE;
expression COUNT;
typedef u8;
typedef __u8;
@@
(
devm_kzalloc(HANDLE,
- sizeof(u8) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(__u8) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(char) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(unsigned char) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(u8) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(__u8) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(char) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(unsigned char) * COUNT
+ COUNT
, ...)
)
// 2-factor product with sizeof(type/expression) and identifier or constant.
@@
expression HANDLE;
type TYPE;
expression THING;
identifier COUNT_ID;
constant COUNT_CONST;
@@
(
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (COUNT_ID)
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * COUNT_ID
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (COUNT_CONST)
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * COUNT_CONST
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (COUNT_ID)
+ COUNT_ID, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * COUNT_ID
+ COUNT_ID, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (COUNT_CONST)
+ COUNT_CONST, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * COUNT_CONST
+ COUNT_CONST, sizeof(THING)
, ...)
)
// 2-factor product, only identifiers.
@@
expression HANDLE;
identifier SIZE, COUNT;
@@
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- SIZE * COUNT
+ COUNT, SIZE
, ...)
// 3-factor product with 1 sizeof(type) or sizeof(expression), with
// redundant parens removed.
@@
expression HANDLE;
expression THING;
identifier STRIDE, COUNT;
type TYPE;
@@
(
devm_kzalloc(HANDLE,
- sizeof(TYPE) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
)
// 3-factor product with 2 sizeof(variable), with redundant parens removed.
@@
expression HANDLE;
expression THING1, THING2;
identifier COUNT;
type TYPE1, TYPE2;
@@
(
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(TYPE2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
)
// 3-factor product, only identifiers, with redundant parens removed.
@@
expression HANDLE;
identifier STRIDE, SIZE, COUNT;
@@
(
devm_kzalloc(HANDLE,
- (COUNT) * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
)
// Any remaining multi-factor products, first at least 3-factor products,
// when they're not all constants...
@@
expression HANDLE;
expression E1, E2, E3;
constant C1, C2, C3;
@@
(
devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
devm_kzalloc(HANDLE,
- (E1) * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- (E1) * (E2) * E3
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- (E1) * (E2) * (E3)
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- E1 * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
)
// And then all remaining 2 factors products when they're not all constants,
// keeping sizeof() as the second factor argument.
@@
expression HANDLE;
expression THING, E1, E2;
type TYPE;
constant C1, C2, C3;
@@
(
devm_kzalloc(HANDLE, sizeof(THING) * C2, ...)
|
devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...)
|
devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
devm_kzalloc(HANDLE, C1 * C2, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (E2)
+ E2, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * E2
+ E2, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (E2)
+ E2, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * E2
+ E2, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- (E1) * E2
+ E1, E2
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- (E1) * (E2)
+ E1, E2
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- E1 * E2
+ E1, E2
, ...)
)
Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-12 14:07:58 -07:00
|
|
|
dpaa_fq = devm_kcalloc(dev, count, sizeof(*dpaa_fq),
|
2016-11-15 10:41:02 +02:00
|
|
|
GFP_KERNEL);
|
|
|
|
|
if (!dpaa_fq)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
|
dpaa_fq[i].fq_type = fq_type;
|
|
|
|
|
dpaa_fq[i].fqid = start ? start + i : 0;
|
|
|
|
|
list_add_tail(&dpaa_fq[i].list, list);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++)
|
2016-07-25 16:38:21 +03:00
|
|
|
dpaa_assign_wq(dpaa_fq + i, i);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
return dpaa_fq;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list,
|
|
|
|
|
struct fm_port_fqs *port_fqs)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_fq *dpaa_fq;
|
2017-08-27 16:13:39 +03:00
|
|
|
u32 fq_base, fq_base_aligned, i;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR);
|
|
|
|
|
if (!dpaa_fq)
|
|
|
|
|
goto fq_alloc_failed;
|
|
|
|
|
|
|
|
|
|
port_fqs->rx_errq = &dpaa_fq[0];
|
|
|
|
|
|
|
|
|
|
dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT);
|
|
|
|
|
if (!dpaa_fq)
|
|
|
|
|
goto fq_alloc_failed;
|
|
|
|
|
|
|
|
|
|
port_fqs->rx_defq = &dpaa_fq[0];
|
|
|
|
|
|
2017-08-27 16:13:39 +03:00
|
|
|
/* the PCD FQIDs range needs to be aligned for correct operation */
|
|
|
|
|
if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM))
|
|
|
|
|
goto fq_alloc_failed;
|
|
|
|
|
|
|
|
|
|
fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM);
|
|
|
|
|
|
|
|
|
|
for (i = fq_base; i < fq_base_aligned; i++)
|
|
|
|
|
qman_release_fqid(i);
|
|
|
|
|
|
|
|
|
|
for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM;
|
|
|
|
|
i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++)
|
|
|
|
|
qman_release_fqid(i);
|
|
|
|
|
|
|
|
|
|
dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM,
|
|
|
|
|
list, FQ_TYPE_RX_PCD);
|
|
|
|
|
if (!dpaa_fq)
|
|
|
|
|
goto fq_alloc_failed;
|
|
|
|
|
|
|
|
|
|
port_fqs->rx_pcdq = &dpaa_fq[0];
|
|
|
|
|
|
2024-07-14 01:53:33 +03:00
|
|
|
if (!dpaa_fq_alloc(dev, 0, dpaa_max_num_txqs(), list,
|
|
|
|
|
FQ_TYPE_TX_CONF_MQ))
|
2016-11-15 10:41:02 +02:00
|
|
|
goto fq_alloc_failed;
|
|
|
|
|
|
|
|
|
|
dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR);
|
|
|
|
|
if (!dpaa_fq)
|
|
|
|
|
goto fq_alloc_failed;
|
|
|
|
|
|
|
|
|
|
port_fqs->tx_errq = &dpaa_fq[0];
|
|
|
|
|
|
|
|
|
|
dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM);
|
|
|
|
|
if (!dpaa_fq)
|
|
|
|
|
goto fq_alloc_failed;
|
|
|
|
|
|
|
|
|
|
port_fqs->tx_defq = &dpaa_fq[0];
|
|
|
|
|
|
2024-07-14 01:53:33 +03:00
|
|
|
if (!dpaa_fq_alloc(dev, 0, dpaa_max_num_txqs(), list, FQ_TYPE_TX))
|
2016-11-15 10:41:02 +02:00
|
|
|
goto fq_alloc_failed;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
fq_alloc_failed:
|
|
|
|
|
dev_err(dev, "dpaa_fq_alloc() failed\n");
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static u32 rx_pool_channel;
|
|
|
|
|
static DEFINE_SPINLOCK(rx_pool_channel_init);
|
|
|
|
|
|
|
|
|
|
static int dpaa_get_channel(void)
|
|
|
|
|
{
|
|
|
|
|
spin_lock(&rx_pool_channel_init);
|
|
|
|
|
if (!rx_pool_channel) {
|
|
|
|
|
u32 pool;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = qman_alloc_pool(&pool);
|
|
|
|
|
|
|
|
|
|
if (!ret)
|
|
|
|
|
rx_pool_channel = pool;
|
|
|
|
|
}
|
|
|
|
|
spin_unlock(&rx_pool_channel_init);
|
|
|
|
|
if (!rx_pool_channel)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
return rx_pool_channel;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dpaa_release_channel(void)
|
|
|
|
|
{
|
|
|
|
|
qman_release_pool(rx_pool_channel);
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 16:37:59 +02:00
|
|
|
static void dpaa_eth_add_channel(u16 channel, struct device *dev)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel);
|
|
|
|
|
const cpumask_t *cpus = qman_affine_cpus();
|
|
|
|
|
struct qman_portal *portal;
|
|
|
|
|
int cpu;
|
|
|
|
|
|
2019-05-27 15:24:05 +03:00
|
|
|
for_each_cpu_and(cpu, cpus, cpu_online_mask) {
|
2016-11-15 10:41:02 +02:00
|
|
|
portal = qman_get_affine_portal(cpu);
|
|
|
|
|
qman_p_static_dequeue_add(portal, pool);
|
2019-10-31 16:37:59 +02:00
|
|
|
qman_start_using_portal(portal, dev);
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Congestion group state change notification callback.
|
|
|
|
|
* Stops the device's egress queues while they are congested and
|
|
|
|
|
* wakes them upon exiting congested state.
|
|
|
|
|
* Also updates some CGR-related stats.
|
|
|
|
|
*/
|
|
|
|
|
static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr,
|
|
|
|
|
int congested)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_priv *priv = (struct dpaa_priv *)container_of(cgr,
|
|
|
|
|
struct dpaa_priv, cgr_data.cgr);
|
|
|
|
|
|
2016-11-15 10:41:04 +02:00
|
|
|
if (congested) {
|
|
|
|
|
priv->cgr_data.congestion_start_jiffies = jiffies;
|
2016-11-15 10:41:02 +02:00
|
|
|
netif_tx_stop_all_queues(priv->net_dev);
|
2016-11-15 10:41:04 +02:00
|
|
|
priv->cgr_data.cgr_congested_count++;
|
|
|
|
|
} else {
|
|
|
|
|
priv->cgr_data.congested_jiffies +=
|
|
|
|
|
(jiffies - priv->cgr_data.congestion_start_jiffies);
|
2016-11-15 10:41:02 +02:00
|
|
|
netif_tx_wake_all_queues(priv->net_dev);
|
2016-11-15 10:41:04 +02:00
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_eth_cgr_init(struct dpaa_priv *priv)
|
|
|
|
|
{
|
|
|
|
|
struct qm_mcc_initcgr initcgr;
|
|
|
|
|
u32 cs_th;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid);
|
|
|
|
|
if (err < 0) {
|
|
|
|
|
if (netif_msg_drv(priv))
|
|
|
|
|
pr_err("%s: Error %d allocating CGR ID\n",
|
|
|
|
|
__func__, err);
|
|
|
|
|
goto out_error;
|
|
|
|
|
}
|
|
|
|
|
priv->cgr_data.cgr.cb = dpaa_eth_cgscn;
|
|
|
|
|
|
|
|
|
|
/* Enable Congestion State Change Notifications and CS taildrop */
|
2017-01-04 13:21:30 +02:00
|
|
|
memset(&initcgr, 0, sizeof(initcgr));
|
2016-12-15 15:13:04 +02:00
|
|
|
initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES);
|
2016-11-15 10:41:02 +02:00
|
|
|
initcgr.cgr.cscn_en = QM_CGR_EN;
|
|
|
|
|
|
2022-09-02 17:57:36 -04:00
|
|
|
/* Set different thresholds based on the configured MAC speed.
|
|
|
|
|
* This may turn suboptimal if the MAC is reconfigured at another
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
* speed, so MACs must call dpaa_eth_cgr_set_speed in their link_up
|
2022-09-02 17:57:36 -04:00
|
|
|
* callback.
|
2016-11-15 10:41:02 +02:00
|
|
|
*/
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
if (priv->mac_dev->phylink_config.mac_capabilities & MAC_10000FD)
|
2016-11-15 10:41:02 +02:00
|
|
|
cs_th = DPAA_CS_THRESHOLD_10G;
|
|
|
|
|
else
|
|
|
|
|
cs_th = DPAA_CS_THRESHOLD_1G;
|
|
|
|
|
qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
|
|
|
|
|
|
2016-12-15 15:13:04 +02:00
|
|
|
initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
|
2016-11-15 10:41:02 +02:00
|
|
|
initcgr.cgr.cstd_en = QM_CGR_EN;
|
|
|
|
|
|
|
|
|
|
err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT,
|
|
|
|
|
&initcgr);
|
|
|
|
|
if (err < 0) {
|
|
|
|
|
if (netif_msg_drv(priv))
|
|
|
|
|
pr_err("%s: Error %d creating CGR with ID %d\n",
|
|
|
|
|
__func__, err, priv->cgr_data.cgr.cgrid);
|
|
|
|
|
qman_release_cgrid(priv->cgr_data.cgr.cgrid);
|
|
|
|
|
goto out_error;
|
|
|
|
|
}
|
|
|
|
|
if (netif_msg_drv(priv))
|
|
|
|
|
pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n",
|
|
|
|
|
priv->cgr_data.cgr.cgrid, priv->mac_dev->addr,
|
|
|
|
|
priv->cgr_data.cgr.chan);
|
|
|
|
|
|
|
|
|
|
out_error:
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2022-09-02 17:57:36 -04:00
|
|
|
static void dpaa_eth_cgr_set_speed(struct mac_device *mac_dev, int speed)
|
|
|
|
|
{
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
struct net_device *net_dev = to_net_dev(mac_dev->phylink_config.dev);
|
2022-09-02 17:57:36 -04:00
|
|
|
struct dpaa_priv *priv = netdev_priv(net_dev);
|
|
|
|
|
struct qm_mcc_initcgr opts = { };
|
|
|
|
|
u32 cs_th;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
opts.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES);
|
|
|
|
|
switch (speed) {
|
|
|
|
|
case SPEED_10000:
|
|
|
|
|
cs_th = DPAA_CS_THRESHOLD_10G;
|
|
|
|
|
break;
|
|
|
|
|
case SPEED_1000:
|
|
|
|
|
default:
|
|
|
|
|
cs_th = DPAA_CS_THRESHOLD_1G;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
qm_cgr_cs_thres_set64(&opts.cgr.cs_thres, cs_th, 1);
|
|
|
|
|
|
|
|
|
|
err = qman_update_cgr_safe(&priv->cgr_data.cgr, &opts);
|
|
|
|
|
if (err)
|
|
|
|
|
netdev_err(net_dev, "could not update speed: %d\n", err);
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
static inline void dpaa_setup_ingress(const struct dpaa_priv *priv,
|
|
|
|
|
struct dpaa_fq *fq,
|
|
|
|
|
const struct qman_fq *template)
|
|
|
|
|
{
|
|
|
|
|
fq->fq_base = *template;
|
|
|
|
|
fq->net_dev = priv->net_dev;
|
|
|
|
|
|
|
|
|
|
fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE;
|
|
|
|
|
fq->channel = priv->channel;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void dpaa_setup_egress(const struct dpaa_priv *priv,
|
|
|
|
|
struct dpaa_fq *fq,
|
|
|
|
|
struct fman_port *port,
|
|
|
|
|
const struct qman_fq *template)
|
|
|
|
|
{
|
|
|
|
|
fq->fq_base = *template;
|
|
|
|
|
fq->net_dev = priv->net_dev;
|
|
|
|
|
|
|
|
|
|
if (port) {
|
|
|
|
|
fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL;
|
|
|
|
|
fq->channel = (u16)fman_port_get_qman_channel_id(port);
|
|
|
|
|
} else {
|
|
|
|
|
fq->flags = QMAN_FQ_FLAG_NO_MODIFY;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2024-07-14 01:53:32 +03:00
|
|
|
static int dpaa_fq_setup(struct dpaa_priv *priv,
|
|
|
|
|
const struct dpaa_fq_cbs *fq_cbs,
|
|
|
|
|
struct fman_port *tx_port)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
2017-08-27 16:13:39 +03:00
|
|
|
int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu;
|
2016-11-15 10:41:02 +02:00
|
|
|
const cpumask_t *affine_cpus = qman_affine_cpus();
|
|
|
|
|
struct dpaa_fq *fq;
|
2024-07-14 01:53:32 +03:00
|
|
|
u16 *channels;
|
|
|
|
|
|
|
|
|
|
channels = kcalloc(num_possible_cpus(), sizeof(u16), GFP_KERNEL);
|
|
|
|
|
if (!channels)
|
|
|
|
|
return -ENOMEM;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2019-05-27 15:24:05 +03:00
|
|
|
for_each_cpu_and(cpu, affine_cpus, cpu_online_mask)
|
2017-08-27 16:13:39 +03:00
|
|
|
channels[num_portals++] = qman_affine_channel(cpu);
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
if (num_portals == 0)
|
|
|
|
|
dev_err(priv->net_dev->dev.parent,
|
2019-10-23 12:08:46 +03:00
|
|
|
"No Qman software (affine) channels found\n");
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* Initialize each FQ in the list */
|
|
|
|
|
list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
|
|
|
|
|
switch (fq->fq_type) {
|
|
|
|
|
case FQ_TYPE_RX_DEFAULT:
|
|
|
|
|
dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
|
|
|
|
|
break;
|
|
|
|
|
case FQ_TYPE_RX_ERROR:
|
|
|
|
|
dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq);
|
|
|
|
|
break;
|
2017-08-27 16:13:39 +03:00
|
|
|
case FQ_TYPE_RX_PCD:
|
|
|
|
|
if (!num_portals)
|
|
|
|
|
continue;
|
|
|
|
|
dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
|
|
|
|
|
fq->channel = channels[portal_cnt++ % num_portals];
|
|
|
|
|
break;
|
2016-11-15 10:41:02 +02:00
|
|
|
case FQ_TYPE_TX:
|
|
|
|
|
dpaa_setup_egress(priv, fq, tx_port,
|
|
|
|
|
&fq_cbs->egress_ern);
|
2024-07-14 01:53:34 +03:00
|
|
|
priv->egress_fqs[egress_cnt++] = &fq->fq_base;
|
2016-11-15 10:41:02 +02:00
|
|
|
break;
|
|
|
|
|
case FQ_TYPE_TX_CONF_MQ:
|
|
|
|
|
priv->conf_fqs[conf_cnt++] = &fq->fq_base;
|
2020-08-23 17:36:59 -05:00
|
|
|
fallthrough;
|
2016-11-15 10:41:02 +02:00
|
|
|
case FQ_TYPE_TX_CONFIRM:
|
|
|
|
|
dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq);
|
|
|
|
|
break;
|
|
|
|
|
case FQ_TYPE_TX_ERROR:
|
|
|
|
|
dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
dev_warn(priv->net_dev->dev.parent,
|
|
|
|
|
"Unknown FQ type detected!\n");
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2024-07-14 01:53:32 +03:00
|
|
|
kfree(channels);
|
|
|
|
|
|
|
|
|
|
return 0;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv,
|
|
|
|
|
struct qman_fq *tx_fq)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
2024-07-14 01:53:33 +03:00
|
|
|
for (i = 0; i < dpaa_max_num_txqs(); i++)
|
2016-11-15 10:41:02 +02:00
|
|
|
if (priv->egress_fqs[i] == tx_fq)
|
|
|
|
|
return i;
|
|
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable)
|
|
|
|
|
{
|
|
|
|
|
const struct dpaa_priv *priv;
|
|
|
|
|
struct qman_fq *confq = NULL;
|
|
|
|
|
struct qm_mcc_initfq initfq;
|
|
|
|
|
struct device *dev;
|
|
|
|
|
struct qman_fq *fq;
|
|
|
|
|
int queue_id;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
priv = netdev_priv(dpaa_fq->net_dev);
|
|
|
|
|
dev = dpaa_fq->net_dev->dev.parent;
|
|
|
|
|
|
|
|
|
|
if (dpaa_fq->fqid == 0)
|
|
|
|
|
dpaa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
|
|
|
|
|
|
|
|
|
|
dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY);
|
|
|
|
|
|
|
|
|
|
err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(dev, "qman_create_fq() failed\n");
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
fq = &dpaa_fq->fq_base;
|
|
|
|
|
|
|
|
|
|
if (dpaa_fq->init) {
|
|
|
|
|
memset(&initfq, 0, sizeof(initfq));
|
|
|
|
|
|
2016-12-15 15:13:04 +02:00
|
|
|
initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL);
|
2016-11-15 10:41:02 +02:00
|
|
|
/* Note: we may get to keep an empty FQ in cache */
|
2016-12-15 15:13:04 +02:00
|
|
|
initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* Try to reduce the number of portal interrupts for
|
|
|
|
|
* Tx Confirmation FQs.
|
|
|
|
|
*/
|
|
|
|
|
if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM)
|
2017-03-30 16:24:15 +03:00
|
|
|
initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* FQ placement */
|
2016-12-15 15:13:04 +02:00
|
|
|
initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq);
|
|
|
|
|
|
|
|
|
|
/* Put all egress queues in a congestion group of their own.
|
|
|
|
|
* Sensu stricto, the Tx confirmation queues are Rx FQs,
|
|
|
|
|
* rather than Tx - but they nonetheless account for the
|
|
|
|
|
* memory footprint on behalf of egress traffic. We therefore
|
|
|
|
|
* place them in the netdev's CGR, along with the Tx FQs.
|
|
|
|
|
*/
|
|
|
|
|
if (dpaa_fq->fq_type == FQ_TYPE_TX ||
|
|
|
|
|
dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM ||
|
|
|
|
|
dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) {
|
2016-12-15 15:13:04 +02:00
|
|
|
initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
|
|
|
|
|
initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
|
2016-11-15 10:41:02 +02:00
|
|
|
initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid;
|
|
|
|
|
/* Set a fixed overhead accounting, in an attempt to
|
|
|
|
|
* reduce the impact of fixed-size skb shells and the
|
|
|
|
|
* driver's needed headroom on system memory. This is
|
|
|
|
|
* especially the case when the egress traffic is
|
|
|
|
|
* composed of small datagrams.
|
|
|
|
|
* Unfortunately, QMan's OAL value is capped to an
|
|
|
|
|
* insufficient value, but even that is better than
|
|
|
|
|
* no overhead accounting at all.
|
|
|
|
|
*/
|
2016-12-15 15:13:04 +02:00
|
|
|
initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
|
2016-11-15 10:41:02 +02:00
|
|
|
qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
|
|
|
|
|
qm_fqd_set_oal(&initfq.fqd,
|
|
|
|
|
min(sizeof(struct sk_buff) +
|
|
|
|
|
priv->tx_headroom,
|
|
|
|
|
(size_t)FSL_QMAN_MAX_OAL));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (td_enable) {
|
2016-12-15 15:13:04 +02:00
|
|
|
initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH);
|
2016-11-15 10:41:02 +02:00
|
|
|
qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1);
|
2016-12-15 15:13:04 +02:00
|
|
|
initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE);
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dpaa_fq->fq_type == FQ_TYPE_TX) {
|
|
|
|
|
queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base);
|
|
|
|
|
if (queue_id >= 0)
|
|
|
|
|
confq = priv->conf_fqs[queue_id];
|
|
|
|
|
if (confq) {
|
2016-12-15 15:13:04 +02:00
|
|
|
initfq.we_mask |=
|
|
|
|
|
cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
|
2016-11-15 10:41:02 +02:00
|
|
|
/* ContextA: OVOM=1(use contextA2 bits instead of ICAD)
|
|
|
|
|
* A2V=1 (contextA A2 field is valid)
|
|
|
|
|
* A0V=1 (contextA A0 field is valid)
|
|
|
|
|
* B0V=1 (contextB field is valid)
|
|
|
|
|
* ContextA A2: EBD=1 (deallocate buffers inside FMan)
|
|
|
|
|
* ContextB B0(ASPID): 0 (absolute Virtual Storage ID)
|
|
|
|
|
*/
|
2016-12-15 15:13:04 +02:00
|
|
|
qm_fqd_context_a_set64(&initfq.fqd,
|
|
|
|
|
0x1e00000080000000ULL);
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Put all the ingress queues in our "ingress CGR". */
|
|
|
|
|
if (priv->use_ingress_cgr &&
|
|
|
|
|
(dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
|
2017-08-27 16:13:39 +03:00
|
|
|
dpaa_fq->fq_type == FQ_TYPE_RX_ERROR ||
|
|
|
|
|
dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) {
|
2016-12-15 15:13:04 +02:00
|
|
|
initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
|
|
|
|
|
initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
|
2016-11-15 10:41:02 +02:00
|
|
|
initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid;
|
|
|
|
|
/* Set a fixed overhead accounting, just like for the
|
|
|
|
|
* egress CGR.
|
|
|
|
|
*/
|
2016-12-15 15:13:04 +02:00
|
|
|
initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
|
2016-11-15 10:41:02 +02:00
|
|
|
qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
|
|
|
|
|
qm_fqd_set_oal(&initfq.fqd,
|
|
|
|
|
min(sizeof(struct sk_buff) +
|
|
|
|
|
priv->tx_headroom,
|
|
|
|
|
(size_t)FSL_QMAN_MAX_OAL));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Initialization common to all ingress queues */
|
|
|
|
|
if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) {
|
2016-12-15 15:13:04 +02:00
|
|
|
initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
|
2017-02-14 17:17:28 +02:00
|
|
|
initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_HOLDACTIVE |
|
|
|
|
|
QM_FQCTRL_CTXASTASHING);
|
2016-11-15 10:41:02 +02:00
|
|
|
initfq.fqd.context_a.stashing.exclusive =
|
|
|
|
|
QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX |
|
|
|
|
|
QM_STASHING_EXCL_ANNOTATION;
|
|
|
|
|
qm_fqd_set_stashing(&initfq.fqd, 1, 2,
|
|
|
|
|
DIV_ROUND_UP(sizeof(struct qman_fq),
|
|
|
|
|
64));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq);
|
|
|
|
|
if (err < 0) {
|
|
|
|
|
dev_err(dev, "qman_init_fq(%u) = %d\n",
|
|
|
|
|
qman_fq_fqid(fq), err);
|
|
|
|
|
qman_destroy_fq(fq);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dpaa_fq->fqid = qman_fq_fqid(fq);
|
|
|
|
|
|
2020-11-25 18:53:33 +02:00
|
|
|
if (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
|
|
|
|
|
dpaa_fq->fq_type == FQ_TYPE_RX_PCD) {
|
|
|
|
|
err = xdp_rxq_info_reg(&dpaa_fq->xdp_rxq, dpaa_fq->net_dev,
|
2020-12-03 15:43:43 +01:00
|
|
|
dpaa_fq->fqid, 0);
|
2020-11-25 18:53:33 +02:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(dev, "xdp_rxq_info_reg() = %d\n", err);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
err = xdp_rxq_info_reg_mem_model(&dpaa_fq->xdp_rxq,
|
|
|
|
|
MEM_TYPE_PAGE_ORDER0, NULL);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(dev, "xdp_rxq_info_reg_mem_model() = %d\n",
|
|
|
|
|
err);
|
|
|
|
|
xdp_rxq_info_unreg(&dpaa_fq->xdp_rxq);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_fq_free_entry(struct device *dev, struct qman_fq *fq)
|
|
|
|
|
{
|
|
|
|
|
const struct dpaa_priv *priv;
|
|
|
|
|
struct dpaa_fq *dpaa_fq;
|
|
|
|
|
int err, error;
|
|
|
|
|
|
|
|
|
|
err = 0;
|
|
|
|
|
|
|
|
|
|
dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
|
|
|
|
|
priv = netdev_priv(dpaa_fq->net_dev);
|
|
|
|
|
|
|
|
|
|
if (dpaa_fq->init) {
|
|
|
|
|
err = qman_retire_fq(fq, NULL);
|
|
|
|
|
if (err < 0 && netif_msg_drv(priv))
|
|
|
|
|
dev_err(dev, "qman_retire_fq(%u) = %d\n",
|
|
|
|
|
qman_fq_fqid(fq), err);
|
|
|
|
|
|
|
|
|
|
error = qman_oos_fq(fq);
|
|
|
|
|
if (error < 0 && netif_msg_drv(priv)) {
|
|
|
|
|
dev_err(dev, "qman_oos_fq(%u) = %d\n",
|
|
|
|
|
qman_fq_fqid(fq), error);
|
|
|
|
|
if (err >= 0)
|
|
|
|
|
err = error;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-11-25 18:53:33 +02:00
|
|
|
if ((dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
|
|
|
|
|
dpaa_fq->fq_type == FQ_TYPE_RX_PCD) &&
|
|
|
|
|
xdp_rxq_info_is_reg(&dpaa_fq->xdp_rxq))
|
|
|
|
|
xdp_rxq_info_unreg(&dpaa_fq->xdp_rxq);
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
qman_destroy_fq(fq);
|
|
|
|
|
list_del(&dpaa_fq->list);
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_fq_free(struct device *dev, struct list_head *list)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_fq *dpaa_fq, *tmp;
|
|
|
|
|
int err, error;
|
|
|
|
|
|
|
|
|
|
err = 0;
|
|
|
|
|
list_for_each_entry_safe(dpaa_fq, tmp, list, list) {
|
|
|
|
|
error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq);
|
|
|
|
|
if (error < 0 && err >= 0)
|
|
|
|
|
err = error;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-13 17:20:01 +02:00
|
|
|
static int dpaa_eth_init_tx_port(struct fman_port *port, struct dpaa_fq *errq,
|
|
|
|
|
struct dpaa_fq *defq,
|
|
|
|
|
struct dpaa_buffer_layout *buf_layout)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
struct fman_buffer_prefix_content buf_prefix_content;
|
|
|
|
|
struct fman_port_params params;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
memset(¶ms, 0, sizeof(params));
|
|
|
|
|
memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
|
|
|
|
|
|
|
|
|
|
buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
|
|
|
|
|
buf_prefix_content.pass_prs_result = true;
|
|
|
|
|
buf_prefix_content.pass_hash_result = true;
|
2018-06-25 20:37:15 +08:00
|
|
|
buf_prefix_content.pass_time_stamp = true;
|
2016-11-15 10:41:02 +02:00
|
|
|
buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
|
|
|
|
|
|
|
|
|
|
params.specific_params.non_rx_params.err_fqid = errq->fqid;
|
|
|
|
|
params.specific_params.non_rx_params.dflt_fqid = defq->fqid;
|
|
|
|
|
|
|
|
|
|
err = fman_port_config(port, ¶ms);
|
2017-02-13 17:20:01 +02:00
|
|
|
if (err) {
|
2016-11-15 10:41:02 +02:00
|
|
|
pr_err("%s: fman_port_config failed\n", __func__);
|
2017-02-13 17:20:01 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
|
2017-02-13 17:20:01 +02:00
|
|
|
if (err) {
|
2016-11-15 10:41:02 +02:00
|
|
|
pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
|
|
|
|
|
__func__);
|
2017-02-13 17:20:01 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
err = fman_port_init(port);
|
|
|
|
|
if (err)
|
|
|
|
|
pr_err("%s: fm_port_init failed\n", __func__);
|
2017-02-13 17:20:01 +02:00
|
|
|
|
|
|
|
|
return err;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
2019-10-31 16:37:47 +02:00
|
|
|
static int dpaa_eth_init_rx_port(struct fman_port *port, struct dpaa_bp *bp,
|
|
|
|
|
struct dpaa_fq *errq,
|
2017-08-27 16:13:39 +03:00
|
|
|
struct dpaa_fq *defq, struct dpaa_fq *pcdq,
|
2017-02-13 17:20:01 +02:00
|
|
|
struct dpaa_buffer_layout *buf_layout)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
struct fman_buffer_prefix_content buf_prefix_content;
|
|
|
|
|
struct fman_port_rx_params *rx_p;
|
|
|
|
|
struct fman_port_params params;
|
2019-10-31 16:37:47 +02:00
|
|
|
int err;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
memset(¶ms, 0, sizeof(params));
|
|
|
|
|
memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
|
|
|
|
|
|
|
|
|
|
buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
|
|
|
|
|
buf_prefix_content.pass_prs_result = true;
|
|
|
|
|
buf_prefix_content.pass_hash_result = true;
|
2018-06-25 20:37:15 +08:00
|
|
|
buf_prefix_content.pass_time_stamp = true;
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
buf_prefix_content.data_align = DPAA_FD_RX_DATA_ALIGNMENT;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
rx_p = ¶ms.specific_params.rx_params;
|
|
|
|
|
rx_p->err_fqid = errq->fqid;
|
|
|
|
|
rx_p->dflt_fqid = defq->fqid;
|
2017-08-27 16:13:39 +03:00
|
|
|
if (pcdq) {
|
|
|
|
|
rx_p->pcd_base_fqid = pcdq->fqid;
|
|
|
|
|
rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM;
|
|
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2019-10-31 16:37:47 +02:00
|
|
|
rx_p->ext_buf_pools.num_of_pools_used = 1;
|
|
|
|
|
rx_p->ext_buf_pools.ext_buf_pool[0].id = bp->bpid;
|
|
|
|
|
rx_p->ext_buf_pools.ext_buf_pool[0].size = (u16)bp->size;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
err = fman_port_config(port, ¶ms);
|
2017-02-13 17:20:01 +02:00
|
|
|
if (err) {
|
2016-11-15 10:41:02 +02:00
|
|
|
pr_err("%s: fman_port_config failed\n", __func__);
|
2017-02-13 17:20:01 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
|
2017-02-13 17:20:01 +02:00
|
|
|
if (err) {
|
2016-11-15 10:41:02 +02:00
|
|
|
pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
|
|
|
|
|
__func__);
|
2017-02-13 17:20:01 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
err = fman_port_init(port);
|
|
|
|
|
if (err)
|
|
|
|
|
pr_err("%s: fm_port_init failed\n", __func__);
|
2017-02-13 17:20:01 +02:00
|
|
|
|
|
|
|
|
return err;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
2017-02-13 17:20:01 +02:00
|
|
|
static int dpaa_eth_init_ports(struct mac_device *mac_dev,
|
2019-10-31 16:37:47 +02:00
|
|
|
struct dpaa_bp *bp,
|
2017-02-13 17:20:01 +02:00
|
|
|
struct fm_port_fqs *port_fqs,
|
|
|
|
|
struct dpaa_buffer_layout *buf_layout,
|
|
|
|
|
struct device *dev)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
struct fman_port *rxport = mac_dev->port[RX];
|
|
|
|
|
struct fman_port *txport = mac_dev->port[TX];
|
2017-02-13 17:20:01 +02:00
|
|
|
int err;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2017-02-13 17:20:01 +02:00
|
|
|
err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq,
|
|
|
|
|
port_fqs->tx_defq, &buf_layout[TX]);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
2019-10-31 16:37:47 +02:00
|
|
|
err = dpaa_eth_init_rx_port(rxport, bp, port_fqs->rx_errq,
|
2017-08-27 16:13:39 +03:00
|
|
|
port_fqs->rx_defq, port_fqs->rx_pcdq,
|
|
|
|
|
&buf_layout[RX]);
|
2017-02-13 17:20:01 +02:00
|
|
|
|
|
|
|
|
return err;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp,
|
|
|
|
|
struct bm_buffer *bmb, int cnt)
|
|
|
|
|
{
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = bman_release(dpaa_bp->pool, bmb, cnt);
|
|
|
|
|
/* Should never occur, address anyway to avoid leaking the buffers */
|
2018-09-07 20:23:18 +03:00
|
|
|
if (WARN_ON(err) && dpaa_bp->free_buf_cb)
|
2016-11-15 10:41:02 +02:00
|
|
|
while (cnt-- > 0)
|
|
|
|
|
dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]);
|
|
|
|
|
|
|
|
|
|
return cnt;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dpaa_release_sgt_members(struct qm_sg_entry *sgt)
|
|
|
|
|
{
|
|
|
|
|
struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX];
|
|
|
|
|
struct dpaa_bp *dpaa_bp;
|
|
|
|
|
int i = 0, j;
|
|
|
|
|
|
|
|
|
|
memset(bmb, 0, sizeof(bmb));
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
|
|
|
|
|
if (!dpaa_bp)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
j = 0;
|
|
|
|
|
do {
|
|
|
|
|
WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
|
|
|
|
|
|
|
|
|
|
bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i]));
|
|
|
|
|
|
|
|
|
|
j++; i++;
|
|
|
|
|
} while (j < ARRAY_SIZE(bmb) &&
|
|
|
|
|
!qm_sg_entry_is_final(&sgt[i - 1]) &&
|
|
|
|
|
sgt[i - 1].bpid == sgt[i].bpid);
|
|
|
|
|
|
|
|
|
|
dpaa_bman_release(dpaa_bp, bmb, j);
|
|
|
|
|
} while (!qm_sg_entry_is_final(&sgt[i - 1]));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dpaa_fd_release(const struct net_device *net_dev,
|
|
|
|
|
const struct qm_fd *fd)
|
|
|
|
|
{
|
|
|
|
|
struct qm_sg_entry *sgt;
|
|
|
|
|
struct dpaa_bp *dpaa_bp;
|
|
|
|
|
struct bm_buffer bmb;
|
|
|
|
|
dma_addr_t addr;
|
|
|
|
|
void *vaddr;
|
|
|
|
|
|
|
|
|
|
bmb.data = 0;
|
|
|
|
|
bm_buffer_set64(&bmb, qm_fd_addr(fd));
|
|
|
|
|
|
|
|
|
|
dpaa_bp = dpaa_bpid2pool(fd->bpid);
|
|
|
|
|
if (!dpaa_bp)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
if (qm_fd_get_format(fd) == qm_fd_sg) {
|
|
|
|
|
vaddr = phys_to_virt(qm_fd_addr(fd));
|
|
|
|
|
sgt = vaddr + qm_fd_get_offset(fd);
|
|
|
|
|
|
2019-10-31 16:37:48 +02:00
|
|
|
dma_unmap_page(dpaa_bp->priv->rx_dma_dev, qm_fd_addr(fd),
|
|
|
|
|
DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
dpaa_release_sgt_members(sgt);
|
|
|
|
|
|
2019-10-31 16:37:48 +02:00
|
|
|
addr = dma_map_page(dpaa_bp->priv->rx_dma_dev,
|
|
|
|
|
virt_to_page(vaddr), 0, DPAA_BP_RAW_SIZE,
|
|
|
|
|
DMA_FROM_DEVICE);
|
2019-10-23 12:08:44 +03:00
|
|
|
if (dma_mapping_error(dpaa_bp->priv->rx_dma_dev, addr)) {
|
|
|
|
|
netdev_err(net_dev, "DMA mapping failed\n");
|
2016-11-15 10:41:02 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
bm_buffer_set64(&bmb, addr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dpaa_bman_release(dpaa_bp, &bmb, 1);
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:04 +02:00
|
|
|
static void count_ern(struct dpaa_percpu_priv *percpu_priv,
|
|
|
|
|
const union qm_mr_entry *msg)
|
|
|
|
|
{
|
|
|
|
|
switch (msg->ern.rc & QM_MR_RC_MASK) {
|
|
|
|
|
case QM_MR_RC_CGR_TAILDROP:
|
|
|
|
|
percpu_priv->ern_cnt.cg_tdrop++;
|
|
|
|
|
break;
|
|
|
|
|
case QM_MR_RC_WRED:
|
|
|
|
|
percpu_priv->ern_cnt.wred++;
|
|
|
|
|
break;
|
|
|
|
|
case QM_MR_RC_ERROR:
|
|
|
|
|
percpu_priv->ern_cnt.err_cond++;
|
|
|
|
|
break;
|
|
|
|
|
case QM_MR_RC_ORPWINDOW_EARLY:
|
|
|
|
|
percpu_priv->ern_cnt.early_window++;
|
|
|
|
|
break;
|
|
|
|
|
case QM_MR_RC_ORPWINDOW_LATE:
|
|
|
|
|
percpu_priv->ern_cnt.late_window++;
|
|
|
|
|
break;
|
|
|
|
|
case QM_MR_RC_FQ_TAILDROP:
|
|
|
|
|
percpu_priv->ern_cnt.fq_tdrop++;
|
|
|
|
|
break;
|
|
|
|
|
case QM_MR_RC_ORPWINDOW_RETIRED:
|
|
|
|
|
percpu_priv->ern_cnt.fq_retired++;
|
|
|
|
|
break;
|
|
|
|
|
case QM_MR_RC_ORP_ZERO:
|
|
|
|
|
percpu_priv->ern_cnt.orp_zero++;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
/* Turn on HW checksum computation for this outgoing frame.
|
|
|
|
|
* If the current protocol is not something we support in this regard
|
|
|
|
|
* (or if the stack has already computed the SW checksum), we do nothing.
|
|
|
|
|
*
|
|
|
|
|
* Returns 0 if all goes well (or HW csum doesn't apply), and a negative value
|
|
|
|
|
* otherwise.
|
|
|
|
|
*
|
|
|
|
|
* Note that this function may modify the fd->cmd field and the skb data buffer
|
|
|
|
|
* (the Parse Results area).
|
|
|
|
|
*/
|
|
|
|
|
static int dpaa_enable_tx_csum(struct dpaa_priv *priv,
|
|
|
|
|
struct sk_buff *skb,
|
|
|
|
|
struct qm_fd *fd,
|
2019-10-31 16:37:53 +02:00
|
|
|
void *parse_results)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
struct fman_prs_result *parse_result;
|
|
|
|
|
u16 ethertype = ntohs(skb->protocol);
|
|
|
|
|
struct ipv6hdr *ipv6h = NULL;
|
|
|
|
|
struct iphdr *iph;
|
|
|
|
|
int retval = 0;
|
|
|
|
|
u8 l4_proto;
|
|
|
|
|
|
|
|
|
|
if (skb->ip_summed != CHECKSUM_PARTIAL)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
/* Note: L3 csum seems to be already computed in sw, but we can't choose
|
|
|
|
|
* L4 alone from the FM configuration anyway.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* Fill in some fields of the Parse Results array, so the FMan
|
|
|
|
|
* can find them as if they came from the FMan Parser.
|
|
|
|
|
*/
|
|
|
|
|
parse_result = (struct fman_prs_result *)parse_results;
|
|
|
|
|
|
|
|
|
|
/* If we're dealing with VLAN, get the real Ethernet type */
|
2023-04-21 01:55:55 +03:00
|
|
|
if (ethertype == ETH_P_8021Q)
|
|
|
|
|
ethertype = ntohs(skb_vlan_eth_hdr(skb)->h_vlan_encapsulated_proto);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* Fill in the relevant L3 parse result fields
|
|
|
|
|
* and read the L4 protocol type
|
|
|
|
|
*/
|
|
|
|
|
switch (ethertype) {
|
|
|
|
|
case ETH_P_IP:
|
|
|
|
|
parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4);
|
|
|
|
|
iph = ip_hdr(skb);
|
|
|
|
|
WARN_ON(!iph);
|
|
|
|
|
l4_proto = iph->protocol;
|
|
|
|
|
break;
|
|
|
|
|
case ETH_P_IPV6:
|
|
|
|
|
parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6);
|
|
|
|
|
ipv6h = ipv6_hdr(skb);
|
|
|
|
|
WARN_ON(!ipv6h);
|
|
|
|
|
l4_proto = ipv6h->nexthdr;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
/* We shouldn't even be here */
|
|
|
|
|
if (net_ratelimit())
|
|
|
|
|
netif_alert(priv, tx_err, priv->net_dev,
|
|
|
|
|
"Can't compute HW csum for L3 proto 0x%x\n",
|
|
|
|
|
ntohs(skb->protocol));
|
|
|
|
|
retval = -EIO;
|
|
|
|
|
goto return_error;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Fill in the relevant L4 parse result fields */
|
|
|
|
|
switch (l4_proto) {
|
|
|
|
|
case IPPROTO_UDP:
|
|
|
|
|
parse_result->l4r = FM_L4_PARSE_RESULT_UDP;
|
|
|
|
|
break;
|
|
|
|
|
case IPPROTO_TCP:
|
|
|
|
|
parse_result->l4r = FM_L4_PARSE_RESULT_TCP;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
if (net_ratelimit())
|
|
|
|
|
netif_alert(priv, tx_err, priv->net_dev,
|
|
|
|
|
"Can't compute HW csum for L4 proto 0x%x\n",
|
|
|
|
|
l4_proto);
|
|
|
|
|
retval = -EIO;
|
|
|
|
|
goto return_error;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* At index 0 is IPOffset_1 as defined in the Parse Results */
|
|
|
|
|
parse_result->ip_off[0] = (u8)skb_network_offset(skb);
|
|
|
|
|
parse_result->l4_off = (u8)skb_transport_offset(skb);
|
|
|
|
|
|
|
|
|
|
/* Enable L3 (and L4, if TCP or UDP) HW checksum. */
|
2016-12-15 15:13:04 +02:00
|
|
|
fd->cmd |= cpu_to_be32(FM_FD_CMD_RPD | FM_FD_CMD_DTC);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* On P1023 and similar platforms fd->cmd interpretation could
|
|
|
|
|
* be disabled by setting CONTEXT_A bit ICMD; currently this bit
|
|
|
|
|
* is not set so we do not need to check; in the future, if/when
|
|
|
|
|
* using context_a we need to check this bit
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
return_error:
|
|
|
|
|
return retval;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp)
|
|
|
|
|
{
|
2019-10-23 12:08:44 +03:00
|
|
|
struct net_device *net_dev = dpaa_bp->priv->net_dev;
|
2016-11-15 10:41:02 +02:00
|
|
|
struct bm_buffer bmb[8];
|
|
|
|
|
dma_addr_t addr;
|
2019-10-31 16:37:48 +02:00
|
|
|
struct page *p;
|
2016-11-15 10:41:02 +02:00
|
|
|
u8 i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
2019-10-31 16:37:48 +02:00
|
|
|
p = dev_alloc_pages(0);
|
|
|
|
|
if (unlikely(!p)) {
|
|
|
|
|
netdev_err(net_dev, "dev_alloc_pages() failed\n");
|
2016-11-15 10:41:02 +02:00
|
|
|
goto release_previous_buffs;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 16:37:48 +02:00
|
|
|
addr = dma_map_page(dpaa_bp->priv->rx_dma_dev, p, 0,
|
|
|
|
|
DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
|
2019-10-23 12:08:44 +03:00
|
|
|
if (unlikely(dma_mapping_error(dpaa_bp->priv->rx_dma_dev,
|
|
|
|
|
addr))) {
|
|
|
|
|
netdev_err(net_dev, "DMA map failed\n");
|
2016-11-15 10:41:02 +02:00
|
|
|
goto release_previous_buffs;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bmb[i].data = 0;
|
|
|
|
|
bm_buffer_set64(&bmb[i], addr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
release_bufs:
|
|
|
|
|
return dpaa_bman_release(dpaa_bp, bmb, i);
|
|
|
|
|
|
|
|
|
|
release_previous_buffs:
|
|
|
|
|
WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n");
|
|
|
|
|
|
|
|
|
|
bm_buffer_set64(&bmb[i], 0);
|
|
|
|
|
/* Avoid releasing a completely null buffer; bman_release() requires
|
|
|
|
|
* at least one buffer.
|
|
|
|
|
*/
|
|
|
|
|
if (likely(i))
|
|
|
|
|
goto release_bufs;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
/* Give each CPU an allotment of "config_count" buffers */
|
|
|
|
|
for_each_possible_cpu(i) {
|
|
|
|
|
int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i);
|
|
|
|
|
int j;
|
|
|
|
|
|
|
|
|
|
/* Although we access another CPU's counters here
|
|
|
|
|
* we do it at boot time so it is safe
|
|
|
|
|
*/
|
|
|
|
|
for (j = 0; j < dpaa_bp->config_count; j += 8)
|
|
|
|
|
*count_ptr += dpaa_bp_add_8_bufs(dpaa_bp);
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Add buffers/(pages) for Rx processing whenever bpool count falls below
|
|
|
|
|
* REFILL_THRESHOLD.
|
|
|
|
|
*/
|
|
|
|
|
static int dpaa_eth_refill_bpool(struct dpaa_bp *dpaa_bp, int *countptr)
|
|
|
|
|
{
|
|
|
|
|
int count = *countptr;
|
|
|
|
|
int new_bufs;
|
|
|
|
|
|
|
|
|
|
if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) {
|
|
|
|
|
do {
|
|
|
|
|
new_bufs = dpaa_bp_add_8_bufs(dpaa_bp);
|
|
|
|
|
if (unlikely(!new_bufs)) {
|
|
|
|
|
/* Avoid looping forever if we've temporarily
|
|
|
|
|
* run out of memory. We'll try again at the
|
|
|
|
|
* next NAPI cycle.
|
|
|
|
|
*/
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
count += new_bufs;
|
|
|
|
|
} while (count < FSL_DPAA_ETH_MAX_BUF_COUNT);
|
|
|
|
|
|
|
|
|
|
*countptr = count;
|
|
|
|
|
if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT))
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_eth_refill_bpools(struct dpaa_priv *priv)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_bp *dpaa_bp;
|
|
|
|
|
int *countptr;
|
2019-10-31 16:37:47 +02:00
|
|
|
|
|
|
|
|
dpaa_bp = priv->dpaa_bp;
|
|
|
|
|
if (!dpaa_bp)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
countptr = this_cpu_ptr(dpaa_bp->percpu_count);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2020-12-09 17:21:07 +08:00
|
|
|
return dpaa_eth_refill_bpool(dpaa_bp, countptr);
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Cleanup function for outgoing frame descriptors that were built on Tx path,
|
|
|
|
|
* either contiguous frames or scatter/gather ones.
|
|
|
|
|
* Skb freeing is not handled here.
|
|
|
|
|
*
|
|
|
|
|
* This function may be called on error paths in the Tx function, so guard
|
2019-10-31 16:37:50 +02:00
|
|
|
* against cases when not all fd relevant fields were filled in. To avoid
|
|
|
|
|
* reading the invalid transmission timestamp for the error paths set ts to
|
|
|
|
|
* false.
|
2016-11-15 10:41:02 +02:00
|
|
|
*
|
|
|
|
|
* Return the skb backpointer, since for S/G frames the buffer containing it
|
|
|
|
|
* gets freed here.
|
2020-11-25 18:53:33 +02:00
|
|
|
*
|
|
|
|
|
* No skb backpointer is set when transmitting XDP frames. Cleanup the buffer
|
|
|
|
|
* and return NULL in this case.
|
2016-11-15 10:41:02 +02:00
|
|
|
*/
|
|
|
|
|
static struct sk_buff *dpaa_cleanup_tx_fd(const struct dpaa_priv *priv,
|
2019-10-31 16:37:50 +02:00
|
|
|
const struct qm_fd *fd, bool ts)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
|
|
|
|
|
struct device *dev = priv->net_dev->dev.parent;
|
2018-06-25 20:37:15 +08:00
|
|
|
struct skb_shared_hwtstamps shhwtstamps;
|
2016-11-15 10:41:02 +02:00
|
|
|
dma_addr_t addr = qm_fd_addr(fd);
|
2019-10-31 16:37:51 +02:00
|
|
|
void *vaddr = phys_to_virt(addr);
|
2016-11-15 10:41:02 +02:00
|
|
|
const struct qm_sg_entry *sgt;
|
2020-11-25 18:53:30 +02:00
|
|
|
struct dpaa_eth_swbp *swbp;
|
2019-10-31 16:37:51 +02:00
|
|
|
struct sk_buff *skb;
|
2018-06-25 20:37:15 +08:00
|
|
|
u64 ns;
|
2019-10-31 16:37:52 +02:00
|
|
|
int i;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) {
|
2019-10-31 16:37:54 +02:00
|
|
|
dma_unmap_page(priv->tx_dma_dev, addr,
|
|
|
|
|
qm_fd_get_offset(fd) + DPAA_SGT_SIZE,
|
|
|
|
|
dma_dir);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* The sgt buffer has been allocated with netdev_alloc_frag(),
|
|
|
|
|
* it's from lowmem.
|
|
|
|
|
*/
|
2019-10-31 16:37:51 +02:00
|
|
|
sgt = vaddr + qm_fd_get_offset(fd);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* sgt[0] is from lowmem, was dma_map_single()-ed */
|
2019-10-23 12:08:44 +03:00
|
|
|
dma_unmap_single(priv->tx_dma_dev, qm_sg_addr(&sgt[0]),
|
2016-11-15 10:41:02 +02:00
|
|
|
qm_sg_entry_get_len(&sgt[0]), dma_dir);
|
|
|
|
|
|
|
|
|
|
/* remaining pages were mapped with skb_frag_dma_map() */
|
2019-10-31 16:37:52 +02:00
|
|
|
for (i = 1; (i < DPAA_SGT_MAX_ENTRIES) &&
|
|
|
|
|
!qm_sg_entry_is_final(&sgt[i - 1]); i++) {
|
2016-11-15 10:41:02 +02:00
|
|
|
WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
|
|
|
|
|
|
2019-10-23 12:08:44 +03:00
|
|
|
dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[i]),
|
2016-11-15 10:41:02 +02:00
|
|
|
qm_sg_entry_get_len(&sgt[i]), dma_dir);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
2019-10-23 12:08:44 +03:00
|
|
|
dma_unmap_single(priv->tx_dma_dev, addr,
|
2020-11-25 18:53:33 +02:00
|
|
|
qm_fd_get_offset(fd) + qm_fd_get_length(fd),
|
2019-10-31 16:37:52 +02:00
|
|
|
dma_dir);
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
2020-11-25 18:53:30 +02:00
|
|
|
swbp = (struct dpaa_eth_swbp *)vaddr;
|
|
|
|
|
skb = swbp->skb;
|
2019-10-31 16:37:52 +02:00
|
|
|
|
2020-11-25 18:53:33 +02:00
|
|
|
/* No skb backpointer is set when running XDP. An xdp_frame
|
|
|
|
|
* backpointer is saved instead.
|
|
|
|
|
*/
|
|
|
|
|
if (!skb) {
|
|
|
|
|
xdp_return_frame(swbp->xdpf);
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 16:37:49 +02:00
|
|
|
/* DMA unmapping is required before accessing the HW provided info */
|
2019-10-31 16:37:50 +02:00
|
|
|
if (ts && priv->tx_tstamp &&
|
|
|
|
|
skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
|
2019-10-31 16:37:49 +02:00
|
|
|
memset(&shhwtstamps, 0, sizeof(shhwtstamps));
|
|
|
|
|
|
2019-10-31 16:37:51 +02:00
|
|
|
if (!fman_port_get_tstamp(priv->mac_dev->port[TX], vaddr,
|
2019-10-31 16:37:49 +02:00
|
|
|
&ns)) {
|
|
|
|
|
shhwtstamps.hwtstamp = ns_to_ktime(ns);
|
|
|
|
|
skb_tstamp_tx(skb, &shhwtstamps);
|
|
|
|
|
} else {
|
|
|
|
|
dev_warn(dev, "fman_port_get_tstamp failed!\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (qm_fd_get_format(fd) == qm_fd_sg)
|
2019-10-31 16:37:54 +02:00
|
|
|
/* Free the page that we allocated on Tx for the SGT */
|
|
|
|
|
free_pages((unsigned long)vaddr, 0);
|
2019-10-31 16:37:49 +02:00
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
return skb;
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-26 14:34:02 +02:00
|
|
|
static u8 rx_csum_offload(const struct dpaa_priv *priv, const struct qm_fd *fd)
|
|
|
|
|
{
|
|
|
|
|
/* The parser has run and performed L4 checksum validation.
|
|
|
|
|
* We know there were no parser errors (and implicitly no
|
|
|
|
|
* L4 csum error), otherwise we wouldn't be here.
|
|
|
|
|
*/
|
|
|
|
|
if ((priv->net_dev->features & NETIF_F_RXCSUM) &&
|
|
|
|
|
(be32_to_cpu(fd->status) & FM_FD_STAT_L4CV))
|
|
|
|
|
return CHECKSUM_UNNECESSARY;
|
|
|
|
|
|
|
|
|
|
/* We're here because either the parser didn't run or the L4 checksum
|
|
|
|
|
* was not verified. This may include the case of a UDP frame with
|
|
|
|
|
* checksum zero or an L4 proto other than TCP/UDP
|
|
|
|
|
*/
|
|
|
|
|
return CHECKSUM_NONE;
|
|
|
|
|
}
|
|
|
|
|
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
#define PTR_IS_ALIGNED(x, a) (IS_ALIGNED((unsigned long)(x), (a)))
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
/* Build a linear skb around the received buffer.
|
|
|
|
|
* We are guaranteed there is enough room at the end of the data buffer to
|
|
|
|
|
* accommodate the shared info area of the skb.
|
|
|
|
|
*/
|
|
|
|
|
static struct sk_buff *contig_fd_to_skb(const struct dpaa_priv *priv,
|
|
|
|
|
const struct qm_fd *fd)
|
|
|
|
|
{
|
|
|
|
|
ssize_t fd_off = qm_fd_get_offset(fd);
|
|
|
|
|
dma_addr_t addr = qm_fd_addr(fd);
|
|
|
|
|
struct dpaa_bp *dpaa_bp;
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
void *vaddr;
|
|
|
|
|
|
|
|
|
|
vaddr = phys_to_virt(addr);
|
|
|
|
|
WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
|
|
|
|
|
|
|
|
|
|
dpaa_bp = dpaa_bpid2pool(fd->bpid);
|
|
|
|
|
if (!dpaa_bp)
|
|
|
|
|
goto free_buffer;
|
|
|
|
|
|
|
|
|
|
skb = build_skb(vaddr, dpaa_bp->size +
|
|
|
|
|
SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
|
2018-09-07 20:23:18 +03:00
|
|
|
if (WARN_ONCE(!skb, "Build skb failure on Rx\n"))
|
2016-11-15 10:41:02 +02:00
|
|
|
goto free_buffer;
|
|
|
|
|
skb_reserve(skb, fd_off);
|
|
|
|
|
skb_put(skb, qm_fd_get_length(fd));
|
|
|
|
|
|
2017-01-26 14:34:02 +02:00
|
|
|
skb->ip_summed = rx_csum_offload(priv, fd);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
return skb;
|
|
|
|
|
|
|
|
|
|
free_buffer:
|
2019-10-31 16:37:48 +02:00
|
|
|
free_pages((unsigned long)vaddr, 0);
|
2016-11-15 10:41:02 +02:00
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Build an skb with the data of the first S/G entry in the linear portion and
|
|
|
|
|
* the rest of the frame as skb fragments.
|
|
|
|
|
*
|
|
|
|
|
* The page fragment holding the S/G Table is recycled here.
|
|
|
|
|
*/
|
|
|
|
|
static struct sk_buff *sg_fd_to_skb(const struct dpaa_priv *priv,
|
|
|
|
|
const struct qm_fd *fd)
|
|
|
|
|
{
|
|
|
|
|
ssize_t fd_off = qm_fd_get_offset(fd);
|
|
|
|
|
dma_addr_t addr = qm_fd_addr(fd);
|
|
|
|
|
const struct qm_sg_entry *sgt;
|
|
|
|
|
struct page *page, *head_page;
|
|
|
|
|
struct dpaa_bp *dpaa_bp;
|
|
|
|
|
void *vaddr, *sg_vaddr;
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
dma_addr_t sg_addr;
|
|
|
|
|
int page_offset;
|
|
|
|
|
unsigned int sz;
|
|
|
|
|
int *count_ptr;
|
2019-12-23 09:39:22 +02:00
|
|
|
int i, j;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
vaddr = phys_to_virt(addr);
|
|
|
|
|
WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
|
|
|
|
|
|
|
|
|
|
/* Iterate through the SGT entries and add data buffers to the skb */
|
|
|
|
|
sgt = vaddr + fd_off;
|
2017-11-03 13:52:24 +01:00
|
|
|
skb = NULL;
|
2016-11-15 10:41:02 +02:00
|
|
|
for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) {
|
|
|
|
|
/* Extension bit is not supported */
|
|
|
|
|
WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
|
|
|
|
|
|
|
|
|
|
sg_addr = qm_sg_addr(&sgt[i]);
|
|
|
|
|
sg_vaddr = phys_to_virt(sg_addr);
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
WARN_ON(!PTR_IS_ALIGNED(sg_vaddr, SMP_CACHE_BYTES));
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2019-12-23 09:39:22 +02:00
|
|
|
dma_unmap_page(priv->rx_dma_dev, sg_addr,
|
|
|
|
|
DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
/* We may use multiple Rx pools */
|
|
|
|
|
dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
|
|
|
|
|
if (!dpaa_bp)
|
|
|
|
|
goto free_buffers;
|
|
|
|
|
|
2017-11-03 13:52:24 +01:00
|
|
|
if (!skb) {
|
2016-11-15 10:41:02 +02:00
|
|
|
sz = dpaa_bp->size +
|
|
|
|
|
SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
|
|
|
|
|
skb = build_skb(sg_vaddr, sz);
|
2018-09-07 20:23:18 +03:00
|
|
|
if (WARN_ON(!skb))
|
2016-11-15 10:41:02 +02:00
|
|
|
goto free_buffers;
|
|
|
|
|
|
2017-01-26 14:34:02 +02:00
|
|
|
skb->ip_summed = rx_csum_offload(priv, fd);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* Make sure forwarded skbs will have enough space
|
|
|
|
|
* on Tx, if extra headers are added.
|
|
|
|
|
*/
|
|
|
|
|
WARN_ON(fd_off != priv->rx_headroom);
|
net: dpaa_eth: add assertions about SGT entry offsets in sg_fd_to_skb()
Multi-buffer frame descriptors (FDs) point to a buffer holding a
scatter/gather table (SGT), which is a finite array of fixed-size
entries, the last of which has qm_sg_entry_is_final(&sgt[i]) == true.
Each SGT entry points to a buffer holding pieces of the frame.
DPAARM.pdf explains in the figure called "Internal and External Margins,
Scatter/Gather Frame Format" that the SGT table is located within its
buffer at the same offset as the frame data start is located within the
first packet buffer.
+------------------------+
Scatter/Gather Buffer | First Buffer | Last Buffer
^ +------------+ ^ +-|---->^ +------------+ +->+------------+
| | | | ICEOF | | | | | |////////////|
| +------------+ v | | | | | |////////////|
BSM | |/ part of //| | |BSM | | | |////////////|
| |/ Internal /| | | | | | |////////////|
| |/ Context //| | | | | | |// Frame ///|
| +------------+ | | | | | ... |/ content //|
| | | | | | | | |////////////|
| | | | | | | | |////////////|
v +------------+ | | v +------------+ |////////////|
| Scatter/ //| sgt[0]--+ | |// Frame ///| |////////////|
| Gather List| ... | |/ content //| +------------+ ^
|////////////| sgt[N]----+ |////////////| | | | BEM
|////////////| |////////////| | | |
+------------+ +------------+ +------------+ v
BSM = Buffer Start Margin, BEM = Buffer End Margin, both are configured
by dpaa_eth_init_rx_port() for the RX FMan port relevant here.
sg_fd_to_skb() runs in the calling context of rx_default_dqrr() -
the NAPI receive callback - which only expects to receive contiguous
(qm_fd_contig) or scatter/gather (qm_fd_sg) frame descriptors.
Everything else is irrelevant codewise.
The processing done by sg_fd_to_skb() is weird because it does not
conform to the expectations laid out by the aforementioned figure.
Namely, it parses the OFFSET field only for SGT entries with i != 0
(codewise, skb != NULL). In those cases, OFFSET should always be 0.
Also, it does not parse the OFFSET field for the sgt[0] case, the only
case where the buffer offset is meaningful in this context. There, it
uses the fd_off, aka the offset to the Scatter/Gather List in the
Scatter/Gather Buffer from the figure. By equivalence, they should both
be equal to the BSM (in turn, equal to priv->rx_headroom).
This can actually be explained due to the bug which we had in
qm_sg_entry_get_off() until the previous change:
- qm_sg_entry_get_off() did not actually _work_ for sgt[0]. It returned
zero even with a non-zero offset, so fd_off had to be used as a fill-in.
- qm_sg_entry_get_off() always returned zero for sgt[i>0], and that
resulted in no user-visible bug, because the buffer offset _was
supposed_ to be zero for those buffers. So remove it from calculations.
Add assertions about the OFFSET field in both cases (first or subsequent
SGT entries) to make it absolutely obvious when something is not well
handled.
Similar logic can be seen in the driver for the architecturally similar
DPAA2, where dpaa2_eth_build_frag_skb() calls dpaa2_sg_get_offset() only
for i == 0. For the rest, there is even a comment stating the same thing:
* Data in subsequent SG entries is stored from the
* beginning of the buffer, so we don't need to add the
* sg_offset.
Tested on LS1046A.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Link: https://patch.msgid.link/20241029164317.50182-3-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-29 18:43:16 +02:00
|
|
|
/* The offset to data start within the buffer holding
|
|
|
|
|
* the SGT should always be equal to the offset to data
|
|
|
|
|
* start within the first buffer holding the frame.
|
|
|
|
|
*/
|
|
|
|
|
WARN_ON_ONCE(fd_off != qm_sg_entry_get_off(&sgt[i]));
|
2016-11-15 10:41:02 +02:00
|
|
|
skb_reserve(skb, fd_off);
|
|
|
|
|
skb_put(skb, qm_sg_entry_get_len(&sgt[i]));
|
|
|
|
|
} else {
|
|
|
|
|
/* Not the first S/G entry; all data from buffer will
|
|
|
|
|
* be added in an skb fragment; fragment index is offset
|
|
|
|
|
* by one since first S/G entry was incorporated in the
|
|
|
|
|
* linear part of the skb.
|
|
|
|
|
*
|
|
|
|
|
* Caution: 'page' may be a tail page.
|
|
|
|
|
*/
|
|
|
|
|
page = virt_to_page(sg_vaddr);
|
|
|
|
|
head_page = virt_to_head_page(sg_vaddr);
|
|
|
|
|
|
net: dpaa_eth: add assertions about SGT entry offsets in sg_fd_to_skb()
Multi-buffer frame descriptors (FDs) point to a buffer holding a
scatter/gather table (SGT), which is a finite array of fixed-size
entries, the last of which has qm_sg_entry_is_final(&sgt[i]) == true.
Each SGT entry points to a buffer holding pieces of the frame.
DPAARM.pdf explains in the figure called "Internal and External Margins,
Scatter/Gather Frame Format" that the SGT table is located within its
buffer at the same offset as the frame data start is located within the
first packet buffer.
+------------------------+
Scatter/Gather Buffer | First Buffer | Last Buffer
^ +------------+ ^ +-|---->^ +------------+ +->+------------+
| | | | ICEOF | | | | | |////////////|
| +------------+ v | | | | | |////////////|
BSM | |/ part of //| | |BSM | | | |////////////|
| |/ Internal /| | | | | | |////////////|
| |/ Context //| | | | | | |// Frame ///|
| +------------+ | | | | | ... |/ content //|
| | | | | | | | |////////////|
| | | | | | | | |////////////|
v +------------+ | | v +------------+ |////////////|
| Scatter/ //| sgt[0]--+ | |// Frame ///| |////////////|
| Gather List| ... | |/ content //| +------------+ ^
|////////////| sgt[N]----+ |////////////| | | | BEM
|////////////| |////////////| | | |
+------------+ +------------+ +------------+ v
BSM = Buffer Start Margin, BEM = Buffer End Margin, both are configured
by dpaa_eth_init_rx_port() for the RX FMan port relevant here.
sg_fd_to_skb() runs in the calling context of rx_default_dqrr() -
the NAPI receive callback - which only expects to receive contiguous
(qm_fd_contig) or scatter/gather (qm_fd_sg) frame descriptors.
Everything else is irrelevant codewise.
The processing done by sg_fd_to_skb() is weird because it does not
conform to the expectations laid out by the aforementioned figure.
Namely, it parses the OFFSET field only for SGT entries with i != 0
(codewise, skb != NULL). In those cases, OFFSET should always be 0.
Also, it does not parse the OFFSET field for the sgt[0] case, the only
case where the buffer offset is meaningful in this context. There, it
uses the fd_off, aka the offset to the Scatter/Gather List in the
Scatter/Gather Buffer from the figure. By equivalence, they should both
be equal to the BSM (in turn, equal to priv->rx_headroom).
This can actually be explained due to the bug which we had in
qm_sg_entry_get_off() until the previous change:
- qm_sg_entry_get_off() did not actually _work_ for sgt[0]. It returned
zero even with a non-zero offset, so fd_off had to be used as a fill-in.
- qm_sg_entry_get_off() always returned zero for sgt[i>0], and that
resulted in no user-visible bug, because the buffer offset _was
supposed_ to be zero for those buffers. So remove it from calculations.
Add assertions about the OFFSET field in both cases (first or subsequent
SGT entries) to make it absolutely obvious when something is not well
handled.
Similar logic can be seen in the driver for the architecturally similar
DPAA2, where dpaa2_eth_build_frag_skb() calls dpaa2_sg_get_offset() only
for i == 0. For the rest, there is even a comment stating the same thing:
* Data in subsequent SG entries is stored from the
* beginning of the buffer, so we don't need to add the
* sg_offset.
Tested on LS1046A.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Link: https://patch.msgid.link/20241029164317.50182-3-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-29 18:43:16 +02:00
|
|
|
/* Compute offset of sg_vaddr in (possibly tail) page */
|
2016-11-15 10:41:02 +02:00
|
|
|
page_offset = ((unsigned long)sg_vaddr &
|
|
|
|
|
(PAGE_SIZE - 1)) +
|
|
|
|
|
(page_address(page) - page_address(head_page));
|
net: dpaa_eth: add assertions about SGT entry offsets in sg_fd_to_skb()
Multi-buffer frame descriptors (FDs) point to a buffer holding a
scatter/gather table (SGT), which is a finite array of fixed-size
entries, the last of which has qm_sg_entry_is_final(&sgt[i]) == true.
Each SGT entry points to a buffer holding pieces of the frame.
DPAARM.pdf explains in the figure called "Internal and External Margins,
Scatter/Gather Frame Format" that the SGT table is located within its
buffer at the same offset as the frame data start is located within the
first packet buffer.
+------------------------+
Scatter/Gather Buffer | First Buffer | Last Buffer
^ +------------+ ^ +-|---->^ +------------+ +->+------------+
| | | | ICEOF | | | | | |////////////|
| +------------+ v | | | | | |////////////|
BSM | |/ part of //| | |BSM | | | |////////////|
| |/ Internal /| | | | | | |////////////|
| |/ Context //| | | | | | |// Frame ///|
| +------------+ | | | | | ... |/ content //|
| | | | | | | | |////////////|
| | | | | | | | |////////////|
v +------------+ | | v +------------+ |////////////|
| Scatter/ //| sgt[0]--+ | |// Frame ///| |////////////|
| Gather List| ... | |/ content //| +------------+ ^
|////////////| sgt[N]----+ |////////////| | | | BEM
|////////////| |////////////| | | |
+------------+ +------------+ +------------+ v
BSM = Buffer Start Margin, BEM = Buffer End Margin, both are configured
by dpaa_eth_init_rx_port() for the RX FMan port relevant here.
sg_fd_to_skb() runs in the calling context of rx_default_dqrr() -
the NAPI receive callback - which only expects to receive contiguous
(qm_fd_contig) or scatter/gather (qm_fd_sg) frame descriptors.
Everything else is irrelevant codewise.
The processing done by sg_fd_to_skb() is weird because it does not
conform to the expectations laid out by the aforementioned figure.
Namely, it parses the OFFSET field only for SGT entries with i != 0
(codewise, skb != NULL). In those cases, OFFSET should always be 0.
Also, it does not parse the OFFSET field for the sgt[0] case, the only
case where the buffer offset is meaningful in this context. There, it
uses the fd_off, aka the offset to the Scatter/Gather List in the
Scatter/Gather Buffer from the figure. By equivalence, they should both
be equal to the BSM (in turn, equal to priv->rx_headroom).
This can actually be explained due to the bug which we had in
qm_sg_entry_get_off() until the previous change:
- qm_sg_entry_get_off() did not actually _work_ for sgt[0]. It returned
zero even with a non-zero offset, so fd_off had to be used as a fill-in.
- qm_sg_entry_get_off() always returned zero for sgt[i>0], and that
resulted in no user-visible bug, because the buffer offset _was
supposed_ to be zero for those buffers. So remove it from calculations.
Add assertions about the OFFSET field in both cases (first or subsequent
SGT entries) to make it absolutely obvious when something is not well
handled.
Similar logic can be seen in the driver for the architecturally similar
DPAA2, where dpaa2_eth_build_frag_skb() calls dpaa2_sg_get_offset() only
for i == 0. For the rest, there is even a comment stating the same thing:
* Data in subsequent SG entries is stored from the
* beginning of the buffer, so we don't need to add the
* sg_offset.
Tested on LS1046A.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Link: https://patch.msgid.link/20241029164317.50182-3-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-29 18:43:16 +02:00
|
|
|
|
|
|
|
|
/* Non-initial SGT entries should not have a buffer
|
|
|
|
|
* offset.
|
2016-11-15 10:41:02 +02:00
|
|
|
*/
|
net: dpaa_eth: add assertions about SGT entry offsets in sg_fd_to_skb()
Multi-buffer frame descriptors (FDs) point to a buffer holding a
scatter/gather table (SGT), which is a finite array of fixed-size
entries, the last of which has qm_sg_entry_is_final(&sgt[i]) == true.
Each SGT entry points to a buffer holding pieces of the frame.
DPAARM.pdf explains in the figure called "Internal and External Margins,
Scatter/Gather Frame Format" that the SGT table is located within its
buffer at the same offset as the frame data start is located within the
first packet buffer.
+------------------------+
Scatter/Gather Buffer | First Buffer | Last Buffer
^ +------------+ ^ +-|---->^ +------------+ +->+------------+
| | | | ICEOF | | | | | |////////////|
| +------------+ v | | | | | |////////////|
BSM | |/ part of //| | |BSM | | | |////////////|
| |/ Internal /| | | | | | |////////////|
| |/ Context //| | | | | | |// Frame ///|
| +------------+ | | | | | ... |/ content //|
| | | | | | | | |////////////|
| | | | | | | | |////////////|
v +------------+ | | v +------------+ |////////////|
| Scatter/ //| sgt[0]--+ | |// Frame ///| |////////////|
| Gather List| ... | |/ content //| +------------+ ^
|////////////| sgt[N]----+ |////////////| | | | BEM
|////////////| |////////////| | | |
+------------+ +------------+ +------------+ v
BSM = Buffer Start Margin, BEM = Buffer End Margin, both are configured
by dpaa_eth_init_rx_port() for the RX FMan port relevant here.
sg_fd_to_skb() runs in the calling context of rx_default_dqrr() -
the NAPI receive callback - which only expects to receive contiguous
(qm_fd_contig) or scatter/gather (qm_fd_sg) frame descriptors.
Everything else is irrelevant codewise.
The processing done by sg_fd_to_skb() is weird because it does not
conform to the expectations laid out by the aforementioned figure.
Namely, it parses the OFFSET field only for SGT entries with i != 0
(codewise, skb != NULL). In those cases, OFFSET should always be 0.
Also, it does not parse the OFFSET field for the sgt[0] case, the only
case where the buffer offset is meaningful in this context. There, it
uses the fd_off, aka the offset to the Scatter/Gather List in the
Scatter/Gather Buffer from the figure. By equivalence, they should both
be equal to the BSM (in turn, equal to priv->rx_headroom).
This can actually be explained due to the bug which we had in
qm_sg_entry_get_off() until the previous change:
- qm_sg_entry_get_off() did not actually _work_ for sgt[0]. It returned
zero even with a non-zero offset, so fd_off had to be used as a fill-in.
- qm_sg_entry_get_off() always returned zero for sgt[i>0], and that
resulted in no user-visible bug, because the buffer offset _was
supposed_ to be zero for those buffers. So remove it from calculations.
Add assertions about the OFFSET field in both cases (first or subsequent
SGT entries) to make it absolutely obvious when something is not well
handled.
Similar logic can be seen in the driver for the architecturally similar
DPAA2, where dpaa2_eth_build_frag_skb() calls dpaa2_sg_get_offset() only
for i == 0. For the rest, there is even a comment stating the same thing:
* Data in subsequent SG entries is stored from the
* beginning of the buffer, so we don't need to add the
* sg_offset.
Tested on LS1046A.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Link: https://patch.msgid.link/20241029164317.50182-3-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-29 18:43:16 +02:00
|
|
|
WARN_ON_ONCE(qm_sg_entry_get_off(&sgt[i]));
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
/* skb_add_rx_frag() does no checking on the page; if
|
|
|
|
|
* we pass it a tail page, we'll end up with
|
net: dpaa_eth: add assertions about SGT entry offsets in sg_fd_to_skb()
Multi-buffer frame descriptors (FDs) point to a buffer holding a
scatter/gather table (SGT), which is a finite array of fixed-size
entries, the last of which has qm_sg_entry_is_final(&sgt[i]) == true.
Each SGT entry points to a buffer holding pieces of the frame.
DPAARM.pdf explains in the figure called "Internal and External Margins,
Scatter/Gather Frame Format" that the SGT table is located within its
buffer at the same offset as the frame data start is located within the
first packet buffer.
+------------------------+
Scatter/Gather Buffer | First Buffer | Last Buffer
^ +------------+ ^ +-|---->^ +------------+ +->+------------+
| | | | ICEOF | | | | | |////////////|
| +------------+ v | | | | | |////////////|
BSM | |/ part of //| | |BSM | | | |////////////|
| |/ Internal /| | | | | | |////////////|
| |/ Context //| | | | | | |// Frame ///|
| +------------+ | | | | | ... |/ content //|
| | | | | | | | |////////////|
| | | | | | | | |////////////|
v +------------+ | | v +------------+ |////////////|
| Scatter/ //| sgt[0]--+ | |// Frame ///| |////////////|
| Gather List| ... | |/ content //| +------------+ ^
|////////////| sgt[N]----+ |////////////| | | | BEM
|////////////| |////////////| | | |
+------------+ +------------+ +------------+ v
BSM = Buffer Start Margin, BEM = Buffer End Margin, both are configured
by dpaa_eth_init_rx_port() for the RX FMan port relevant here.
sg_fd_to_skb() runs in the calling context of rx_default_dqrr() -
the NAPI receive callback - which only expects to receive contiguous
(qm_fd_contig) or scatter/gather (qm_fd_sg) frame descriptors.
Everything else is irrelevant codewise.
The processing done by sg_fd_to_skb() is weird because it does not
conform to the expectations laid out by the aforementioned figure.
Namely, it parses the OFFSET field only for SGT entries with i != 0
(codewise, skb != NULL). In those cases, OFFSET should always be 0.
Also, it does not parse the OFFSET field for the sgt[0] case, the only
case where the buffer offset is meaningful in this context. There, it
uses the fd_off, aka the offset to the Scatter/Gather List in the
Scatter/Gather Buffer from the figure. By equivalence, they should both
be equal to the BSM (in turn, equal to priv->rx_headroom).
This can actually be explained due to the bug which we had in
qm_sg_entry_get_off() until the previous change:
- qm_sg_entry_get_off() did not actually _work_ for sgt[0]. It returned
zero even with a non-zero offset, so fd_off had to be used as a fill-in.
- qm_sg_entry_get_off() always returned zero for sgt[i>0], and that
resulted in no user-visible bug, because the buffer offset _was
supposed_ to be zero for those buffers. So remove it from calculations.
Add assertions about the OFFSET field in both cases (first or subsequent
SGT entries) to make it absolutely obvious when something is not well
handled.
Similar logic can be seen in the driver for the architecturally similar
DPAA2, where dpaa2_eth_build_frag_skb() calls dpaa2_sg_get_offset() only
for i == 0. For the rest, there is even a comment stating the same thing:
* Data in subsequent SG entries is stored from the
* beginning of the buffer, so we don't need to add the
* sg_offset.
Tested on LS1046A.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Link: https://patch.msgid.link/20241029164317.50182-3-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-29 18:43:16 +02:00
|
|
|
* bad page accounting and eventually with segfaults.
|
2016-11-15 10:41:02 +02:00
|
|
|
*/
|
net: dpaa_eth: add assertions about SGT entry offsets in sg_fd_to_skb()
Multi-buffer frame descriptors (FDs) point to a buffer holding a
scatter/gather table (SGT), which is a finite array of fixed-size
entries, the last of which has qm_sg_entry_is_final(&sgt[i]) == true.
Each SGT entry points to a buffer holding pieces of the frame.
DPAARM.pdf explains in the figure called "Internal and External Margins,
Scatter/Gather Frame Format" that the SGT table is located within its
buffer at the same offset as the frame data start is located within the
first packet buffer.
+------------------------+
Scatter/Gather Buffer | First Buffer | Last Buffer
^ +------------+ ^ +-|---->^ +------------+ +->+------------+
| | | | ICEOF | | | | | |////////////|
| +------------+ v | | | | | |////////////|
BSM | |/ part of //| | |BSM | | | |////////////|
| |/ Internal /| | | | | | |////////////|
| |/ Context //| | | | | | |// Frame ///|
| +------------+ | | | | | ... |/ content //|
| | | | | | | | |////////////|
| | | | | | | | |////////////|
v +------------+ | | v +------------+ |////////////|
| Scatter/ //| sgt[0]--+ | |// Frame ///| |////////////|
| Gather List| ... | |/ content //| +------------+ ^
|////////////| sgt[N]----+ |////////////| | | | BEM
|////////////| |////////////| | | |
+------------+ +------------+ +------------+ v
BSM = Buffer Start Margin, BEM = Buffer End Margin, both are configured
by dpaa_eth_init_rx_port() for the RX FMan port relevant here.
sg_fd_to_skb() runs in the calling context of rx_default_dqrr() -
the NAPI receive callback - which only expects to receive contiguous
(qm_fd_contig) or scatter/gather (qm_fd_sg) frame descriptors.
Everything else is irrelevant codewise.
The processing done by sg_fd_to_skb() is weird because it does not
conform to the expectations laid out by the aforementioned figure.
Namely, it parses the OFFSET field only for SGT entries with i != 0
(codewise, skb != NULL). In those cases, OFFSET should always be 0.
Also, it does not parse the OFFSET field for the sgt[0] case, the only
case where the buffer offset is meaningful in this context. There, it
uses the fd_off, aka the offset to the Scatter/Gather List in the
Scatter/Gather Buffer from the figure. By equivalence, they should both
be equal to the BSM (in turn, equal to priv->rx_headroom).
This can actually be explained due to the bug which we had in
qm_sg_entry_get_off() until the previous change:
- qm_sg_entry_get_off() did not actually _work_ for sgt[0]. It returned
zero even with a non-zero offset, so fd_off had to be used as a fill-in.
- qm_sg_entry_get_off() always returned zero for sgt[i>0], and that
resulted in no user-visible bug, because the buffer offset _was
supposed_ to be zero for those buffers. So remove it from calculations.
Add assertions about the OFFSET field in both cases (first or subsequent
SGT entries) to make it absolutely obvious when something is not well
handled.
Similar logic can be seen in the driver for the architecturally similar
DPAA2, where dpaa2_eth_build_frag_skb() calls dpaa2_sg_get_offset() only
for i == 0. For the rest, there is even a comment stating the same thing:
* Data in subsequent SG entries is stored from the
* beginning of the buffer, so we don't need to add the
* sg_offset.
Tested on LS1046A.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Link: https://patch.msgid.link/20241029164317.50182-3-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-29 18:43:16 +02:00
|
|
|
skb_add_rx_frag(skb, i - 1, head_page, page_offset,
|
|
|
|
|
qm_sg_entry_get_len(&sgt[i]),
|
|
|
|
|
dpaa_bp->size);
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
2019-12-23 09:39:22 +02:00
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
/* Update the pool count for the current {cpu x bpool} */
|
2019-12-23 09:39:22 +02:00
|
|
|
count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
|
2016-11-15 10:41:02 +02:00
|
|
|
(*count_ptr)--;
|
|
|
|
|
|
|
|
|
|
if (qm_sg_entry_is_final(&sgt[i]))
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n");
|
|
|
|
|
|
|
|
|
|
/* free the SG table buffer */
|
2019-10-31 16:37:48 +02:00
|
|
|
free_pages((unsigned long)vaddr, 0);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
return skb;
|
|
|
|
|
|
|
|
|
|
free_buffers:
|
|
|
|
|
/* free all the SG entries */
|
2019-12-23 09:39:22 +02:00
|
|
|
for (j = 0; j < DPAA_SGT_MAX_ENTRIES ; j++) {
|
|
|
|
|
sg_addr = qm_sg_addr(&sgt[j]);
|
2016-11-15 10:41:02 +02:00
|
|
|
sg_vaddr = phys_to_virt(sg_addr);
|
2019-12-23 09:39:22 +02:00
|
|
|
/* all pages 0..i were unmaped */
|
|
|
|
|
if (j > i)
|
|
|
|
|
dma_unmap_page(priv->rx_dma_dev, qm_sg_addr(&sgt[j]),
|
|
|
|
|
DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
|
2019-10-31 16:37:48 +02:00
|
|
|
free_pages((unsigned long)sg_vaddr, 0);
|
2019-12-23 09:39:22 +02:00
|
|
|
/* counters 0..i-1 were decremented */
|
|
|
|
|
if (j >= i) {
|
|
|
|
|
dpaa_bp = dpaa_bpid2pool(sgt[j].bpid);
|
|
|
|
|
if (dpaa_bp) {
|
|
|
|
|
count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
|
|
|
|
|
(*count_ptr)--;
|
|
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
2019-12-23 09:39:22 +02:00
|
|
|
if (qm_sg_entry_is_final(&sgt[j]))
|
2016-11-15 10:41:02 +02:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
/* free the SGT fragment */
|
2019-10-31 16:37:48 +02:00
|
|
|
free_pages((unsigned long)vaddr, 0);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int skb_to_contig_fd(struct dpaa_priv *priv,
|
|
|
|
|
struct sk_buff *skb, struct qm_fd *fd,
|
|
|
|
|
int *offset)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *net_dev = priv->net_dev;
|
|
|
|
|
enum dma_data_direction dma_dir;
|
2020-11-25 18:53:30 +02:00
|
|
|
struct dpaa_eth_swbp *swbp;
|
2019-10-31 16:37:53 +02:00
|
|
|
unsigned char *buff_start;
|
2016-11-15 10:41:02 +02:00
|
|
|
dma_addr_t addr;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
/* We are guaranteed to have at least tx_headroom bytes
|
|
|
|
|
* available, so just use that for offset.
|
|
|
|
|
*/
|
|
|
|
|
fd->bpid = FSL_DPAA_BPID_INV;
|
2019-10-31 16:37:53 +02:00
|
|
|
buff_start = skb->data - priv->tx_headroom;
|
2016-11-15 10:41:02 +02:00
|
|
|
dma_dir = DMA_TO_DEVICE;
|
|
|
|
|
|
2020-11-25 18:53:30 +02:00
|
|
|
swbp = (struct dpaa_eth_swbp *)buff_start;
|
|
|
|
|
swbp->skb = skb;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* Enable L3/L4 hardware checksum computation.
|
|
|
|
|
*
|
|
|
|
|
* We must do this before dma_map_single(DMA_TO_DEVICE), because we may
|
|
|
|
|
* need to write into the skb.
|
|
|
|
|
*/
|
|
|
|
|
err = dpaa_enable_tx_csum(priv, skb, fd,
|
2019-10-31 16:37:53 +02:00
|
|
|
buff_start + DPAA_TX_PRIV_DATA_SIZE);
|
2016-11-15 10:41:02 +02:00
|
|
|
if (unlikely(err < 0)) {
|
|
|
|
|
if (net_ratelimit())
|
|
|
|
|
netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
|
|
|
|
|
err);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Fill in the rest of the FD fields */
|
|
|
|
|
qm_fd_set_contig(fd, priv->tx_headroom, skb->len);
|
2016-12-15 15:13:04 +02:00
|
|
|
fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* Map the entire buffer size that may be seen by FMan, but no more */
|
2019-10-31 16:37:53 +02:00
|
|
|
addr = dma_map_single(priv->tx_dma_dev, buff_start,
|
|
|
|
|
priv->tx_headroom + skb->len, dma_dir);
|
2019-10-23 12:08:44 +03:00
|
|
|
if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
|
2016-11-15 10:41:02 +02:00
|
|
|
if (net_ratelimit())
|
|
|
|
|
netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
qm_fd_addr_set64(fd, addr);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int skb_to_sg_fd(struct dpaa_priv *priv,
|
|
|
|
|
struct sk_buff *skb, struct qm_fd *fd)
|
|
|
|
|
{
|
|
|
|
|
const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
|
|
|
|
|
const int nr_frags = skb_shinfo(skb)->nr_frags;
|
|
|
|
|
struct net_device *net_dev = priv->net_dev;
|
2020-11-25 18:53:30 +02:00
|
|
|
struct dpaa_eth_swbp *swbp;
|
2016-11-15 10:41:02 +02:00
|
|
|
struct qm_sg_entry *sgt;
|
2019-10-31 16:37:54 +02:00
|
|
|
void *buff_start;
|
2016-11-15 10:41:02 +02:00
|
|
|
skb_frag_t *frag;
|
|
|
|
|
dma_addr_t addr;
|
|
|
|
|
size_t frag_len;
|
2019-10-31 16:37:54 +02:00
|
|
|
struct page *p;
|
|
|
|
|
int i, j, err;
|
|
|
|
|
|
|
|
|
|
/* get a page to store the SGTable */
|
|
|
|
|
p = dev_alloc_pages(0);
|
|
|
|
|
if (unlikely(!p)) {
|
|
|
|
|
netdev_err(net_dev, "dev_alloc_pages() failed\n");
|
2016-11-15 10:41:02 +02:00
|
|
|
return -ENOMEM;
|
|
|
|
|
}
|
2019-10-31 16:37:54 +02:00
|
|
|
buff_start = page_address(p);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* Enable L3/L4 hardware checksum computation.
|
|
|
|
|
*
|
|
|
|
|
* We must do this before dma_map_single(DMA_TO_DEVICE), because we may
|
|
|
|
|
* need to write into the skb.
|
|
|
|
|
*/
|
|
|
|
|
err = dpaa_enable_tx_csum(priv, skb, fd,
|
2019-10-31 16:37:54 +02:00
|
|
|
buff_start + DPAA_TX_PRIV_DATA_SIZE);
|
2016-11-15 10:41:02 +02:00
|
|
|
if (unlikely(err < 0)) {
|
|
|
|
|
if (net_ratelimit())
|
|
|
|
|
netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
|
|
|
|
|
err);
|
|
|
|
|
goto csum_failed;
|
|
|
|
|
}
|
|
|
|
|
|
2018-02-26 11:24:01 -06:00
|
|
|
/* SGT[0] is used by the linear part */
|
2019-10-31 16:37:54 +02:00
|
|
|
sgt = (struct qm_sg_entry *)(buff_start + priv->tx_headroom);
|
2018-02-26 11:24:01 -06:00
|
|
|
frag_len = skb_headlen(skb);
|
|
|
|
|
qm_sg_entry_set_len(&sgt[0], frag_len);
|
2016-11-15 10:41:02 +02:00
|
|
|
sgt[0].bpid = FSL_DPAA_BPID_INV;
|
|
|
|
|
sgt[0].offset = 0;
|
2019-10-23 12:08:44 +03:00
|
|
|
addr = dma_map_single(priv->tx_dma_dev, skb->data,
|
2016-11-15 10:41:02 +02:00
|
|
|
skb_headlen(skb), dma_dir);
|
2019-10-23 12:08:44 +03:00
|
|
|
if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
|
|
|
|
|
netdev_err(priv->net_dev, "DMA mapping failed\n");
|
2016-11-15 10:41:02 +02:00
|
|
|
err = -EINVAL;
|
|
|
|
|
goto sg0_map_failed;
|
|
|
|
|
}
|
|
|
|
|
qm_sg_entry_set64(&sgt[0], addr);
|
|
|
|
|
|
|
|
|
|
/* populate the rest of SGT entries */
|
2018-02-26 11:24:01 -06:00
|
|
|
for (i = 0; i < nr_frags; i++) {
|
|
|
|
|
frag = &skb_shinfo(skb)->frags[i];
|
2019-07-24 04:36:15 -07:00
|
|
|
frag_len = skb_frag_size(frag);
|
2016-11-15 10:41:02 +02:00
|
|
|
WARN_ON(!skb_frag_page(frag));
|
2019-10-23 12:08:44 +03:00
|
|
|
addr = skb_frag_dma_map(priv->tx_dma_dev, frag, 0,
|
2016-11-15 10:41:02 +02:00
|
|
|
frag_len, dma_dir);
|
2019-10-23 12:08:44 +03:00
|
|
|
if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
|
|
|
|
|
netdev_err(priv->net_dev, "DMA mapping failed\n");
|
2016-11-15 10:41:02 +02:00
|
|
|
err = -EINVAL;
|
|
|
|
|
goto sg_map_failed;
|
|
|
|
|
}
|
|
|
|
|
|
2018-02-26 11:24:01 -06:00
|
|
|
qm_sg_entry_set_len(&sgt[i + 1], frag_len);
|
|
|
|
|
sgt[i + 1].bpid = FSL_DPAA_BPID_INV;
|
|
|
|
|
sgt[i + 1].offset = 0;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* keep the offset in the address */
|
2018-02-26 11:24:01 -06:00
|
|
|
qm_sg_entry_set64(&sgt[i + 1], addr);
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
2018-02-26 11:24:01 -06:00
|
|
|
|
|
|
|
|
/* Set the final bit in the last used entry of the SGT */
|
|
|
|
|
qm_sg_entry_set_f(&sgt[nr_frags], frag_len);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2019-10-31 16:37:54 +02:00
|
|
|
/* set fd offset to priv->tx_headroom */
|
2016-11-15 10:41:02 +02:00
|
|
|
qm_fd_set_sg(fd, priv->tx_headroom, skb->len);
|
|
|
|
|
|
|
|
|
|
/* DMA map the SGT page */
|
2020-11-25 18:53:30 +02:00
|
|
|
swbp = (struct dpaa_eth_swbp *)buff_start;
|
|
|
|
|
swbp->skb = skb;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2019-10-31 16:37:54 +02:00
|
|
|
addr = dma_map_page(priv->tx_dma_dev, p, 0,
|
|
|
|
|
priv->tx_headroom + DPAA_SGT_SIZE, dma_dir);
|
2019-10-23 12:08:44 +03:00
|
|
|
if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
|
|
|
|
|
netdev_err(priv->net_dev, "DMA mapping failed\n");
|
2016-11-15 10:41:02 +02:00
|
|
|
err = -EINVAL;
|
|
|
|
|
goto sgt_map_failed;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
fd->bpid = FSL_DPAA_BPID_INV;
|
2016-12-15 15:13:04 +02:00
|
|
|
fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
|
2016-11-15 10:41:02 +02:00
|
|
|
qm_fd_addr_set64(fd, addr);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
sgt_map_failed:
|
|
|
|
|
sg_map_failed:
|
|
|
|
|
for (j = 0; j < i; j++)
|
2019-10-23 12:08:44 +03:00
|
|
|
dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[j]),
|
2016-11-15 10:41:02 +02:00
|
|
|
qm_sg_entry_get_len(&sgt[j]), dma_dir);
|
|
|
|
|
sg0_map_failed:
|
|
|
|
|
csum_failed:
|
2019-10-31 16:37:54 +02:00
|
|
|
free_pages((unsigned long)buff_start, 0);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int dpaa_xmit(struct dpaa_priv *priv,
|
|
|
|
|
struct rtnl_link_stats64 *percpu_stats,
|
|
|
|
|
int queue,
|
|
|
|
|
struct qm_fd *fd)
|
|
|
|
|
{
|
|
|
|
|
struct qman_fq *egress_fq;
|
|
|
|
|
int err, i;
|
|
|
|
|
|
|
|
|
|
egress_fq = priv->egress_fqs[queue];
|
|
|
|
|
if (fd->bpid == FSL_DPAA_BPID_INV)
|
2016-12-15 15:13:04 +02:00
|
|
|
fd->cmd |= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue]));
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2016-11-15 10:41:06 +02:00
|
|
|
/* Trace this Tx fd */
|
|
|
|
|
trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd);
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) {
|
|
|
|
|
err = qman_enqueue(egress_fq, fd);
|
|
|
|
|
if (err != -EBUSY)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (unlikely(err < 0)) {
|
|
|
|
|
percpu_stats->tx_fifo_errors++;
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
percpu_stats->tx_packets++;
|
|
|
|
|
percpu_stats->tx_bytes += qm_fd_get_length(fd);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
#ifdef CONFIG_DPAA_ERRATUM_A050385
|
2020-11-25 18:53:35 +02:00
|
|
|
static int dpaa_a050385_wa_skb(struct net_device *net_dev, struct sk_buff **s)
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
{
|
|
|
|
|
struct dpaa_priv *priv = netdev_priv(net_dev);
|
|
|
|
|
struct sk_buff *new_skb, *skb = *s;
|
|
|
|
|
unsigned char *start, i;
|
|
|
|
|
|
|
|
|
|
/* check linear buffer alignment */
|
|
|
|
|
if (!PTR_IS_ALIGNED(skb->data, DPAA_A050385_ALIGN))
|
|
|
|
|
goto workaround;
|
|
|
|
|
|
|
|
|
|
/* linear buffers just need to have an aligned start */
|
|
|
|
|
if (!skb_is_nonlinear(skb))
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
/* linear data size for nonlinear skbs needs to be aligned */
|
|
|
|
|
if (!IS_ALIGNED(skb_headlen(skb), DPAA_A050385_ALIGN))
|
|
|
|
|
goto workaround;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
|
|
|
|
|
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
|
|
|
|
|
|
|
|
|
|
/* all fragments need to have aligned start addresses */
|
|
|
|
|
if (!IS_ALIGNED(skb_frag_off(frag), DPAA_A050385_ALIGN))
|
|
|
|
|
goto workaround;
|
|
|
|
|
|
|
|
|
|
/* all but last fragment need to have aligned sizes */
|
|
|
|
|
if (!IS_ALIGNED(skb_frag_size(frag), DPAA_A050385_ALIGN) &&
|
|
|
|
|
(i < skb_shinfo(skb)->nr_frags - 1))
|
|
|
|
|
goto workaround;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
workaround:
|
|
|
|
|
/* copy all the skb content into a new linear buffer */
|
|
|
|
|
new_skb = netdev_alloc_skb(net_dev, skb->len + DPAA_A050385_ALIGN - 1 +
|
|
|
|
|
priv->tx_headroom);
|
|
|
|
|
if (!new_skb)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
/* NET_SKB_PAD bytes already reserved, adding up to tx_headroom */
|
|
|
|
|
skb_reserve(new_skb, priv->tx_headroom - NET_SKB_PAD);
|
|
|
|
|
|
|
|
|
|
/* Workaround for DPAA_A050385 requires data start to be aligned */
|
|
|
|
|
start = PTR_ALIGN(new_skb->data, DPAA_A050385_ALIGN);
|
2020-04-27 16:02:30 +05:30
|
|
|
if (start - new_skb->data)
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
skb_reserve(new_skb, start - new_skb->data);
|
|
|
|
|
|
|
|
|
|
skb_put(new_skb, skb->len);
|
|
|
|
|
skb_copy_bits(skb, 0, new_skb->data, skb->len);
|
|
|
|
|
skb_copy_header(new_skb, skb);
|
|
|
|
|
new_skb->dev = skb->dev;
|
|
|
|
|
|
2020-12-01 15:52:58 +08:00
|
|
|
/* Copy relevant timestamp info from the old skb to the new */
|
|
|
|
|
if (priv->tx_tstamp) {
|
|
|
|
|
skb_shinfo(new_skb)->tx_flags = skb_shinfo(skb)->tx_flags;
|
|
|
|
|
skb_shinfo(new_skb)->hwtstamps = skb_shinfo(skb)->hwtstamps;
|
|
|
|
|
skb_shinfo(new_skb)->tskey = skb_shinfo(skb)->tskey;
|
|
|
|
|
if (skb->sk)
|
|
|
|
|
skb_set_owner_w(new_skb, skb->sk);
|
|
|
|
|
}
|
|
|
|
|
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
/* We move the headroom when we align it so we have to reset the
|
|
|
|
|
* network and transport header offsets relative to the new data
|
|
|
|
|
* pointer. The checksum offload relies on these offsets.
|
|
|
|
|
*/
|
|
|
|
|
skb_set_network_header(new_skb, skb_network_offset(skb));
|
|
|
|
|
skb_set_transport_header(new_skb, skb_transport_offset(skb));
|
|
|
|
|
|
|
|
|
|
dev_kfree_skb(skb);
|
|
|
|
|
*s = new_skb;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2020-11-25 18:53:36 +02:00
|
|
|
|
|
|
|
|
static int dpaa_a050385_wa_xdpf(struct dpaa_priv *priv,
|
|
|
|
|
struct xdp_frame **init_xdpf)
|
|
|
|
|
{
|
|
|
|
|
struct xdp_frame *new_xdpf, *xdpf = *init_xdpf;
|
2021-02-04 18:49:28 +02:00
|
|
|
void *new_buff, *aligned_data;
|
2020-11-25 18:53:36 +02:00
|
|
|
struct page *p;
|
2021-02-04 18:49:28 +02:00
|
|
|
u32 data_shift;
|
2021-02-04 18:49:26 +02:00
|
|
|
int headroom;
|
2020-11-25 18:53:36 +02:00
|
|
|
|
|
|
|
|
/* Check the data alignment and make sure the headroom is large
|
|
|
|
|
* enough to store the xdpf backpointer. Use an aligned headroom
|
|
|
|
|
* value.
|
|
|
|
|
*
|
|
|
|
|
* Due to alignment constraints, we give XDP access to the full 256
|
|
|
|
|
* byte frame headroom. If the XDP program uses all of it, copy the
|
|
|
|
|
* data to a new buffer and make room for storing the backpointer.
|
|
|
|
|
*/
|
2021-02-04 18:49:27 +02:00
|
|
|
if (PTR_IS_ALIGNED(xdpf->data, DPAA_FD_DATA_ALIGNMENT) &&
|
2020-11-25 18:53:36 +02:00
|
|
|
xdpf->headroom >= priv->tx_headroom) {
|
|
|
|
|
xdpf->headroom = priv->tx_headroom;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2021-02-04 18:49:28 +02:00
|
|
|
/* Try to move the data inside the buffer just enough to align it and
|
|
|
|
|
* store the xdpf backpointer. If the available headroom isn't large
|
|
|
|
|
* enough, resort to allocating a new buffer and copying the data.
|
|
|
|
|
*/
|
|
|
|
|
aligned_data = PTR_ALIGN_DOWN(xdpf->data, DPAA_FD_DATA_ALIGNMENT);
|
|
|
|
|
data_shift = xdpf->data - aligned_data;
|
|
|
|
|
|
|
|
|
|
/* The XDP frame's headroom needs to be large enough to accommodate
|
|
|
|
|
* shifting the data as well as storing the xdpf backpointer.
|
|
|
|
|
*/
|
|
|
|
|
if (xdpf->headroom >= data_shift + priv->tx_headroom) {
|
|
|
|
|
memmove(aligned_data, xdpf->data, xdpf->len);
|
|
|
|
|
xdpf->data = aligned_data;
|
|
|
|
|
xdpf->headroom = priv->tx_headroom;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2021-02-04 18:49:26 +02:00
|
|
|
/* The new xdp_frame is stored in the new buffer. Reserve enough space
|
|
|
|
|
* in the headroom for storing it along with the driver's private
|
|
|
|
|
* info. The headroom needs to be aligned to DPAA_FD_DATA_ALIGNMENT to
|
|
|
|
|
* guarantee the data's alignment in the buffer.
|
|
|
|
|
*/
|
|
|
|
|
headroom = ALIGN(sizeof(*new_xdpf) + priv->tx_headroom,
|
|
|
|
|
DPAA_FD_DATA_ALIGNMENT);
|
|
|
|
|
|
|
|
|
|
/* Assure the extended headroom and data don't overflow the buffer,
|
|
|
|
|
* while maintaining the mandatory tailroom.
|
|
|
|
|
*/
|
|
|
|
|
if (headroom + xdpf->len > DPAA_BP_RAW_SIZE -
|
|
|
|
|
SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2020-11-25 18:53:36 +02:00
|
|
|
p = dev_alloc_pages(0);
|
|
|
|
|
if (unlikely(!p))
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
/* Copy the data to the new buffer at a properly aligned offset */
|
|
|
|
|
new_buff = page_address(p);
|
2021-02-04 18:49:26 +02:00
|
|
|
memcpy(new_buff + headroom, xdpf->data, xdpf->len);
|
2020-11-25 18:53:36 +02:00
|
|
|
|
|
|
|
|
/* Create an XDP frame around the new buffer in a similar fashion
|
|
|
|
|
* to xdp_convert_buff_to_frame.
|
|
|
|
|
*/
|
|
|
|
|
new_xdpf = new_buff;
|
2021-02-04 18:49:26 +02:00
|
|
|
new_xdpf->data = new_buff + headroom;
|
2020-11-25 18:53:36 +02:00
|
|
|
new_xdpf->len = xdpf->len;
|
|
|
|
|
new_xdpf->headroom = priv->tx_headroom;
|
|
|
|
|
new_xdpf->frame_sz = DPAA_BP_RAW_SIZE;
|
2024-12-11 18:26:39 +01:00
|
|
|
new_xdpf->mem_type = MEM_TYPE_PAGE_ORDER0;
|
2020-11-25 18:53:36 +02:00
|
|
|
|
|
|
|
|
/* Release the initial buffer */
|
|
|
|
|
xdp_return_frame_rx_napi(xdpf);
|
|
|
|
|
|
|
|
|
|
*init_xdpf = new_xdpf;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
#endif
|
|
|
|
|
|
2018-09-21 10:50:32 +08:00
|
|
|
static netdev_tx_t
|
|
|
|
|
dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
const int queue_mapping = skb_get_queue_mapping(skb);
|
|
|
|
|
struct rtnl_link_stats64 *percpu_stats;
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
2019-01-17 11:42:27 +02:00
|
|
|
struct netdev_queue *txq;
|
2016-11-15 10:41:02 +02:00
|
|
|
struct dpaa_priv *priv;
|
|
|
|
|
struct qm_fd fd;
|
2024-09-10 10:31:44 -04:00
|
|
|
bool nonlinear;
|
2016-11-15 10:41:02 +02:00
|
|
|
int offset = 0;
|
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
percpu_priv = this_cpu_ptr(priv->percpu_priv);
|
|
|
|
|
percpu_stats = &percpu_priv->stats;
|
|
|
|
|
|
|
|
|
|
qm_fd_clear_fd(&fd);
|
|
|
|
|
|
2024-09-10 10:31:44 -04:00
|
|
|
/* Packet data is always read as 32-bit words, so zero out any part of
|
|
|
|
|
* the skb which might be sent if we have to pad the packet
|
|
|
|
|
*/
|
|
|
|
|
if (__skb_put_padto(skb, ETH_ZLEN, false))
|
|
|
|
|
goto enomem;
|
|
|
|
|
|
|
|
|
|
nonlinear = skb_is_nonlinear(skb);
|
2016-11-15 10:41:02 +02:00
|
|
|
if (!nonlinear) {
|
|
|
|
|
/* We're going to store the skb backpointer at the beginning
|
|
|
|
|
* of the data buffer, so we need a privately owned skb
|
|
|
|
|
*
|
|
|
|
|
* We've made sure skb is not shared in dev->priv_flags,
|
|
|
|
|
* we need to verify the skb head is not cloned
|
|
|
|
|
*/
|
|
|
|
|
if (skb_cow_head(skb, priv->tx_headroom))
|
|
|
|
|
goto enomem;
|
|
|
|
|
|
|
|
|
|
WARN_ON(skb_is_nonlinear(skb));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES;
|
|
|
|
|
* make sure we don't feed FMan with more fragments than it supports.
|
|
|
|
|
*/
|
2018-02-26 11:24:03 -06:00
|
|
|
if (unlikely(nonlinear &&
|
|
|
|
|
(skb_shinfo(skb)->nr_frags >= DPAA_SGT_MAX_ENTRIES))) {
|
2016-11-15 10:41:02 +02:00
|
|
|
/* If the egress skb contains more fragments than we support
|
|
|
|
|
* we have no choice but to linearize it ourselves.
|
|
|
|
|
*/
|
2018-02-26 11:24:03 -06:00
|
|
|
if (__skb_linearize(skb))
|
2016-11-15 10:41:02 +02:00
|
|
|
goto enomem;
|
|
|
|
|
|
2018-02-26 11:24:03 -06:00
|
|
|
nonlinear = skb_is_nonlinear(skb);
|
|
|
|
|
}
|
|
|
|
|
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
#ifdef CONFIG_DPAA_ERRATUM_A050385
|
|
|
|
|
if (unlikely(fman_has_errata_a050385())) {
|
2020-11-25 18:53:35 +02:00
|
|
|
if (dpaa_a050385_wa_skb(net_dev, &skb))
|
dpaa_eth: FMan erratum A050385 workaround
Align buffers, data start, SG fragment length to avoid DMA splits.
These changes prevent the A050385 erratum to manifest itself:
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-04 18:04:28 +02:00
|
|
|
goto enomem;
|
|
|
|
|
nonlinear = skb_is_nonlinear(skb);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2018-02-26 11:24:03 -06:00
|
|
|
if (nonlinear) {
|
|
|
|
|
/* Just create a S/G fd based on the skb */
|
|
|
|
|
err = skb_to_sg_fd(priv, skb, &fd);
|
|
|
|
|
percpu_priv->tx_frag_skbuffs++;
|
|
|
|
|
} else {
|
|
|
|
|
/* Create a contig FD from this skb */
|
2016-11-15 10:41:02 +02:00
|
|
|
err = skb_to_contig_fd(priv, skb, &fd, &offset);
|
|
|
|
|
}
|
|
|
|
|
if (unlikely(err < 0))
|
|
|
|
|
goto skb_to_fd_failed;
|
|
|
|
|
|
2019-01-17 11:42:27 +02:00
|
|
|
txq = netdev_get_tx_queue(net_dev, queue_mapping);
|
|
|
|
|
|
|
|
|
|
/* LLTX requires to do our own update of trans_start */
|
2021-11-16 19:29:22 -08:00
|
|
|
txq_trans_cond_update(txq);
|
2019-01-17 11:42:27 +02:00
|
|
|
|
2018-06-25 20:37:15 +08:00
|
|
|
if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
|
|
|
|
|
fd.cmd |= cpu_to_be32(FM_FD_CMD_UPD);
|
|
|
|
|
skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0))
|
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
|
|
2019-10-31 16:37:50 +02:00
|
|
|
dpaa_cleanup_tx_fd(priv, &fd, false);
|
2016-11-15 10:41:02 +02:00
|
|
|
skb_to_fd_failed:
|
|
|
|
|
enomem:
|
|
|
|
|
percpu_stats->tx_errors++;
|
|
|
|
|
dev_kfree_skb(skb);
|
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dpaa_rx_error(struct net_device *net_dev,
|
|
|
|
|
const struct dpaa_priv *priv,
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv,
|
|
|
|
|
const struct qm_fd *fd,
|
|
|
|
|
u32 fqid)
|
|
|
|
|
{
|
|
|
|
|
if (net_ratelimit())
|
|
|
|
|
netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n",
|
2016-12-15 15:13:04 +02:00
|
|
|
be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
percpu_priv->stats.rx_errors++;
|
|
|
|
|
|
2016-12-15 15:13:04 +02:00
|
|
|
if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA)
|
2016-11-15 10:41:04 +02:00
|
|
|
percpu_priv->rx_errors.dme++;
|
2016-12-15 15:13:04 +02:00
|
|
|
if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL)
|
2016-11-15 10:41:04 +02:00
|
|
|
percpu_priv->rx_errors.fpe++;
|
2016-12-15 15:13:04 +02:00
|
|
|
if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE)
|
2016-11-15 10:41:04 +02:00
|
|
|
percpu_priv->rx_errors.fse++;
|
2016-12-15 15:13:04 +02:00
|
|
|
if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR)
|
2016-11-15 10:41:04 +02:00
|
|
|
percpu_priv->rx_errors.phe++;
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
dpaa_fd_release(net_dev, fd);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dpaa_tx_error(struct net_device *net_dev,
|
|
|
|
|
const struct dpaa_priv *priv,
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv,
|
|
|
|
|
const struct qm_fd *fd,
|
|
|
|
|
u32 fqid)
|
|
|
|
|
{
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
|
|
|
|
|
if (net_ratelimit())
|
|
|
|
|
netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
|
2016-12-15 15:13:04 +02:00
|
|
|
be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
percpu_priv->stats.tx_errors++;
|
|
|
|
|
|
2019-10-31 16:37:50 +02:00
|
|
|
skb = dpaa_cleanup_tx_fd(priv, fd, false);
|
2016-11-15 10:41:02 +02:00
|
|
|
dev_kfree_skb(skb);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_eth_poll(struct napi_struct *napi, int budget)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_napi_portal *np =
|
|
|
|
|
container_of(napi, struct dpaa_napi_portal, napi);
|
2020-11-25 18:53:34 +02:00
|
|
|
int cleaned;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2020-11-25 18:53:34 +02:00
|
|
|
np->xdp_act = 0;
|
|
|
|
|
|
|
|
|
|
cleaned = qman_p_poll_dqrr(np->p, budget);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2023-01-25 08:49:00 +01:00
|
|
|
if (np->xdp_act & XDP_REDIRECT)
|
|
|
|
|
xdp_do_flush();
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
if (cleaned < budget) {
|
2017-01-30 08:22:01 -08:00
|
|
|
napi_complete_done(napi, cleaned);
|
2016-11-15 10:41:02 +02:00
|
|
|
qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
|
|
|
|
|
} else if (np->down) {
|
|
|
|
|
qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return cleaned;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dpaa_tx_conf(struct net_device *net_dev,
|
|
|
|
|
const struct dpaa_priv *priv,
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv,
|
|
|
|
|
const struct qm_fd *fd,
|
|
|
|
|
u32 fqid)
|
|
|
|
|
{
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
|
2016-12-15 15:13:04 +02:00
|
|
|
if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) {
|
2016-11-15 10:41:02 +02:00
|
|
|
if (net_ratelimit())
|
|
|
|
|
netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
|
2016-12-15 15:13:04 +02:00
|
|
|
be32_to_cpu(fd->status) &
|
|
|
|
|
FM_FD_STAT_TX_ERRORS);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
percpu_priv->stats.tx_errors++;
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:04 +02:00
|
|
|
percpu_priv->tx_confirm++;
|
|
|
|
|
|
2019-10-31 16:37:50 +02:00
|
|
|
skb = dpaa_cleanup_tx_fd(priv, fd, true);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
consume_skb(skb);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv,
|
2020-11-02 00:22:56 +01:00
|
|
|
struct qman_portal *portal, bool sched_napi)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
2020-11-02 00:22:56 +01:00
|
|
|
if (sched_napi) {
|
2016-11-15 10:41:02 +02:00
|
|
|
/* Disable QMan IRQ and invoke NAPI */
|
|
|
|
|
qman_p_irqsource_remove(portal, QM_PIRQ_DQRI);
|
|
|
|
|
|
|
|
|
|
percpu_priv->np.p = portal;
|
|
|
|
|
napi_schedule(&percpu_priv->np.napi);
|
2016-11-15 10:41:04 +02:00
|
|
|
percpu_priv->in_interrupt++;
|
2016-11-15 10:41:02 +02:00
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal,
|
|
|
|
|
struct qman_fq *fq,
|
2020-11-02 00:22:55 +01:00
|
|
|
const struct qm_dqrr_entry *dq,
|
|
|
|
|
bool sched_napi)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
struct net_device *net_dev;
|
|
|
|
|
struct dpaa_bp *dpaa_bp;
|
|
|
|
|
struct dpaa_priv *priv;
|
|
|
|
|
|
|
|
|
|
net_dev = dpaa_fq->net_dev;
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
|
|
|
|
|
if (!dpaa_bp)
|
|
|
|
|
return qman_cb_dqrr_consume;
|
|
|
|
|
|
|
|
|
|
percpu_priv = this_cpu_ptr(priv->percpu_priv);
|
|
|
|
|
|
2020-11-02 00:22:56 +01:00
|
|
|
if (dpaa_eth_napi_schedule(percpu_priv, portal, sched_napi))
|
2016-11-15 10:41:02 +02:00
|
|
|
return qman_cb_dqrr_stop;
|
|
|
|
|
|
2018-02-26 11:24:02 -06:00
|
|
|
dpaa_eth_refill_bpools(priv);
|
|
|
|
|
dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
return qman_cb_dqrr_consume;
|
|
|
|
|
}
|
|
|
|
|
|
2020-11-25 18:53:33 +02:00
|
|
|
static int dpaa_xdp_xmit_frame(struct net_device *net_dev,
|
|
|
|
|
struct xdp_frame *xdpf)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_priv *priv = netdev_priv(net_dev);
|
|
|
|
|
struct rtnl_link_stats64 *percpu_stats;
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
struct dpaa_eth_swbp *swbp;
|
|
|
|
|
struct netdev_queue *txq;
|
|
|
|
|
void *buff_start;
|
|
|
|
|
struct qm_fd fd;
|
|
|
|
|
dma_addr_t addr;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
percpu_priv = this_cpu_ptr(priv->percpu_priv);
|
|
|
|
|
percpu_stats = &percpu_priv->stats;
|
|
|
|
|
|
2020-11-25 18:53:36 +02:00
|
|
|
#ifdef CONFIG_DPAA_ERRATUM_A050385
|
|
|
|
|
if (unlikely(fman_has_errata_a050385())) {
|
|
|
|
|
if (dpaa_a050385_wa_xdpf(priv, &xdpf)) {
|
|
|
|
|
err = -ENOMEM;
|
|
|
|
|
goto out_error;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2020-11-25 18:53:33 +02:00
|
|
|
if (xdpf->headroom < DPAA_TX_PRIV_DATA_SIZE) {
|
|
|
|
|
err = -EINVAL;
|
|
|
|
|
goto out_error;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
buff_start = xdpf->data - xdpf->headroom;
|
|
|
|
|
|
|
|
|
|
/* Leave empty the skb backpointer at the start of the buffer.
|
|
|
|
|
* Save the XDP frame for easy cleanup on confirmation.
|
|
|
|
|
*/
|
|
|
|
|
swbp = (struct dpaa_eth_swbp *)buff_start;
|
|
|
|
|
swbp->skb = NULL;
|
|
|
|
|
swbp->xdpf = xdpf;
|
|
|
|
|
|
|
|
|
|
qm_fd_clear_fd(&fd);
|
|
|
|
|
fd.bpid = FSL_DPAA_BPID_INV;
|
|
|
|
|
fd.cmd |= cpu_to_be32(FM_FD_CMD_FCO);
|
|
|
|
|
qm_fd_set_contig(&fd, xdpf->headroom, xdpf->len);
|
|
|
|
|
|
|
|
|
|
addr = dma_map_single(priv->tx_dma_dev, buff_start,
|
|
|
|
|
xdpf->headroom + xdpf->len,
|
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
|
if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
|
|
|
|
|
err = -EINVAL;
|
|
|
|
|
goto out_error;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
qm_fd_addr_set64(&fd, addr);
|
|
|
|
|
|
|
|
|
|
/* Bump the trans_start */
|
|
|
|
|
txq = netdev_get_tx_queue(net_dev, smp_processor_id());
|
2021-11-16 19:29:22 -08:00
|
|
|
txq_trans_cond_update(txq);
|
2020-11-25 18:53:33 +02:00
|
|
|
|
|
|
|
|
err = dpaa_xmit(priv, percpu_stats, smp_processor_id(), &fd);
|
|
|
|
|
if (err) {
|
|
|
|
|
dma_unmap_single(priv->tx_dma_dev, addr,
|
|
|
|
|
qm_fd_get_offset(&fd) + qm_fd_get_length(&fd),
|
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
|
goto out_error;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
out_error:
|
|
|
|
|
percpu_stats->tx_errors++;
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2020-11-25 18:53:31 +02:00
|
|
|
static u32 dpaa_run_xdp(struct dpaa_priv *priv, struct qm_fd *fd, void *vaddr,
|
2020-11-25 18:53:33 +02:00
|
|
|
struct dpaa_fq *dpaa_fq, unsigned int *xdp_meta_len)
|
2020-11-25 18:53:31 +02:00
|
|
|
{
|
|
|
|
|
ssize_t fd_off = qm_fd_get_offset(fd);
|
|
|
|
|
struct bpf_prog *xdp_prog;
|
2020-11-25 18:53:33 +02:00
|
|
|
struct xdp_frame *xdpf;
|
2020-11-25 18:53:31 +02:00
|
|
|
struct xdp_buff xdp;
|
|
|
|
|
u32 xdp_act;
|
2020-11-25 18:53:34 +02:00
|
|
|
int err;
|
2020-11-25 18:53:31 +02:00
|
|
|
|
|
|
|
|
xdp_prog = READ_ONCE(priv->xdp_prog);
|
2021-06-24 18:06:00 +02:00
|
|
|
if (!xdp_prog)
|
2020-11-25 18:53:31 +02:00
|
|
|
return XDP_PASS;
|
|
|
|
|
|
2020-12-22 22:09:28 +01:00
|
|
|
xdp_init_buff(&xdp, DPAA_BP_RAW_SIZE - DPAA_TX_PRIV_DATA_SIZE,
|
|
|
|
|
&dpaa_fq->xdp_rxq);
|
2020-12-22 22:09:29 +01:00
|
|
|
xdp_prepare_buff(&xdp, vaddr + fd_off - XDP_PACKET_HEADROOM,
|
|
|
|
|
XDP_PACKET_HEADROOM, qm_fd_get_length(fd), true);
|
2020-11-25 18:53:31 +02:00
|
|
|
|
2020-11-25 18:53:36 +02:00
|
|
|
/* We reserve a fixed headroom of 256 bytes under the erratum and we
|
|
|
|
|
* offer it all to XDP programs to use. If no room is left for the
|
|
|
|
|
* xdpf backpointer on TX, we will need to copy the data.
|
|
|
|
|
* Disable metadata support since data realignments might be required
|
|
|
|
|
* and the information can be lost.
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_DPAA_ERRATUM_A050385
|
|
|
|
|
if (unlikely(fman_has_errata_a050385())) {
|
|
|
|
|
xdp_set_data_meta_invalid(&xdp);
|
|
|
|
|
xdp.data_hard_start = vaddr;
|
|
|
|
|
xdp.frame_sz = DPAA_BP_RAW_SIZE;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2020-11-25 18:53:31 +02:00
|
|
|
xdp_act = bpf_prog_run_xdp(xdp_prog, &xdp);
|
|
|
|
|
|
|
|
|
|
/* Update the length and the offset of the FD */
|
|
|
|
|
qm_fd_set_contig(fd, xdp.data - vaddr, xdp.data_end - xdp.data);
|
|
|
|
|
|
|
|
|
|
switch (xdp_act) {
|
|
|
|
|
case XDP_PASS:
|
2020-11-25 18:53:36 +02:00
|
|
|
#ifdef CONFIG_DPAA_ERRATUM_A050385
|
|
|
|
|
*xdp_meta_len = xdp_data_meta_unsupported(&xdp) ? 0 :
|
|
|
|
|
xdp.data - xdp.data_meta;
|
|
|
|
|
#else
|
2020-11-25 18:53:31 +02:00
|
|
|
*xdp_meta_len = xdp.data - xdp.data_meta;
|
2020-11-25 18:53:36 +02:00
|
|
|
#endif
|
2020-11-25 18:53:33 +02:00
|
|
|
break;
|
|
|
|
|
case XDP_TX:
|
|
|
|
|
/* We can access the full headroom when sending the frame
|
|
|
|
|
* back out
|
|
|
|
|
*/
|
|
|
|
|
xdp.data_hard_start = vaddr;
|
|
|
|
|
xdp.frame_sz = DPAA_BP_RAW_SIZE;
|
|
|
|
|
xdpf = xdp_convert_buff_to_frame(&xdp);
|
|
|
|
|
if (unlikely(!xdpf)) {
|
|
|
|
|
free_pages((unsigned long)vaddr, 0);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dpaa_xdp_xmit_frame(priv->net_dev, xdpf))
|
|
|
|
|
xdp_return_frame_rx_napi(xdpf);
|
|
|
|
|
|
2020-11-25 18:53:34 +02:00
|
|
|
break;
|
|
|
|
|
case XDP_REDIRECT:
|
|
|
|
|
/* Allow redirect to use the full headroom */
|
|
|
|
|
xdp.data_hard_start = vaddr;
|
|
|
|
|
xdp.frame_sz = DPAA_BP_RAW_SIZE;
|
|
|
|
|
|
|
|
|
|
err = xdp_do_redirect(priv->net_dev, &xdp, xdp_prog);
|
|
|
|
|
if (err) {
|
|
|
|
|
trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
|
|
|
|
|
free_pages((unsigned long)vaddr, 0);
|
|
|
|
|
}
|
2020-11-25 18:53:31 +02:00
|
|
|
break;
|
|
|
|
|
default:
|
2021-11-30 11:08:07 +01:00
|
|
|
bpf_warn_invalid_xdp_action(priv->net_dev, xdp_prog, xdp_act);
|
2020-11-25 18:53:31 +02:00
|
|
|
fallthrough;
|
|
|
|
|
case XDP_ABORTED:
|
|
|
|
|
trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
|
|
|
|
|
fallthrough;
|
|
|
|
|
case XDP_DROP:
|
|
|
|
|
/* Free the buffer */
|
|
|
|
|
free_pages((unsigned long)vaddr, 0);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return xdp_act;
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal,
|
|
|
|
|
struct qman_fq *fq,
|
2020-11-02 00:22:55 +01:00
|
|
|
const struct qm_dqrr_entry *dq,
|
|
|
|
|
bool sched_napi)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
2020-11-25 18:53:31 +02:00
|
|
|
bool ts_valid = false, hash_valid = false;
|
2018-06-25 20:37:15 +08:00
|
|
|
struct skb_shared_hwtstamps *shhwtstamps;
|
2020-11-25 18:53:31 +02:00
|
|
|
unsigned int skb_len, xdp_meta_len = 0;
|
2016-11-15 10:41:02 +02:00
|
|
|
struct rtnl_link_stats64 *percpu_stats;
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
const struct qm_fd *fd = &dq->fd;
|
|
|
|
|
dma_addr_t addr = qm_fd_addr(fd);
|
2020-11-25 18:53:34 +02:00
|
|
|
struct dpaa_napi_portal *np;
|
2016-11-15 10:41:02 +02:00
|
|
|
enum qm_fd_format fd_format;
|
|
|
|
|
struct net_device *net_dev;
|
2017-08-27 16:13:41 +03:00
|
|
|
u32 fd_status, hash_offset;
|
2020-11-25 18:53:31 +02:00
|
|
|
struct qm_sg_entry *sgt;
|
2016-11-15 10:41:02 +02:00
|
|
|
struct dpaa_bp *dpaa_bp;
|
2020-11-25 18:53:33 +02:00
|
|
|
struct dpaa_fq *dpaa_fq;
|
2016-11-15 10:41:02 +02:00
|
|
|
struct dpaa_priv *priv;
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
int *count_ptr;
|
2020-11-25 18:53:31 +02:00
|
|
|
u32 xdp_act;
|
2017-08-27 16:13:41 +03:00
|
|
|
void *vaddr;
|
2020-11-25 18:53:31 +02:00
|
|
|
u32 hash;
|
2018-06-25 20:37:15 +08:00
|
|
|
u64 ns;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2020-11-25 18:53:33 +02:00
|
|
|
dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
|
2016-12-15 15:13:04 +02:00
|
|
|
fd_status = be32_to_cpu(fd->status);
|
|
|
|
|
fd_format = qm_fd_get_format(fd);
|
2020-11-25 18:53:33 +02:00
|
|
|
net_dev = dpaa_fq->net_dev;
|
2016-11-15 10:41:02 +02:00
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
|
|
|
|
|
if (!dpaa_bp)
|
|
|
|
|
return qman_cb_dqrr_consume;
|
|
|
|
|
|
2016-11-15 10:41:06 +02:00
|
|
|
/* Trace the Rx fd */
|
|
|
|
|
trace_dpaa_rx_fd(net_dev, fq, &dq->fd);
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
percpu_priv = this_cpu_ptr(priv->percpu_priv);
|
|
|
|
|
percpu_stats = &percpu_priv->stats;
|
2021-02-18 20:21:06 +02:00
|
|
|
np = &percpu_priv->np;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2020-11-02 00:22:56 +01:00
|
|
|
if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal, sched_napi)))
|
2016-11-15 10:41:02 +02:00
|
|
|
return qman_cb_dqrr_stop;
|
|
|
|
|
|
|
|
|
|
/* Make sure we didn't run out of buffers */
|
|
|
|
|
if (unlikely(dpaa_eth_refill_bpools(priv))) {
|
|
|
|
|
/* Unable to refill the buffer pool due to insufficient
|
|
|
|
|
* system memory. Just release the frame back into the pool,
|
|
|
|
|
* otherwise we'll soon end up with an empty buffer pool.
|
|
|
|
|
*/
|
|
|
|
|
dpaa_fd_release(net_dev, &dq->fd);
|
|
|
|
|
return qman_cb_dqrr_consume;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) {
|
|
|
|
|
if (net_ratelimit())
|
|
|
|
|
netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
|
|
|
|
|
fd_status & FM_FD_STAT_RX_ERRORS);
|
|
|
|
|
|
|
|
|
|
percpu_stats->rx_errors++;
|
|
|
|
|
dpaa_fd_release(net_dev, fd);
|
|
|
|
|
return qman_cb_dqrr_consume;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 16:37:48 +02:00
|
|
|
dma_unmap_page(dpaa_bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE,
|
|
|
|
|
DMA_FROM_DEVICE);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* prefetch the first 64 bytes of the frame or the SGT start */
|
2017-08-27 16:13:41 +03:00
|
|
|
vaddr = phys_to_virt(addr);
|
|
|
|
|
prefetch(vaddr + qm_fd_get_offset(fd));
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* The only FD types that we may receive are contig and S/G */
|
|
|
|
|
WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg));
|
|
|
|
|
|
|
|
|
|
/* Account for either the contig buffer or the SGT buffer (depending on
|
|
|
|
|
* which case we were in) having been removed from the pool.
|
|
|
|
|
*/
|
|
|
|
|
count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
|
|
|
|
|
(*count_ptr)--;
|
|
|
|
|
|
2020-11-25 18:53:31 +02:00
|
|
|
/* Extract the timestamp stored in the headroom before running XDP */
|
|
|
|
|
if (priv->rx_tstamp) {
|
|
|
|
|
if (!fman_port_get_tstamp(priv->mac_dev->port[RX], vaddr, &ns))
|
|
|
|
|
ts_valid = true;
|
|
|
|
|
else
|
|
|
|
|
WARN_ONCE(1, "fman_port_get_tstamp failed!\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Extract the hash stored in the headroom before running XDP */
|
|
|
|
|
if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use &&
|
|
|
|
|
!fman_port_get_hash_result_offset(priv->mac_dev->port[RX],
|
|
|
|
|
&hash_offset)) {
|
2024-10-29 18:43:17 +02:00
|
|
|
hash = be32_to_cpu(*(__be32 *)(vaddr + hash_offset));
|
2020-11-25 18:53:31 +02:00
|
|
|
hash_valid = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (likely(fd_format == qm_fd_contig)) {
|
|
|
|
|
xdp_act = dpaa_run_xdp(priv, (struct qm_fd *)fd, vaddr,
|
2020-11-25 18:53:33 +02:00
|
|
|
dpaa_fq, &xdp_meta_len);
|
2020-11-25 18:53:34 +02:00
|
|
|
np->xdp_act |= xdp_act;
|
2020-11-25 18:53:31 +02:00
|
|
|
if (xdp_act != XDP_PASS) {
|
|
|
|
|
percpu_stats->rx_packets++;
|
|
|
|
|
percpu_stats->rx_bytes += qm_fd_get_length(fd);
|
|
|
|
|
return qman_cb_dqrr_consume;
|
|
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
skb = contig_fd_to_skb(priv, fd);
|
2020-11-25 18:53:31 +02:00
|
|
|
} else {
|
|
|
|
|
/* XDP doesn't support S/G frames. Return the fragments to the
|
|
|
|
|
* buffer pool and release the SGT.
|
|
|
|
|
*/
|
|
|
|
|
if (READ_ONCE(priv->xdp_prog)) {
|
|
|
|
|
WARN_ONCE(1, "S/G frames not supported under XDP\n");
|
|
|
|
|
sgt = vaddr + qm_fd_get_offset(fd);
|
|
|
|
|
dpaa_release_sgt_members(sgt);
|
|
|
|
|
free_pages((unsigned long)vaddr, 0);
|
|
|
|
|
return qman_cb_dqrr_consume;
|
|
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
skb = sg_fd_to_skb(priv, fd);
|
2020-11-25 18:53:31 +02:00
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
if (!skb)
|
|
|
|
|
return qman_cb_dqrr_consume;
|
|
|
|
|
|
2020-11-25 18:53:31 +02:00
|
|
|
if (xdp_meta_len)
|
|
|
|
|
skb_metadata_set(skb, xdp_meta_len);
|
|
|
|
|
|
|
|
|
|
/* Set the previously extracted timestamp */
|
|
|
|
|
if (ts_valid) {
|
2018-06-25 20:37:15 +08:00
|
|
|
shhwtstamps = skb_hwtstamps(skb);
|
|
|
|
|
memset(shhwtstamps, 0, sizeof(*shhwtstamps));
|
2020-11-25 18:53:31 +02:00
|
|
|
shhwtstamps->hwtstamp = ns_to_ktime(ns);
|
2018-06-25 20:37:15 +08:00
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
skb->protocol = eth_type_trans(skb, net_dev);
|
|
|
|
|
|
2020-11-25 18:53:31 +02:00
|
|
|
/* Set the previously extracted hash */
|
|
|
|
|
if (hash_valid) {
|
2017-08-27 16:13:41 +03:00
|
|
|
enum pkt_hash_types type;
|
|
|
|
|
|
|
|
|
|
/* if L4 exists, it was used in the hash generation */
|
|
|
|
|
type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ?
|
|
|
|
|
PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
|
2020-11-25 18:53:31 +02:00
|
|
|
skb_set_hash(skb, hash, type);
|
2017-08-27 16:13:41 +03:00
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
skb_len = skb->len;
|
|
|
|
|
|
2018-03-14 08:37:31 -05:00
|
|
|
if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) {
|
|
|
|
|
percpu_stats->rx_dropped++;
|
2016-11-15 10:41:02 +02:00
|
|
|
return qman_cb_dqrr_consume;
|
2018-03-14 08:37:31 -05:00
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
percpu_stats->rx_packets++;
|
|
|
|
|
percpu_stats->rx_bytes += skb_len;
|
|
|
|
|
|
|
|
|
|
return qman_cb_dqrr_consume;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal,
|
|
|
|
|
struct qman_fq *fq,
|
2020-11-02 00:22:55 +01:00
|
|
|
const struct qm_dqrr_entry *dq,
|
|
|
|
|
bool sched_napi)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
struct net_device *net_dev;
|
|
|
|
|
struct dpaa_priv *priv;
|
|
|
|
|
|
|
|
|
|
net_dev = ((struct dpaa_fq *)fq)->net_dev;
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
|
|
|
|
|
percpu_priv = this_cpu_ptr(priv->percpu_priv);
|
|
|
|
|
|
2020-11-02 00:22:56 +01:00
|
|
|
if (dpaa_eth_napi_schedule(percpu_priv, portal, sched_napi))
|
2016-11-15 10:41:02 +02:00
|
|
|
return qman_cb_dqrr_stop;
|
|
|
|
|
|
|
|
|
|
dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
|
|
|
|
|
|
|
|
|
|
return qman_cb_dqrr_consume;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal,
|
|
|
|
|
struct qman_fq *fq,
|
2020-11-02 00:22:55 +01:00
|
|
|
const struct qm_dqrr_entry *dq,
|
|
|
|
|
bool sched_napi)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
struct net_device *net_dev;
|
|
|
|
|
struct dpaa_priv *priv;
|
|
|
|
|
|
|
|
|
|
net_dev = ((struct dpaa_fq *)fq)->net_dev;
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
|
2016-11-15 10:41:06 +02:00
|
|
|
/* Trace the fd */
|
|
|
|
|
trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd);
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
percpu_priv = this_cpu_ptr(priv->percpu_priv);
|
|
|
|
|
|
2020-11-02 00:22:56 +01:00
|
|
|
if (dpaa_eth_napi_schedule(percpu_priv, portal, sched_napi))
|
2016-11-15 10:41:02 +02:00
|
|
|
return qman_cb_dqrr_stop;
|
|
|
|
|
|
|
|
|
|
dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
|
|
|
|
|
|
|
|
|
|
return qman_cb_dqrr_consume;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void egress_ern(struct qman_portal *portal,
|
|
|
|
|
struct qman_fq *fq,
|
|
|
|
|
const union qm_mr_entry *msg)
|
|
|
|
|
{
|
|
|
|
|
const struct qm_fd *fd = &msg->ern.fd;
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
const struct dpaa_priv *priv;
|
|
|
|
|
struct net_device *net_dev;
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
|
|
|
|
|
net_dev = ((struct dpaa_fq *)fq)->net_dev;
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
percpu_priv = this_cpu_ptr(priv->percpu_priv);
|
|
|
|
|
|
|
|
|
|
percpu_priv->stats.tx_dropped++;
|
|
|
|
|
percpu_priv->stats.tx_fifo_errors++;
|
2016-11-15 10:41:04 +02:00
|
|
|
count_ern(percpu_priv, msg);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2019-10-31 16:37:50 +02:00
|
|
|
skb = dpaa_cleanup_tx_fd(priv, fd, false);
|
2016-11-15 10:41:02 +02:00
|
|
|
dev_kfree_skb_any(skb);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct dpaa_fq_cbs dpaa_fq_cbs = {
|
|
|
|
|
.rx_defq = { .cb = { .dqrr = rx_default_dqrr } },
|
|
|
|
|
.tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } },
|
|
|
|
|
.rx_errq = { .cb = { .dqrr = rx_error_dqrr } },
|
|
|
|
|
.tx_errq = { .cb = { .dqrr = conf_error_dqrr } },
|
|
|
|
|
.egress_ern = { .cb = { .ern = egress_ern } }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void dpaa_eth_napi_enable(struct dpaa_priv *priv)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
int i;
|
|
|
|
|
|
2019-05-27 15:24:05 +03:00
|
|
|
for_each_online_cpu(i) {
|
2016-11-15 10:41:02 +02:00
|
|
|
percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
|
|
|
|
|
|
2020-11-03 20:05:00 +08:00
|
|
|
percpu_priv->np.down = false;
|
2016-11-15 10:41:02 +02:00
|
|
|
napi_enable(&percpu_priv->np.napi);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dpaa_eth_napi_disable(struct dpaa_priv *priv)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
int i;
|
|
|
|
|
|
2019-05-27 15:24:05 +03:00
|
|
|
for_each_online_cpu(i) {
|
2016-11-15 10:41:02 +02:00
|
|
|
percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
|
|
|
|
|
|
2020-11-03 20:05:00 +08:00
|
|
|
percpu_priv->np.down = true;
|
2016-11-15 10:41:02 +02:00
|
|
|
napi_disable(&percpu_priv->np.napi);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_open(struct net_device *net_dev)
|
|
|
|
|
{
|
|
|
|
|
struct mac_device *mac_dev;
|
|
|
|
|
struct dpaa_priv *priv;
|
|
|
|
|
int err, i;
|
|
|
|
|
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
mac_dev = priv->mac_dev;
|
|
|
|
|
dpaa_eth_napi_enable(priv);
|
|
|
|
|
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
err = phylink_of_phy_connect(mac_dev->phylink,
|
|
|
|
|
mac_dev->dev->of_node, 0);
|
2017-11-01 21:10:32 +08:00
|
|
|
if (err)
|
2017-01-04 13:21:29 +02:00
|
|
|
goto phy_init_failed;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
|
|
|
|
|
err = fman_port_enable(mac_dev->port[i]);
|
|
|
|
|
if (err)
|
|
|
|
|
goto mac_start_failed;
|
|
|
|
|
}
|
|
|
|
|
|
2022-08-18 12:16:28 -04:00
|
|
|
err = priv->mac_dev->enable(mac_dev->fman_mac);
|
2016-11-15 10:41:02 +02:00
|
|
|
if (err < 0) {
|
2022-08-18 12:16:28 -04:00
|
|
|
netif_err(priv, ifup, net_dev, "mac_dev->enable() = %d\n", err);
|
2016-11-15 10:41:02 +02:00
|
|
|
goto mac_start_failed;
|
|
|
|
|
}
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
phylink_start(mac_dev->phylink);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
netif_tx_start_all_queues(net_dev);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
mac_start_failed:
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
|
|
|
|
|
fman_port_disable(mac_dev->port[i]);
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
phylink_disconnect_phy(mac_dev->phylink);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2017-01-04 13:21:29 +02:00
|
|
|
phy_init_failed:
|
2016-11-15 10:41:02 +02:00
|
|
|
dpaa_eth_napi_disable(priv);
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_eth_stop(struct net_device *net_dev)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_priv *priv;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = dpaa_stop(net_dev);
|
|
|
|
|
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
dpaa_eth_napi_disable(priv);
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2020-11-25 18:53:32 +02:00
|
|
|
static bool xdp_validate_mtu(struct dpaa_priv *priv, int mtu)
|
|
|
|
|
{
|
|
|
|
|
int max_contig_data = priv->dpaa_bp->size - priv->rx_headroom;
|
|
|
|
|
|
|
|
|
|
/* We do not support S/G fragments when XDP is enabled.
|
|
|
|
|
* Limit the MTU in relation to the buffer size.
|
|
|
|
|
*/
|
|
|
|
|
if (mtu + VLAN_ETH_HLEN + ETH_FCS_LEN > max_contig_data) {
|
|
|
|
|
dev_warn(priv->net_dev->dev.parent,
|
|
|
|
|
"The maximum MTU for XDP is %d\n",
|
|
|
|
|
max_contig_data - VLAN_ETH_HLEN - ETH_FCS_LEN);
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_change_mtu(struct net_device *net_dev, int new_mtu)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_priv *priv = netdev_priv(net_dev);
|
|
|
|
|
|
|
|
|
|
if (priv->xdp_prog && !xdp_validate_mtu(priv, new_mtu))
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
2024-05-06 10:28:12 +00:00
|
|
|
WRITE_ONCE(net_dev->mtu, new_mtu);
|
2020-11-25 18:53:32 +02:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2020-11-25 18:53:31 +02:00
|
|
|
static int dpaa_setup_xdp(struct net_device *net_dev, struct netdev_bpf *bpf)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_priv *priv = netdev_priv(net_dev);
|
|
|
|
|
struct bpf_prog *old_prog;
|
2020-11-25 18:53:32 +02:00
|
|
|
int err;
|
2020-11-25 18:53:31 +02:00
|
|
|
bool up;
|
|
|
|
|
|
|
|
|
|
/* S/G fragments are not supported in XDP-mode */
|
2020-11-25 18:53:32 +02:00
|
|
|
if (bpf->prog && !xdp_validate_mtu(priv, net_dev->mtu)) {
|
2020-11-25 18:53:31 +02:00
|
|
|
NL_SET_ERR_MSG_MOD(bpf->extack, "MTU too large for XDP");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
up = netif_running(net_dev);
|
|
|
|
|
|
|
|
|
|
if (up)
|
|
|
|
|
dpaa_eth_stop(net_dev);
|
|
|
|
|
|
|
|
|
|
old_prog = xchg(&priv->xdp_prog, bpf->prog);
|
|
|
|
|
if (old_prog)
|
|
|
|
|
bpf_prog_put(old_prog);
|
|
|
|
|
|
|
|
|
|
if (up) {
|
|
|
|
|
err = dpaa_open(net_dev);
|
|
|
|
|
if (err) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(bpf->extack, "dpaa_open() failed");
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_xdp(struct net_device *net_dev, struct netdev_bpf *xdp)
|
|
|
|
|
{
|
|
|
|
|
switch (xdp->command) {
|
|
|
|
|
case XDP_SETUP_PROG:
|
|
|
|
|
return dpaa_setup_xdp(net_dev, xdp);
|
|
|
|
|
default:
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-11-25 18:53:34 +02:00
|
|
|
static int dpaa_xdp_xmit(struct net_device *net_dev, int n,
|
|
|
|
|
struct xdp_frame **frames, u32 flags)
|
|
|
|
|
{
|
|
|
|
|
struct xdp_frame *xdpf;
|
2021-03-08 12:06:58 +01:00
|
|
|
int i, nxmit = 0;
|
2020-11-25 18:53:34 +02:00
|
|
|
|
|
|
|
|
if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
if (!netif_running(net_dev))
|
|
|
|
|
return -ENETDOWN;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < n; i++) {
|
|
|
|
|
xdpf = frames[i];
|
2021-03-08 12:06:58 +01:00
|
|
|
if (dpaa_xdp_xmit_frame(net_dev, xdpf))
|
|
|
|
|
break;
|
|
|
|
|
nxmit++;
|
2020-11-25 18:53:34 +02:00
|
|
|
}
|
|
|
|
|
|
2021-03-08 12:06:58 +01:00
|
|
|
return nxmit;
|
2020-11-25 18:53:34 +02:00
|
|
|
}
|
|
|
|
|
|
2025-05-08 15:47:52 +03:00
|
|
|
static int dpaa_hwtstamp_get(struct net_device *dev,
|
|
|
|
|
struct kernel_hwtstamp_config *config)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_priv *priv = netdev_priv(dev);
|
|
|
|
|
|
|
|
|
|
config->tx_type = priv->tx_tstamp ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
|
|
|
|
|
config->rx_filter = priv->rx_tstamp ? HWTSTAMP_FILTER_ALL :
|
|
|
|
|
HWTSTAMP_FILTER_NONE;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2025-05-08 15:47:51 +03:00
|
|
|
static int dpaa_hwtstamp_set(struct net_device *dev,
|
|
|
|
|
struct kernel_hwtstamp_config *config,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
2018-06-25 20:37:15 +08:00
|
|
|
{
|
|
|
|
|
struct dpaa_priv *priv = netdev_priv(dev);
|
|
|
|
|
|
2025-05-08 15:47:51 +03:00
|
|
|
switch (config->tx_type) {
|
2018-06-25 20:37:15 +08:00
|
|
|
case HWTSTAMP_TX_OFF:
|
|
|
|
|
/* Couldn't disable rx/tx timestamping separately.
|
|
|
|
|
* Do nothing here.
|
|
|
|
|
*/
|
|
|
|
|
priv->tx_tstamp = false;
|
|
|
|
|
break;
|
|
|
|
|
case HWTSTAMP_TX_ON:
|
|
|
|
|
priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true);
|
|
|
|
|
priv->tx_tstamp = true;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
return -ERANGE;
|
|
|
|
|
}
|
|
|
|
|
|
2025-05-08 15:47:51 +03:00
|
|
|
if (config->rx_filter == HWTSTAMP_FILTER_NONE) {
|
2018-06-25 20:37:15 +08:00
|
|
|
/* Couldn't disable rx/tx timestamping separately.
|
|
|
|
|
* Do nothing here.
|
|
|
|
|
*/
|
|
|
|
|
priv->rx_tstamp = false;
|
|
|
|
|
} else {
|
|
|
|
|
priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true);
|
|
|
|
|
priv->rx_tstamp = true;
|
|
|
|
|
/* TS is set for all frame types, not only those requested */
|
2025-05-08 15:47:51 +03:00
|
|
|
config->rx_filter = HWTSTAMP_FILTER_ALL;
|
2018-06-25 20:37:15 +08:00
|
|
|
}
|
|
|
|
|
|
2025-05-08 15:47:51 +03:00
|
|
|
return 0;
|
2018-06-25 20:37:15 +08:00
|
|
|
}
|
|
|
|
|
|
2017-02-20 16:54:18 +01:00
|
|
|
static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
|
|
|
|
|
{
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
struct dpaa_priv *priv = netdev_priv(net_dev);
|
2018-06-25 20:37:15 +08:00
|
|
|
|
2025-05-08 15:47:53 +03:00
|
|
|
return phylink_mii_ioctl(priv->mac_dev->phylink, rq, cmd);
|
2017-02-20 16:54:18 +01:00
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
static const struct net_device_ops dpaa_ops = {
|
|
|
|
|
.ndo_open = dpaa_open,
|
|
|
|
|
.ndo_start_xmit = dpaa_start_xmit,
|
|
|
|
|
.ndo_stop = dpaa_eth_stop,
|
|
|
|
|
.ndo_tx_timeout = dpaa_tx_timeout,
|
|
|
|
|
.ndo_get_stats64 = dpaa_get_stats64,
|
|
|
|
|
.ndo_set_mac_address = dpaa_set_mac_address,
|
|
|
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
|
|
|
.ndo_set_rx_mode = dpaa_set_rx_mode,
|
2021-07-27 15:45:13 +02:00
|
|
|
.ndo_eth_ioctl = dpaa_ioctl,
|
2016-07-25 16:54:56 +03:00
|
|
|
.ndo_setup_tc = dpaa_setup_tc,
|
2020-11-25 18:53:32 +02:00
|
|
|
.ndo_change_mtu = dpaa_change_mtu,
|
2020-11-25 18:53:31 +02:00
|
|
|
.ndo_bpf = dpaa_xdp,
|
2020-11-25 18:53:34 +02:00
|
|
|
.ndo_xdp_xmit = dpaa_xdp_xmit,
|
2025-05-08 15:47:52 +03:00
|
|
|
.ndo_hwtstamp_get = dpaa_hwtstamp_get,
|
2025-05-08 15:47:51 +03:00
|
|
|
.ndo_hwtstamp_set = dpaa_hwtstamp_set,
|
2016-11-15 10:41:02 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int dpaa_napi_add(struct net_device *net_dev)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_priv *priv = netdev_priv(net_dev);
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
int cpu;
|
|
|
|
|
|
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
|
|
|
percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
|
|
|
|
|
|
2022-09-27 06:27:53 -07:00
|
|
|
netif_napi_add(net_dev, &percpu_priv->np.napi, dpaa_eth_poll);
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dpaa_napi_del(struct net_device *net_dev)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_priv *priv = netdev_priv(net_dev);
|
|
|
|
|
struct dpaa_percpu_priv *percpu_priv;
|
|
|
|
|
int cpu;
|
|
|
|
|
|
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
|
|
|
percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
|
|
|
|
|
|
2024-08-22 15:20:42 +08:00
|
|
|
__netif_napi_del(&percpu_priv->np.napi);
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
2024-08-22 15:20:42 +08:00
|
|
|
synchronize_net();
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp,
|
|
|
|
|
struct bm_buffer *bmb)
|
|
|
|
|
{
|
|
|
|
|
dma_addr_t addr = bm_buf_addr(bmb);
|
|
|
|
|
|
2019-10-31 16:37:48 +02:00
|
|
|
dma_unmap_page(bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE,
|
|
|
|
|
DMA_FROM_DEVICE);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
skb_free_frag(phys_to_virt(addr));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Alloc the dpaa_bp struct and configure default values */
|
|
|
|
|
static struct dpaa_bp *dpaa_bp_alloc(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct dpaa_bp *dpaa_bp;
|
|
|
|
|
|
|
|
|
|
dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL);
|
|
|
|
|
if (!dpaa_bp)
|
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
|
|
dpaa_bp->bpid = FSL_DPAA_BPID_INV;
|
|
|
|
|
dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count);
|
2017-08-27 16:13:43 +03:00
|
|
|
if (!dpaa_bp->percpu_count)
|
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT;
|
|
|
|
|
|
|
|
|
|
dpaa_bp->seed_cb = dpaa_bp_seed;
|
|
|
|
|
dpaa_bp->free_buf_cb = dpaa_bp_free_pf;
|
|
|
|
|
|
|
|
|
|
return dpaa_bp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR.
|
|
|
|
|
* We won't be sending congestion notifications to FMan; for now, we just use
|
|
|
|
|
* this CGR to generate enqueue rejections to FMan in order to drop the frames
|
|
|
|
|
* before they reach our ingress queues and eat up memory.
|
|
|
|
|
*/
|
|
|
|
|
static int dpaa_ingress_cgr_init(struct dpaa_priv *priv)
|
|
|
|
|
{
|
|
|
|
|
struct qm_mcc_initcgr initcgr;
|
|
|
|
|
u32 cs_th;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid);
|
|
|
|
|
if (err < 0) {
|
|
|
|
|
if (netif_msg_drv(priv))
|
|
|
|
|
pr_err("Error %d allocating CGR ID\n", err);
|
|
|
|
|
goto out_error;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Enable CS TD, but disable Congestion State Change Notifications. */
|
2017-01-04 13:21:30 +02:00
|
|
|
memset(&initcgr, 0, sizeof(initcgr));
|
2016-12-15 15:13:04 +02:00
|
|
|
initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES);
|
2016-11-15 10:41:02 +02:00
|
|
|
initcgr.cgr.cscn_en = QM_CGR_EN;
|
|
|
|
|
cs_th = DPAA_INGRESS_CS_THRESHOLD;
|
|
|
|
|
qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
|
|
|
|
|
|
2016-12-15 15:13:04 +02:00
|
|
|
initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
|
2016-11-15 10:41:02 +02:00
|
|
|
initcgr.cgr.cstd_en = QM_CGR_EN;
|
|
|
|
|
|
|
|
|
|
/* This CGR will be associated with the SWP affined to the current CPU.
|
|
|
|
|
* However, we'll place all our ingress FQs in it.
|
|
|
|
|
*/
|
|
|
|
|
err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT,
|
|
|
|
|
&initcgr);
|
|
|
|
|
if (err < 0) {
|
|
|
|
|
if (netif_msg_drv(priv))
|
|
|
|
|
pr_err("Error %d creating ingress CGR with ID %d\n",
|
|
|
|
|
err, priv->ingress_cgr.cgrid);
|
|
|
|
|
qman_release_cgrid(priv->ingress_cgr.cgrid);
|
|
|
|
|
goto out_error;
|
|
|
|
|
}
|
|
|
|
|
if (netif_msg_drv(priv))
|
|
|
|
|
pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n",
|
|
|
|
|
priv->ingress_cgr.cgrid, priv->mac_dev->addr);
|
|
|
|
|
|
|
|
|
|
priv->use_ingress_cgr = true;
|
|
|
|
|
|
|
|
|
|
out_error:
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2020-11-02 20:34:36 +02:00
|
|
|
static u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl,
|
|
|
|
|
enum port_type port)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
u16 headroom;
|
|
|
|
|
|
|
|
|
|
/* The frame headroom must accommodate:
|
|
|
|
|
* - the driver private data area
|
|
|
|
|
* - parse results, hash results, timestamp if selected
|
|
|
|
|
* If either hash results or time stamp are selected, both will
|
|
|
|
|
* be copied to/from the frame headroom, as TS is located between PR and
|
|
|
|
|
* HR in the IC and IC copy size has a granularity of 16bytes
|
|
|
|
|
* (see description of FMBM_RICP and FMBM_TICP registers in DPAARM)
|
|
|
|
|
*
|
|
|
|
|
* Also make sure the headroom is a multiple of data_align bytes
|
|
|
|
|
*/
|
2020-11-02 20:34:36 +02:00
|
|
|
headroom = (u16)(bl[port].priv_data_size + DPAA_HWA_SIZE);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2020-11-25 18:53:36 +02:00
|
|
|
if (port == RX) {
|
|
|
|
|
#ifdef CONFIG_DPAA_ERRATUM_A050385
|
|
|
|
|
if (unlikely(fman_has_errata_a050385()))
|
|
|
|
|
headroom = XDP_PACKET_HEADROOM;
|
|
|
|
|
#endif
|
|
|
|
|
|
2020-11-02 20:34:36 +02:00
|
|
|
return ALIGN(headroom, DPAA_FD_RX_DATA_ALIGNMENT);
|
2020-11-25 18:53:36 +02:00
|
|
|
} else {
|
2020-11-02 20:34:36 +02:00
|
|
|
return ALIGN(headroom, DPAA_FD_DATA_ALIGNMENT);
|
2020-11-25 18:53:36 +02:00
|
|
|
}
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dpaa_eth_probe(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *net_dev = NULL;
|
2019-10-31 16:37:47 +02:00
|
|
|
struct dpaa_bp *dpaa_bp = NULL;
|
2016-11-15 10:41:02 +02:00
|
|
|
struct dpaa_fq *dpaa_fq, *tmp;
|
|
|
|
|
struct dpaa_priv *priv = NULL;
|
|
|
|
|
struct fm_port_fqs port_fqs;
|
|
|
|
|
struct mac_device *mac_dev;
|
2019-10-31 16:37:47 +02:00
|
|
|
int err = 0, channel;
|
2016-11-15 10:41:02 +02:00
|
|
|
struct device *dev;
|
|
|
|
|
|
2019-10-23 12:08:44 +03:00
|
|
|
dev = &pdev->dev;
|
|
|
|
|
|
2019-10-23 12:08:41 +03:00
|
|
|
err = bman_is_probed();
|
|
|
|
|
if (!err)
|
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
|
if (err < 0) {
|
2019-10-23 12:08:44 +03:00
|
|
|
dev_err(dev, "failing probe due to bman probe error\n");
|
2019-10-23 12:08:41 +03:00
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
err = qman_is_probed();
|
|
|
|
|
if (!err)
|
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
|
if (err < 0) {
|
2019-10-23 12:08:44 +03:00
|
|
|
dev_err(dev, "failing probe due to qman probe error\n");
|
2019-10-23 12:08:41 +03:00
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
err = bman_portals_probed();
|
|
|
|
|
if (!err)
|
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
|
if (err < 0) {
|
2019-10-23 12:08:44 +03:00
|
|
|
dev_err(dev,
|
2019-10-23 12:08:41 +03:00
|
|
|
"failing probe due to bman portals probe error\n");
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
err = qman_portals_probed();
|
|
|
|
|
if (!err)
|
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
|
if (err < 0) {
|
2019-10-23 12:08:44 +03:00
|
|
|
dev_err(dev,
|
2019-10-23 12:08:41 +03:00
|
|
|
"failing probe due to qman portals probe error\n");
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
/* Allocate this early, so we can store relevant information in
|
|
|
|
|
* the private area
|
|
|
|
|
*/
|
2024-07-14 01:53:33 +03:00
|
|
|
net_dev = alloc_etherdev_mq(sizeof(*priv), dpaa_max_num_txqs());
|
2016-11-15 10:41:02 +02:00
|
|
|
if (!net_dev) {
|
|
|
|
|
dev_err(dev, "alloc_etherdev_mq() failed\n");
|
2017-10-16 21:36:08 +03:00
|
|
|
return -ENOMEM;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Do this here, so we can be verbose early */
|
dpaa_eth: fix usage as DSA master, try 3
The dpaa-eth driver probes on compatible string for the MAC node, and
the fman/mac.c driver allocates a dpaa-ethernet platform device that
triggers the probing of the dpaa-eth net device driver.
All of this is fine, but the problem is that the struct device of the
dpaa_eth net_device is 2 parents away from the MAC which can be
referenced via of_node. So of_find_net_device_by_node can't find it, and
DSA switches won't be able to probe on top of FMan ports.
It would be a bit silly to modify a core function
(of_find_net_device_by_node) to look for dev->parent->parent->of_node
just for one driver. We're just 1 step away from implementing full
recursion.
Actually there have already been at least 2 previous attempts to make
this work:
- Commit a1a50c8e4c24 ("fsl/man: Inherit parent device and of_node")
- One or more of the patches in "[v3,0/6] adapt DPAA drivers for DSA":
https://patchwork.ozlabs.org/project/netdev/cover/1508178970-28945-1-git-send-email-madalin.bucur@nxp.com/
(I couldn't really figure out which one was supposed to solve the
problem and how).
Point being, it looks like this is still pretty much a problem today.
On T1040, the /sys/class/net/eth0 symlink currently points to
../../devices/platform/ffe000000.soc/ffe400000.fman/ffe4e6000.ethernet/dpaa-ethernet.0/net/eth0
which pretty much illustrates the problem. The closest of_node we've got
is the "fsl,fman-memac" at /soc@ffe000000/fman@400000/ethernet@e6000,
which is what we'd like to be able to reference from DSA as host port.
For of_find_net_device_by_node to find the eth0 port, we would need the
parent of the eth0 net_device to not be the "dpaa-ethernet" platform
device, but to point 1 level higher, aka the "fsl,fman-memac" node
directly. The new sysfs path would look like this:
../../devices/platform/ffe000000.soc/ffe400000.fman/ffe4e6000.ethernet/net/eth0
And this is exactly what SET_NETDEV_DEV does. It sets the parent of the
net_device. The new parent has an of_node associated with it, and
of_dev_node_match already checks for the of_node of the device or of its
parent.
Fixes: a1a50c8e4c24 ("fsl/man: Inherit parent device and of_node")
Fixes: c6e26ea8c893 ("dpaa_eth: change device used")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-05-25 00:22:51 +03:00
|
|
|
SET_NETDEV_DEV(net_dev, dev->parent);
|
2016-11-15 10:41:02 +02:00
|
|
|
dev_set_drvdata(dev, net_dev);
|
|
|
|
|
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
priv->net_dev = net_dev;
|
|
|
|
|
|
|
|
|
|
priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT);
|
|
|
|
|
|
2024-07-14 01:53:33 +03:00
|
|
|
priv->egress_fqs = devm_kcalloc(dev, dpaa_max_num_txqs(),
|
|
|
|
|
sizeof(*priv->egress_fqs),
|
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
if (!priv->egress_fqs) {
|
|
|
|
|
err = -ENOMEM;
|
|
|
|
|
goto free_netdev;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
priv->conf_fqs = devm_kcalloc(dev, dpaa_max_num_txqs(),
|
|
|
|
|
sizeof(*priv->conf_fqs),
|
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
if (!priv->conf_fqs) {
|
|
|
|
|
err = -ENOMEM;
|
|
|
|
|
goto free_netdev;
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
mac_dev = dpaa_mac_dev_get(pdev);
|
|
|
|
|
if (IS_ERR(mac_dev)) {
|
2019-10-23 12:08:44 +03:00
|
|
|
netdev_err(net_dev, "dpaa_mac_dev_get() failed\n");
|
2016-11-15 10:41:02 +02:00
|
|
|
err = PTR_ERR(mac_dev);
|
2017-10-16 21:36:08 +03:00
|
|
|
goto free_netdev;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
2019-10-23 12:08:44 +03:00
|
|
|
/* Devices used for DMA mapping */
|
|
|
|
|
priv->rx_dma_dev = fman_port_get_device(mac_dev->port[RX]);
|
|
|
|
|
priv->tx_dma_dev = fman_port_get_device(mac_dev->port[TX]);
|
|
|
|
|
err = dma_coerce_mask_and_coherent(priv->rx_dma_dev, DMA_BIT_MASK(40));
|
|
|
|
|
if (!err)
|
|
|
|
|
err = dma_coerce_mask_and_coherent(priv->tx_dma_dev,
|
|
|
|
|
DMA_BIT_MASK(40));
|
|
|
|
|
if (err) {
|
|
|
|
|
netdev_err(net_dev, "dma_coerce_mask_and_coherent() failed\n");
|
2020-07-20 22:28:29 +08:00
|
|
|
goto free_netdev;
|
2019-10-23 12:08:44 +03:00
|
|
|
}
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
/* If fsl_fm_max_frm is set to a higher value than the all-common 1500,
|
|
|
|
|
* we choose conservatively and let the user explicitly set a higher
|
|
|
|
|
* MTU via ifconfig. Otherwise, the user may end up with different MTUs
|
|
|
|
|
* in the same LAN.
|
|
|
|
|
* If on the other hand fsl_fm_max_frm has been chosen below 1500,
|
|
|
|
|
* start with the maximum allowed.
|
|
|
|
|
*/
|
|
|
|
|
net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN);
|
|
|
|
|
|
|
|
|
|
netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n",
|
|
|
|
|
net_dev->mtu);
|
|
|
|
|
|
|
|
|
|
priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */
|
|
|
|
|
priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */
|
|
|
|
|
|
|
|
|
|
/* bp init */
|
2019-10-31 16:37:47 +02:00
|
|
|
dpaa_bp = dpaa_bp_alloc(dev);
|
|
|
|
|
if (IS_ERR(dpaa_bp)) {
|
|
|
|
|
err = PTR_ERR(dpaa_bp);
|
|
|
|
|
goto free_dpaa_bps;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
2019-10-31 16:37:47 +02:00
|
|
|
/* the raw size of the buffers used for reception */
|
|
|
|
|
dpaa_bp->raw_size = DPAA_BP_RAW_SIZE;
|
|
|
|
|
/* avoid runtime computations by keeping the usable size here */
|
|
|
|
|
dpaa_bp->size = dpaa_bp_size(dpaa_bp->raw_size);
|
|
|
|
|
dpaa_bp->priv = priv;
|
|
|
|
|
|
|
|
|
|
err = dpaa_bp_alloc_pool(dpaa_bp);
|
|
|
|
|
if (err < 0)
|
|
|
|
|
goto free_dpaa_bps;
|
|
|
|
|
priv->dpaa_bp = dpaa_bp;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&priv->dpaa_fq_list);
|
|
|
|
|
|
|
|
|
|
memset(&port_fqs, 0, sizeof(port_fqs));
|
|
|
|
|
|
|
|
|
|
err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs);
|
|
|
|
|
if (err < 0) {
|
|
|
|
|
dev_err(dev, "dpaa_alloc_all_fqs() failed\n");
|
2017-10-16 21:36:08 +03:00
|
|
|
goto free_dpaa_bps;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
priv->mac_dev = mac_dev;
|
|
|
|
|
|
|
|
|
|
channel = dpaa_get_channel();
|
|
|
|
|
if (channel < 0) {
|
|
|
|
|
dev_err(dev, "dpaa_get_channel() failed\n");
|
|
|
|
|
err = channel;
|
2017-10-16 21:36:08 +03:00
|
|
|
goto free_dpaa_bps;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
priv->channel = (u16)channel;
|
|
|
|
|
|
2018-02-12 19:23:43 -05:00
|
|
|
/* Walk the CPUs with affine portals
|
2016-11-15 10:41:02 +02:00
|
|
|
* and add this pool channel to each's dequeue mask.
|
|
|
|
|
*/
|
2019-10-31 16:37:59 +02:00
|
|
|
dpaa_eth_add_channel(priv->channel, &pdev->dev);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2024-07-14 01:53:32 +03:00
|
|
|
err = dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]);
|
|
|
|
|
if (err)
|
|
|
|
|
goto free_dpaa_bps;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* Create a congestion group for this netdev, with
|
|
|
|
|
* dynamically-allocated CGR ID.
|
|
|
|
|
* Must be executed after probing the MAC, but before
|
|
|
|
|
* assigning the egress FQs to the CGRs.
|
|
|
|
|
*/
|
|
|
|
|
err = dpaa_eth_cgr_init(priv);
|
|
|
|
|
if (err < 0) {
|
|
|
|
|
dev_err(dev, "Error initializing CGR\n");
|
2017-10-16 21:36:08 +03:00
|
|
|
goto free_dpaa_bps;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
err = dpaa_ingress_cgr_init(priv);
|
|
|
|
|
if (err < 0) {
|
|
|
|
|
dev_err(dev, "Error initializing ingress CGR\n");
|
2017-10-16 21:36:08 +03:00
|
|
|
goto delete_egress_cgr;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Add the FQs to the interface, and make them active */
|
|
|
|
|
list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) {
|
|
|
|
|
err = dpaa_fq_init(dpaa_fq, false);
|
|
|
|
|
if (err < 0)
|
2017-10-16 21:36:08 +03:00
|
|
|
goto free_dpaa_fqs;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
2020-11-02 20:34:36 +02:00
|
|
|
priv->tx_headroom = dpaa_get_headroom(priv->buf_layout, TX);
|
|
|
|
|
priv->rx_headroom = dpaa_get_headroom(priv->buf_layout, RX);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
/* All real interfaces need their ports initialized */
|
2019-10-31 16:37:47 +02:00
|
|
|
err = dpaa_eth_init_ports(mac_dev, dpaa_bp, &port_fqs,
|
2017-02-13 17:20:01 +02:00
|
|
|
&priv->buf_layout[0], dev);
|
|
|
|
|
if (err)
|
2017-10-16 21:36:08 +03:00
|
|
|
goto free_dpaa_fqs;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2017-08-27 16:13:41 +03:00
|
|
|
/* Rx traffic distribution based on keygen hashing defaults to on */
|
|
|
|
|
priv->keygen_in_use = true;
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv);
|
|
|
|
|
if (!priv->percpu_priv) {
|
|
|
|
|
dev_err(dev, "devm_alloc_percpu() failed\n");
|
|
|
|
|
err = -ENOMEM;
|
2017-10-16 21:36:08 +03:00
|
|
|
goto free_dpaa_fqs;
|
2016-11-15 10:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
2016-07-25 16:38:21 +03:00
|
|
|
priv->num_tc = 1;
|
2024-07-14 01:53:33 +03:00
|
|
|
netif_set_real_num_tx_queues(net_dev,
|
|
|
|
|
priv->num_tc * dpaa_num_txqs_per_tc());
|
2016-07-25 16:38:21 +03:00
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
/* Initialize NAPI */
|
|
|
|
|
err = dpaa_napi_add(net_dev);
|
|
|
|
|
if (err < 0)
|
2017-10-16 21:36:08 +03:00
|
|
|
goto delete_dpaa_napi;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout);
|
|
|
|
|
if (err < 0)
|
2017-10-16 21:36:08 +03:00
|
|
|
goto delete_dpaa_napi;
|
2016-11-15 10:41:02 +02:00
|
|
|
|
2016-11-15 10:41:05 +02:00
|
|
|
dpaa_eth_sysfs_init(&net_dev->dev);
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
netif_info(priv, probe, net_dev, "Probed interface %s\n",
|
|
|
|
|
net_dev->name);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
2017-10-16 21:36:08 +03:00
|
|
|
delete_dpaa_napi:
|
2016-11-15 10:41:02 +02:00
|
|
|
dpaa_napi_del(net_dev);
|
2017-10-16 21:36:08 +03:00
|
|
|
free_dpaa_fqs:
|
2016-11-15 10:41:02 +02:00
|
|
|
dpaa_fq_free(dev, &priv->dpaa_fq_list);
|
|
|
|
|
qman_delete_cgr_safe(&priv->ingress_cgr);
|
|
|
|
|
qman_release_cgrid(priv->ingress_cgr.cgrid);
|
2017-10-16 21:36:08 +03:00
|
|
|
delete_egress_cgr:
|
2016-11-15 10:41:02 +02:00
|
|
|
qman_delete_cgr_safe(&priv->cgr_data.cgr);
|
|
|
|
|
qman_release_cgrid(priv->cgr_data.cgr.cgrid);
|
2017-10-16 21:36:08 +03:00
|
|
|
free_dpaa_bps:
|
2016-11-15 10:41:02 +02:00
|
|
|
dpaa_bps_free(priv);
|
2017-10-16 21:36:08 +03:00
|
|
|
free_netdev:
|
2016-11-15 10:41:02 +02:00
|
|
|
dev_set_drvdata(dev, NULL);
|
|
|
|
|
free_netdev(net_dev);
|
2017-10-16 21:36:08 +03:00
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-10 09:19:40 +02:00
|
|
|
static void dpaa_remove(struct platform_device *pdev)
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
struct net_device *net_dev;
|
|
|
|
|
struct dpaa_priv *priv;
|
|
|
|
|
struct device *dev;
|
|
|
|
|
int err;
|
|
|
|
|
|
2019-10-23 12:08:44 +03:00
|
|
|
dev = &pdev->dev;
|
2016-11-15 10:41:02 +02:00
|
|
|
net_dev = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
|
|
priv = netdev_priv(net_dev);
|
|
|
|
|
|
2016-11-15 10:41:05 +02:00
|
|
|
dpaa_eth_sysfs_remove(dev);
|
|
|
|
|
|
2016-11-15 10:41:02 +02:00
|
|
|
dev_set_drvdata(dev, NULL);
|
|
|
|
|
unregister_netdev(net_dev);
|
net: dpaa: Convert to phylink
This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).
The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.
The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.
The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII. I have left it
unimplemented for now.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-17 16:22:38 -04:00
|
|
|
phylink_destroy(priv->mac_dev->phylink);
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
|
2023-07-10 09:19:39 +02:00
|
|
|
if (err)
|
|
|
|
|
dev_err(dev, "Failed to free FQs on remove (%pE)\n",
|
|
|
|
|
ERR_PTR(err));
|
2016-11-15 10:41:02 +02:00
|
|
|
|
|
|
|
|
qman_delete_cgr_safe(&priv->ingress_cgr);
|
|
|
|
|
qman_release_cgrid(priv->ingress_cgr.cgrid);
|
|
|
|
|
qman_delete_cgr_safe(&priv->cgr_data.cgr);
|
|
|
|
|
qman_release_cgrid(priv->cgr_data.cgr.cgrid);
|
|
|
|
|
|
|
|
|
|
dpaa_napi_del(net_dev);
|
|
|
|
|
|
|
|
|
|
dpaa_bps_free(priv);
|
|
|
|
|
|
|
|
|
|
free_netdev(net_dev);
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-13 16:42:08 +05:30
|
|
|
static const struct platform_device_id dpaa_devtype[] = {
|
2016-11-15 10:41:02 +02:00
|
|
|
{
|
|
|
|
|
.name = "dpaa-ethernet",
|
|
|
|
|
.driver_data = 0,
|
|
|
|
|
}, {
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(platform, dpaa_devtype);
|
|
|
|
|
|
|
|
|
|
static struct platform_driver dpaa_driver = {
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = KBUILD_MODNAME,
|
|
|
|
|
},
|
|
|
|
|
.id_table = dpaa_devtype,
|
|
|
|
|
.probe = dpaa_eth_probe,
|
2024-10-03 12:01:03 +02:00
|
|
|
.remove = dpaa_remove
|
2016-11-15 10:41:02 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int __init dpaa_load(void)
|
|
|
|
|
{
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
pr_debug("FSL DPAA Ethernet driver\n");
|
|
|
|
|
|
|
|
|
|
/* initialize dpaa_eth mirror values */
|
|
|
|
|
dpaa_rx_extra_headroom = fman_get_rx_extra_headroom();
|
|
|
|
|
dpaa_max_frm = fman_get_max_frm();
|
|
|
|
|
|
|
|
|
|
err = platform_driver_register(&dpaa_driver);
|
|
|
|
|
if (err < 0)
|
|
|
|
|
pr_err("Error, platform_driver_register() = %d\n", err);
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
module_init(dpaa_load);
|
|
|
|
|
|
|
|
|
|
static void __exit dpaa_unload(void)
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{
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platform_driver_unregister(&dpaa_driver);
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/* Only one channel is used and needs to be released after all
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* interfaces are removed
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*/
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dpaa_release_channel();
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}
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module_exit(dpaa_unload);
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_DESCRIPTION("FSL DPAA Ethernet driver");
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